DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Item 420 in figure 4A is not referenced in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 15 is objected to because of the following informalities: Line 4 of this claim contains the word “de”, which should “die” or “dies”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4,7, 9, 10, 12, 13, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al, US Patent Application Publication 2017/0125379
Regarding claim 1, Chen teaches an apparatus, comprising:
a first IC die 200 comprising first metallization features (labeled 202 in figure 8) on a first side of the first IC die;
a second IC die 200 laterally adjacent to the first IC die, wherein the second IC die comprises second metallization features (labeled 202 in figure 8) on a first side of the second IC die;
a third IC die stacked 300 over the first and second IC die and comprising third metallization features (labeled 304 in figure 9) in direct contact with a first number of each of the first and second metallization features;
a package dielectric material (labeled 400 in figure 12) adjacent to the third IC die and over the first side of each of the first and second IC dies;
a routing structure 600 within the package dielectric material, the routing structure comprising fourth metallization features in contact with a second number of each of the first and second metallization features, and terminating at first-level interconnect interfaces (as shown in figures 12-13).
Regarding claim 2, Chen teaches the third metallization features electrically interconnect the first IC die to the second IC die (figure 13, via 700A/700B)
Regarding claim 4, Chen teaches the package dielectric material has a first thickness at least equal to a second thickness of the third IC die, and wherein the fourth metallization features comprise vias extending through an entirety of the first thickness of the package dielectric material (figures 12-13).
Regarding claim 7, Chen teaches the third metallization features comprise a plurality of features directly bonded to the first number of first and second metallization features at a bond interface that is coincident with a plane passing through an interface of the fourth metallization features and the second number of first and second metallization features (figures 12-13).
Regarding claims 9-10, Chen teaches the fourth metallization features comprise predominantly Cu [0034] and the package dielectric comprises an organic polymer dielectric material surrounding the fourth metallization features, wherein the polymer dielectric material comprises at least one of epoxy, polyimide, or ABF [0026].
Regarding claim 12, Chen teaches a system comprising:
a plurality of laterally adjacent IC dies 200;
an interconnect bridge die 300 on a first side of the adjacent IC dies, the interconnect bridge die comprising metallization features (labeled 304 in figure 9) directly bonded to metallization features (labeled 202 in figure 8) within a first region of each of the plurality of laterally adjacent IC die;
a package dielectric material (labeled 400 in figure 12) over the interconnect bridge die and over second regions of each of the plurality of laterally adjacent IC die;
a routing structure 600 embedded within the package dielectric material, the routing structure comprising metallization features in contact with a second number of metallization features within a second region of each of the plurality of laterally adjacent IC die and terminating at first-level interconnect interfaces; and
a host component 700A interconnected to the first routing structure through first-level interconnects coupled to the first-level interconnect features 700B (figures 12-13).
Regarding claim 13, Chen teaches the first-level interconnect features comprise solder (figures 12-13)
Regarding claim 16, Chen teaches a method, comprising:
adhering a first IC die 200 and a second IC die 200 adjacent to each other on a glass substrate 100 (figure 2 and [0012]);
attaching a third IC die 300 to a first number of metallization features on a first side of the first and second IC dies, the third IC die spanning a portion of the glass substrate between the first and second IC dies (figure 3);
building up second metallization features 600 within a package dielectric material adjacent to the third IC die and contacting a second number of the metallization features on the first side of the first and second IC dies, the second metallization features terminating at first level interconnect interfaces (figure 6); and
removing the glass substrate after building up the second metallization features to expose a second side of the first IC die and the second IC die (figure 13).
Regarding claim 17, Chen teaches attaching the third IC die further comprises directly bonding a first portion of the third IC die to a first portion of the first IC die concurrently with directly bonding a second portion of the third IC die to a first portion of the second IC die (figure 3)
Regarding claim 18, Chen teaches building up the second metallization features within the package dielectric material comprises applying an organic material over a second portion of the first IC die concurrently with a second portion of the second IC die and curing the organic material [0026].
Regarding claim 19, Chen teaches building up the second metallization features within the package dielectric material comprises planarizing the package dielectric material over a top surface of the third IC die (as shown in figure 4).
Regarding claim 20, Chen teaches building up the second metallization features within the package dielectric material comprises forming first vias 500 through the package dielectric material and in contact with the second number of metallization features on the first side of the first IC die and the second IC die (figure 5).
Claim(s) 1, 2, 6, 7, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teh et al, US Patent Application Publication 2014/0159228
Regarding claim 1, Teh teaches an apparatus, comprising:
a first IC die 102A comprising first metallization features 104A,116A on a first side of the first IC die;
a second IC die 102B laterally adjacent to the first IC die, wherein the second IC die comprises second metallization features 104B, 116B on a first side of the second IC die;
a third IC die 114 stacked over the first and second IC die and comprising third metallization features 116C/116D in direct contact with a first number of each of the first and second metallization features;
a package dielectric material 108A/108B/108C adjacent to the third IC die and over the first side of each of the first and second IC dies;
a routing structure 106/104C within the package dielectric material, the routing structure comprising fourth metallization features in contact with a second number of each of the first and second metallization features, and terminating at first-level interconnect interfaces (figure 5D).
Regarding claim 2, Teh teaches the third metallization features electrically interconnect the first IC die to the second IC die (figure 5D)
Regarding claim 6, Ten teaches the fourth metallization features comprise redistribution lines 104C/104D/104E and overlying vias 106 embedded within a layer of the package dielectric material, the redistribution lines in contact with, and fanning out from, the vias (figure 5D)
Regarding claim 7, Teh teaches the third metallization features comprise a plurality of features 116D, 116C directly bonded to the first number of first and second metallization features at a bond interface that is coincident with a plane passing through an interface of the fourth metallization features and the second number of first and second metallization features (figure 5D).
Regarding claim 11, Teh teaches the package dielectric material 108A is absent from between a first sidewall of the first IC die facing a second sidewall of the second IC die (figure 5D)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Kalandar et al, US Patent 9,034,694.
Regarding claim 3, Chen teaches a surface of the first substrate is substantially coplanar with a surface of the second substrate; and a thickness of the first IC die is substantially equal to a thickness of the second IC die (figures 12-13).
Chen fails to teach a second side of the first IC dies comprises a crystalline first die substrate and the second side of the second IC comprises a crystalline second die substrate.
However, Kalandar teaches that integrated circuit dies may be made of semiconductor materials, such as monocrystalline silicon (see column 2, lines 24-28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kalandar with that of Chen because monocrystalline silicon is one of several conventionally-used materials in forming integrated circuit dies.
Regarding claim 5, Chen teaches the third IC die comprises a through substrate via (TSV) 302 (as labeled in figure 11) extending through the die substrate; the TSV is coupled to the third metallization features; the package dielectric has a second thickness over a second side of the third IC die; and the fourth metallization features comprise a via in contact with the TSV (with the contact being electrical contact via 700A and 700B)
Chen fails to teach a second side of the third IC die comprises a crystalline die substrate.
However, Kalandar teaches that integrated circuit dies may be made of semiconductor materials, such as monocrystalline silicon (see column 2, lines 24-28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kalandar with that of Chen because monocrystalline silicon is one of several conventionally-used materials in forming integrated circuit dies.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teh as applied to claim 1 above, and further in view of Chia et al, US Patent 7,712,211.
Regarding claim 8, Teh teaches the third IC die 114 is a passive die lacking any transistors within a device layer (figure 5D).
Teh fails to teach each of the first and second IC dies further comprises a device layer over a crystalline die substrate on a second side of first and second IC dies.
However, Chia teaches a conventionally-structured die, which contains a device layer (active area) over a crystalline die substrate (substrate) on a second side of first and second IC dies (see figure 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chia with that of Teh because it is generally-known in the art that integrated circuit dies contain an active layer over a monocrystalline silicon substrate.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 13 above, and further in view of Koepf, US Patent 5,138,436
Regarding claims 14 and 15, Chen teaches the interconnect bridge die comprises a plurality of through substrate vias (TSVs) 302 coupled to the metallization features within the first region of each of the plurality of laterally adjacent IC de (figures 12-13)
Chen fails to teach a power supply coupled through the host component to provide power to the plurality of adjacent IC dies and power supply is coupled to the plurality of adjacent IC dies through the TSVs.
However, Koepf teaches that interconnects of the integrated dies are connected to various input/output interconnects and terminals to the power supply, which is required in order for these electrical devices to operate (column 5, lines 26-34), thereby meeting the limitations of “power supply coupled through the host component to provide power to the plurality of adjacent IC dies and power supply is coupled to the plurality of adjacent IC dies through the TSVs”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Koepf with that of Chen because interconnects of the integrated dies are connected to various input/output interconnects and terminals to the power supply, which is required in order for these electrical devices to operate
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899