CTFR 18/091,265 CTFR 81546 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The Specification submitted 6 May 2026 is accepted Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 2, 4, 6, 7, 9, 10, 12, 13, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US Patent Application Publication 2017/0125379 (as cited in previous Office Action) in view of Lin, US Patent 9,087,821 (newly submitted) . Regarding claim 1, Chen teaches an apparatus, comprising: a first integrated circuit (IC) die 200 comprising first metallization features (labeled 202 in figure 8) on a first side of the first IC die; a second IC die 200 laterally adjacent to the first IC die, wherein the second IC die comprises second metallization features (labeled 202 in figure 8) on a first side of the second IC die; a third IC die stacked 300 over the first and second IC die and comprising third metallization features (labeled 304 in figure 9) on a first side of the third IC die, wherein the third IC die is bonded to each of the first IC die and the second IC die, a package dielectric material ( labeled 400 in figure 12 ) adjacent to the third IC die and over the first side of each of the first and second IC dies; a routing structure 600 within the package dielectric material, the routing structure comprising fourth metallization features in contact with a second number of each of the first and second metallization features, and terminating at interconnect interfaces ( as shown in figures 12-13 ). Chen fails to teach the metallization features are embedded within an insulator for each of the IC layers and bonding the third IC die to the first IC die and second IC die is hybrid bonding, wherein the third metallization features are fused with a first number of each of the first and second metallization features at a hybrid bond interface further comprising chemically bonded dielectric material. However, Lin teaches the use of hybrid bonding as an effective means of providing a studier, permanent connection for IC dies by fuse bonding the metal layer and the dielectric layers of different dies together. Lin teaches the metallization features 144 , 244, 124 224, are embedded within an insulator 126, 146, 246, 226 for each of the IC layers,. Combining the hybrid bonding of Lin ( as shown in figure 2C ) with the reference of Chen would then meet the limitations of bonding the third IC die 100 to the first IC die and second IC die ( represented as 200’ ) is hybrid bonding, wherein the third metallization features are fused with a first number of each of the first and second metallization features at a hybrid bond interface further comprising chemically bonded dielectric material ( as bonding interface 150 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with that of Chen because hybrid bonding as an effective means of providing a studier, permanent connection for IC dies that allows for more advance 3D stacking of dies, thereby improving the semiconductor device. Regarding claim 2, Chen teaches the third metallization features electrically interconnect the first IC die to the second IC die ( figure 13, via 700A/700B ) Regarding claim 4, Lin teaches the fourth metallization features 600 comprise first vias extending through the first layer of package dielectric material, the first vias in contact with a second number of each of the first and second metallization (figures 12-13) Lin and Chen fails to teach the package dielectric material comprises a first layer of dielectric material that has a first thickness exceeding a second thickness of the third IC die. However, given the teaching of the references, it would have been obvious to determine the optimum thickness of the layers involved because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See In re Aller, Lacey, and Hall (10 USPQ 23 3-237) "It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of ether the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that tile chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091,231 USPQ 375 (Fed. Cir. 1986). Appellants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992). An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979). Regarding claim 6, Lin teaches the fourth metallization features comprise redistribution lines 510 embedded within a layer of the package dielectric material 520 , the redistribution lines coupling the first and second vias to the interconnect interfaces (figure 1D). Regarding claim 7, Chen in view of Lin teaches hybrid bond interface is coincident with a plane passing through an interface of the first vias and the second number of first and second metallization features ( using hybrid bonding of Lin with figures 12-13 of Chen, which would substitute the solder balls for the hybrid bonding ). Regarding claims 9-10, Chen teaches the fourth metallization features comprise predominantly Cu [0034] and the package dielectric comprises an organic polymer dielectric material surrounding the fourth metallization features, wherein the polymer dielectric material comprises at least one of epoxy , polyimide, or ABF [0026] . Regarding claim 12, Chen teaches a system comprising: a plurality of laterally adjacent IC dies 200 , with each of the IC dies comprising first metallization features; an interconnect bridge die 300 on a first side of each of the adjacent IC dies, the interconnect bridge die comprising second metallization features (labeled 304 in figure 9) are bonded within a first region of each of the plurality of laterally adjacent IC die; a package dielectric material ( labeled 400 in figure 12 ) over the interconnect bridge die and over second regions of each of the plurality of laterally adjacent IC die; a routing structure 600 embedded within the package dielectric material, the routing structure comprising third metallization features in contact with a second number of the first metallization features within a second region of each of the plurality of laterally adjacent IC dies and terminating at interconnect interfaces; and a host component 700A interconnected to the first routing structure through interconnects coupled to the interconnect features 700B ( figures 12-13 ). Chen fails to teach the metallization features are embedded within an insulator for each of the IC layers and the second metallization features are fused with a first number of first metallization features at a hybrid bond interface. However, Lin teaches the use of hybrid bonding as an effective means of providing a studier, permanent connection for IC dies by fuse bonding the metal layer and the dielectric layers of different dies together. Lin teaches the metallization features 144 , 244, 124 224, are embedded within an insulator 126, 146, 246, 226 for each of the IC layers. Combining the hybrid bonding of Lin ( as shown in figure 2B ) with the reference of Chen would then meet the limitation of the second metallization features 144 are fused with a first number of first metallization features 244 at a hybrid bond interface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with that of Chen because hybrid bonding as an effective means of providing a studier, permanent connection for IC dies that allows for more advance 3D stacking of dies, thereby improving the semiconductor device. Regarding claim 13, Chen teaches the interconnect features comprise solder ( figures 12-13 ) Regarding claim 16, Chen teaches a method, comprising: adhering a first IC die 200 and a second IC die 200 adjacent to each other on a glass substrate 100 (figure 2 and [0012]) ; bonding a third IC die 300 to a first side of the first and second IC dies, the third IC die spanning a portion of the glass substrate between the first and second IC dies ( figure 3 ); building up second metallization features 600 within a package dielectric material adjacent to the third IC die and contacting a second number of the first metallization features on the first side of the first and second IC dies, the second metallization features terminating at interconnect interfaces ( figure 6 ); and removing the glass substrate after building up the second metallization features to expose a second side of the first IC die and the second IC die ( figure 13 ). Chen fails to teach the bonding is hybrid bonding, wherein the hybrid bonding sinters metallization features of the third IC die with a first number of first metallization features of each of the first and second IC dies and bonds dielectric material of the third IC die with dielectric material of each of the first and second IC dies However, Lin teaches the use of hybrid bonding as an effective means of providing a studier, permanent connection for IC dies by fuse bonding the metal layer and the dielectric layers of different dies together. Lin teaches the hybrid bonding sinters metallization features of the third IC die with a first number of first metallization features of each of the first and second IC dies and bonds dielectric material of the third IC die with dielectric material of each of the first and second IC dies ( see column 4, line 62- to column 5, line 27 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin with that of Chen because hybrid bonding as an effective means of providing a studier, permanent connection for IC dies that allows for more advance 3D stacking of dies, thereby improving the semiconductor device. Regarding claim 18, Chen teaches building up the second metallization features within the package dielectric material comprises applying an organic material over a second portion of the first IC die concurrently with both a second portion of the second IC die and the third IC die, and curing the organic material [0026 ]. Regarding claim 19, Chen teaches building up the second metallization features within the package dielectric material comprises planarizing the package dielectric material over a top surface of the third IC die ( as shown in figure 4 ) . 07-22-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Lin as applied to claim 1 above, and further in view of Kalandar et al, US Patent 9,034,694 (as cited in previous Office Action) . Regarding claim 3, Chen teaches a surface of the first substrate is substantially coplanar with a surface of the second substrate; and a thickness of the first IC die is substantially equal to a thickness of the second IC die ( figures 12-13 ). Chen and Lin fail to teach a second side of the first IC die comprises a crystalline first die substrate and the second side of the second IC die comprises a crystalline second die substrate. However, Kalandar teaches that integrated circuit dies may be made of semiconductor materials, such as monocrystalline silicon (see column 2, lines 24-28). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kalandar with that of Chen and Lin because monocrystalline silicon is one of several conventionally-used materials in forming integrated circuit dies . 07-22-aia AIA Claim (s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen and Lin as applied to claim 13 above, and further in view of Koepf, US Patent 5,138,436 (as cited in previous Office Action) Regarding claims 14 and 15, Chen teaches the interconnect bridge die comprises a plurality of through substrate vias (TSVs) 302 coupled to the first number of metallization features within the first region of each of the plurality of laterally adjacent IC dies ( figures 12-13 ) Chen and Lin fail to teach a power supply coupled through the host component to provide power to the plurality of adjacent IC dies and power supply is coupled to the plurality of adjacent IC dies through the TSVs. However, Koepf teaches that interconnects of the integrated dies are connected to various input/output interconnects and terminals to the power supply, which is required in order for these electrical devices to operate (column 5, lines 26-34), thereby meeting the limitations of “power supply coupled through the host component to provide power to the plurality of adjacent IC dies and power supply is coupled to the plurality of adjacent IC dies through the TSVs” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Koepf with that of Chen and Lin because interconnects of the integrated dies are connected to various input/output interconnects and terminals to the power supply, which is required in order for these electrical devices to operate Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5, 8, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 12, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale E Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. QVJ /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/091,265 Page 2 Art Unit: 2899 Application/Control Number: 18/091,265 Page 3 Art Unit: 2899 Application/Control Number: 18/091,265 Page 4 Art Unit: 2899 Application/Control Number: 18/091,265 Page 5 Art Unit: 2899 Application/Control Number: 18/091,265 Page 6 Art Unit: 2899 Application/Control Number: 18/091,265 Page 7 Art Unit: 2899 Application/Control Number: 18/091,265 Page 8 Art Unit: 2899 Application/Control Number: 18/091,265 Page 9 Art Unit: 2899 Application/Control Number: 18/091,265 Page 10 Art Unit: 2899 Application/Control Number: 18/091,265 Page 11 Art Unit: 2899 Application/Control Number: 18/091,265 Page 12 Art Unit: 2899
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