Prosecution Insights
Last updated: May 29, 2026
Application No. 18/091,349

PACKAGE SUBSTRATE HAVING DEPRESSION

Final Rejection §102§103§112
Filed
Dec 29, 2022
Examiner
MOJADDEDI, OMAR F
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
458 granted / 512 resolved
+21.5% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
546
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
86.5%
+46.5% vs TC avg
§102
7.8%
-32.2% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 512 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant's election, without traverse, of claims 1-14 in the “Response to Restriction Requirement” filed on 07/08/2025 is acknowledged and entered by the Examiner. This office action consider claims 1-20 pending for prosecution, wherein claims 15-20 are withdrawn from further consideration, and claims 1-14 are presented for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 11 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 13, the instant claim recites limitations in view of the parent device claim 1, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein the depression region includes an indent that abuts the insulation material on one side, and the material is the mold compound” (Claim 11; emphasis added). The claim is indefinite because of the following: i) The claim is indefinite because “wherein the depression region includes an indent that abuts the insulation material on one side, and the material is the mold compound” (Claim 11) is ambiguous and unclear. Claim 1 includes the limitations that the “the depression region including a material” and “a mold compound covering the semiconductor die and the depression region”. Claim 11 includes the limitation “the material is the mold compound”. Thus, it is construed that “a mold compound covering the semiconductor die and the depression region, where depression is including a material. It is not clear if claim 11 is claiming the material and the mold compound are the same layer or whether they comprise of the same materials. Therefore, the limitation of “wherein the depression region includes an indent that abuts the insulation material on one side, and the material is the mold compound” (Claim 11) is indefinite and unclear. The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention. As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 2. Claims 1-7, 11-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aleksov et al. (US 20200219816 A1; hereinafter Aleksov). Regarding claim 1, Aleksov teaches a packaged integrated circuit (IC) (see the entire document, specifically Fig. 1+; [0003+], and as cited below), comprising: a package substrate (102; Fig. 1; [0030-0032]) having opposite first and second surfaces and including metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]) surrounded by an insulation material (see [0031], package substrate may include an insulating material such as carbon-doped dielectrics), the package substrate (102; Fig. 1; [0030-0032]) including a depression region (108; Fig. 1; [0030, 0032]; recess) that extends from the first surface, and the depression region (108; Fig. 1; [0030, 0032]; recess) including a material (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) different from the insulation material (see [0031], package substrate may include an insulating material such as carbon-doped dielectrics) and the metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]); a semiconductor die (114-2; Fig. 1; [0034-0035]) on part of the first surface adjacent to the depression region (108; Fig. 1; [0030, 0032]; recess), the semiconductor die (114-2; Fig. 1; [0034-0035]) including circuitry coupled to the metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]); and a mold compound (131; Fig. 1; [0046]; a thermally conductive material (e.g., metal particles) in a polymer) covering the semiconductor die (114-2; Fig. 1; [0034-0035]) and the depression region (108; Fig. 1; [0030, 0032]; recess). Regarding claim 2, Aleksov teaches all of the features of claim 1. Aleksov further comprising first metal pads (150-2; Fig. 1; [0039, 0045]) on the first surface and second metal pads (137; Fig. 1; [0044]) on the second surface, wherein the metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]) are electrically coupled between the first (150-2; Fig. 1; [0039, 0045]) and second metal pads (137; Fig. 1; [0044]), and the semiconductor die (114-2; Fig. 1; [0034-0035]) is mounted on the first metal pads (150-2; Fig. 1; [0039, 0045]). Regarding claim 3, Aleksov teaches all of the features of claim 2. Aleksov further teaches wherein the depression region (108; Fig. 1; [0030, 0032]; recess) is a cavity abutted by the insulation material (see Fig. 1; see [0031], package substrate may include an insulating material such as carbon-doped dielectrics) on at least two sides. Regarding claim 4, Aleksov teaches all of the features of claim 3. Aleksov further teaches wherein the material (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material that polymerizes) includes an epoxy polymer. Regarding claim 5, Aleksov teaches all of the features of claim 4. Aleksov further teaches wherein: the semiconductor die (114-2; Fig. 1; [0034-0035]) is a first semiconductor die; the packaged IC (Fig. 1) further comprises a second semiconductor die (114-4; Fig. 1; [0029, 0043]) on the first surface; the first semiconductor die (114-2; Fig. 1; [0034-0035]) is on a first side of the cavity (Fig. 1; [0030, 0032]; recess); the second semiconductor die (114-4; Fig. 1; [0029, 0043]) is on a second side of the cavity (Fig. 1; [0030, 0032]; recess) opposite to the first side; and the epoxy polymer (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material that polymerizes) (see below for “is configured as an optoisolator”) between the first (114-2; Fig. 1; [0034-0035]) and second semiconductor (114-4; Fig. 1; [0029, 0043]) dies. It is the Examiner’s position that the limitation of a "the epoxy polymer is configured as an optoisolator between the first and second semiconductor dies” is a functional limitation of the apparatus claimed. While features of an apparatus may be recited either structurally or functionally, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431- 32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959); MPEP 2114. Furthermore, because the device of Aleksov has all of the structural limitations of the claimed invention, the device is capable of operating in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Moreover, as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Aleksov teaches the structure of the claims as detailed above. Thus, Aleksov teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 6, Aleksov teaches all of the features of claim 1. Aleksov further teaches wherein the mold compound (131; Fig. 1; [0046]; a thermally conductive material (e.g., metal particles) in a polymer) is a first mold compound (131; Fig. 1; [0046]; a thermally conductive material (e.g., metal particles) in a polymer); and wherein the material (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) includes a second mold compound (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) different from the first mold compound (131; Fig. 1; [0046]; a thermally conductive material (e.g., metal particles) in a polymer). Regarding claim 7, Aleksov teaches all of the features of claim 6. Aleksov further teaches wherein the second mold compound (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) includes a resin and metal particles (150-1; Fig. 1; see [0045, 0048]; see [0048] for metal particles), in which the metal particles (150-1; Fig. 1; [0039, 0045]) are suspended in the resin. Regarding claim 11, Aleksov teaches all of the features of claim 1. Aleksov further teaches wherein the depression region (108; Fig. 1; [0030, 0032]; recess) includes an indent that abuts the insulation material (see Fig. 1; see [0031], package substrate may include an insulating material such as carbon-doped dielectrics) on one side, and the material (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) is the mold compound (see section 1, above; 112(b) rejection). Regarding claim 12, Aleksov teaches all of the features of claim 1. Aleksov further teaches wherein the metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]) include a first metal, and the material (127; Fig. 1; [0029, 0045]; mold material such as an epoxy material) includes a second metal (150-1; Fig. 1; see [0045, 0048]; where 150-1 is embedded in 127) different from the first metal. Regarding claim 14, Aleksov teaches all of the features of claim 1. Aleksov further teaches wherein the mold compound (131; Fig. 1; [0046]; a thermally conductive material (e.g., metal particles) in a polymer) is a first mold compound, and the insulation material (see [0031], package substrate includes a dielectric material formed in multiple layers) includes at least one of: a build-up film or a second mold compound (see [0031], package substrate includes a dielectric material formed in multiple layers). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 3. Claim 13 is rejected under 35 U.S.C.103 as being unpatentable over Aleksov et al. (US 20200219816 A1; hereinafter Aleksov), in view the following statement Regarding claim 13, Aleksov teaches all of the features of claim 1. Aleksov further teaches wherein: the package substrate (102; Fig. 1; [0030-0032]) include multiple substrate layers (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias); each substrate layer (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias) includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias); the metal layers (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias) of adjacent substrate layers in contact with each other to form the metal interconnects (146; Fig. 1; [0030, 0032, 0039, 0043, 0056]); and the packaged IC (102; Fig. 1; [0030-0032]) includes (see below for “a first number of”) substrate layers (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias) below the depression region (108; Fig. 1; [0030, 0032]; recess), and (see below for “a second number of”) substrate layers (see [0031], package substrate includes a dielectric material formed in multiple layers and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias) abutting the depression region (108; Fig. 1; [0030, 0032]; recess), (see below for “the second number being higher than the first number”). As noted above, modified Tu (by Kim) does not expressly disclose “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number”. However, the Applicant has not presented persuasive evidence that the claimed “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number). Also, the Applicant has not shown that “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Therefore, no rationale is given that the invention will not function without “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number”. Thus, the claimed “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” is not critical to the invention. Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). PNG media_image1.png 18 19 media_image1.png Greyscale In view of the above, as there is no persuasive evidence that the particular configuration of “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” is significant. Thus, the claimed limitation of “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein: the package substrate include multiple substrate layers; each substrate layer includes a metal layer surrounded by the insulation material, the metal layer including at least one of a trace or a via; the metal layers of adjacent substrate layers in contact with each other to form the metal interconnects; and the packaged IC includes a first number of substrate layers below the depression region, and a second number of substrate layers abutting the depression region, the second number being higher than the first number” is not patentable over Aleksov. Allowable Subject Matter 4. Claim 8 (and claims dependent upon claim 8, namely claims 9-10) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form, and to include all of the limitations of the base claim and any intervening claims. 5. The following is a statement of reasons for the indication of allowable subject matter: A search of the prior art failed to disclose or reasonably suggest the limitations “wherein the depression region is a first cavity abutted by the insulation material on at least two sides; the package substrate further includes a second cavity and a third cavity each extending from the first surface; the first cavity is between the second and third cavities; and at least part of the second cavity and the third cavity filled with the second mold compound” of claim 8 (the individual limitations may be found just not in combination). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OMAR F MOJADDEDI/Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Dec 29, 2022
Application Filed
Oct 27, 2025
Non-Final Rejection mailed — §102, §103, §112
Feb 27, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+10.7%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 512 resolved cases by this examiner. Grant probability derived from career allowance rate.

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