Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 17, 2025 is being considered by the examiner.
Claim Objections
Applicant is advised that should claims 1, 5, and 6 be found allowable, claims 7, 9, and 11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first glass layer" in lines 6 and 9 and “the second glass layer in lines 7 and 9. Claim 11 also recites “the first glass layer” and “the second glass layer.” There is insufficient antecedent basis for this limitation in the claim as claim 7 refers to the glass layers as “a first glass panel” and “a second glass panel.” For the purpose of this action, the Examiner will consider “panel” and “layer” to mean the same thing and interpret the claims to read “the first glass panel” and “the second glass panel.”
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0020] recites “the conductive pillars 16” in line 10. Other recitations of the conductive pillars in the specification and drawings use reference number 20.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai (US 2020/0203266 A1) in view of Yu (CN 102820268 B).
With respect to claim 1, Iwai teaches in Fig. 21:
An integrated circuit device substrate (multilayer substrate 200D), comprising:
a first glass layer (glass layer 110),
a second glass layer (glass layer 110A);
a dielectric interface layer (adhesive layer 170, para. 77 and 78 teaches that the adhesive layer may be a polyimide resin with a glass filler) between the first glass layer (110) and the second glass layer (110A);
a conductive pillar (via 150 that includes metal layer 130 and conductive layer 140) extending through the first glass layer (110), the dielectric layer (170) and the second glass layer (110A),
wherein the conductive pillars (150) taper from a first diameter in the dielectric layer (170) to a second diameter in the first glass layer (110) and the second glass layer (110A) (see annotated Fig. 21),
and wherein the first diameter is greater than the second diameter.
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Iwai fails to teach:
and a plurality of conductive pillars
Yu teaches a glass substrate in which glass layers with multiple through glass vias that teaches in Fig. 11:
and a plurality of conductive pillars
Iwai teaches the claimed invention except that there is only one conductive pillar passing through the glass layers and dielectric layer. Yu teaches that it is known to include multiple conductive pillars passing through the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include multiple pillars in the device of Iwai as taught by Yu in order to provide additional connections at the top surface of the substrate, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
With respect to claim 2, Iwai further teaches:
wherein the dielectric interface layer comprises an inorganic material chosen from Si, C, N and mixtures and combinations thereof (para. 77-78, Iwai teaches that the adhesive layer comprises polyimide with glass filler. Polyimides include a class of compounds that definitionally include N and C. Iwai does not specify which type of glass is used as a filler but in para. 68 teaches the use of soda glass and quartz glass in the device, both of which include Si.)
With respect to claim 3, Iwai further teaches:
wherein the inorganic material is SiOx. (para. 77-78, Iwai teaches that the adhesive layer may include glass filler. Para. 68 teaches the use of quartz glass as a glass in this device, which has chemical formula SiO2)
With respect to claim 5, Iwai further teaches:
wherein the first glass layer and the second glass layer are independently chosen from SiO2, soda-lime glass, boro-silicate glass, and alumo-silicate glass. (For the glass layer 110, various glass materials such as alkali-free glass, soda glass, and quartz glass may be used.”)
The Examiner notes that the limitation “independently chosen” is a product-by-process limitation. The Examiner determines that “independently chosen” does not imply any additional structure beyond each glass layer being made from one of the claimed glasses.
With respect to claim 6, Iwai further teaches:
wherein the first glass panel and the second glass panel each have a thickness of less than about 500 microns (para. 82 “For example, the glass layer 110 having a thickness of 100 μm is prepared”)
With respect to claim 7, Iwai teaches in Fig. 21:
An integrated circuit device substrate (multilayer substrate 200D), comprising:
a first glass panel (glass layer 110),
a second glass panel (glass layer 110A);
a dielectric interface layer (adhesive layer 170, para. 77 and 78 teaches that the adhesive layer may be a polyimide resin with a glass filler) between the first glass panel (110) and the second glass panel (110A);
a conductive pillar (via 150 that includes metal layer 130 and conductive layer 140) extending through the first glass layer (110), the dielectric layer (170) and the second glass layer (110A),
wherein the conductive pillars (150) taper from a first diameter in the dielectric layer (170) to a second diameter in the first glass layer (110) and the second glass layer (110A) (see annotated Fig. 21),
and wherein the first diameter is greater than the second diameter.
Iwai fails to teach:
and a plurality of conductive pillars
Yu teaches a glass substrate in which glass layers with multiple through glass vias that teaches in Fig. 11:
and a plurality of conductive pillars
Iwai teaches the claimed invention except that there is only one conductive pillar passing through the glass layers and dielectric layer. Yu teaches that it is known to include multiple conductive pillars passing through the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include multiple pillars in the device of Iwai as taught by Yu in order to provide additional connections at the top surface of the substrate, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
With respect to claim 8, Iwai further teaches:
wherein the dielectric interface layer is chosen from SiOx and polyimides (para. 77-78, Iwai teaches that the adhesive layer comprises polyimide with glass filler.)
With respect to claim 9, Iwai further teaches:
wherein the first glass panel and the second glass panel each have a thickness of less than about 500 microns (para. 82 “For example, the glass layer 110 having a thickness of 100 μm is prepared”)
With respect to claim 10, Iwai further teaches:
further comprising an integrated circuit device (semiconductor chip 300) electrically interconnected with the conductive pillars (coupled to 150 through wiring layer 131A).
With respect to claim 11, Iwai further teaches:
wherein the first glass layer and the second glass layer are independently chosen from SiO2, soda-lime glass, boro-silicate glass, and alumo-silicate glass. (For the glass layer 110, various glass materials such as alkali-free glass, soda glass, and quartz glass may be used.”)
The Examiner notes that the limitation “independently chosen” is a product-by-process limitation. The Examiner determines that “independently chosen” does not imply any additional structure beyond each glass layer being made from one of the claimed glasses.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Iwai (US 2020/0203266 A1) in view of Yu (CN 102820268 B) as applied to independent claim 1 above and further in view of Wiemer (2006 1st Electronic Systemintegration Technology Conference).
With respect to claim 4, Iwai/Yu teaches all limitations of claim 1 upon which claim 4 depends. Iwai/Yu fails to teach:
wherein the dielectric interface layer comprises a polymeric material chosen from benzocyclobutene polymers, and mixtures and combinations thereof.
Wiemer teaches:
wherein the dielectric interface layer comprises a polymeric material chosen from benzocyclobutene polymers, and mixtures and combinations thereof. (Conclusion, “A low temperature adhesive bonding process with thin polymer intermediate layer is proposed and successfully demonstrated. Different bond temperatures between 210~250°C for BCB,” “this method can accommodate different substrates, such as silicon, glass, metals, and other semiconductor materials.”)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai/Yu to use benzocyclobuten polymers as the dielectric interface layer as taught by Wiemer, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Iwai (US 2020/0203266 A1).
With respect to claim 12, Yu teaches in Fig. 11:
A method for making a glass substrate suitable for mounting an integrated circuit device, the method comprising:
forming a first plurality of conductive pillars (conductive material filling body 105 and conductive bump 106) in a first glass panel (main body 101 on top of Fig. 11, which may be glass), wherein the first glass panel comprises a first dielectric layer (insulating layer 102);
forming a second plurality of conductive pillars (conductive material filling body 105 and conductive bump 106) in a second glass panel (main body 101 on bottom of Fig. 11, which may be glass), wherein the second glass panel comprises a second dielectric layer (insulating layer 102);
bonding the first dielectric layer to the second dielectric layer to form a dielectric interface layer (bonded through dielectric adhesion layer 115),
wherein the first plurality of conductive pillars are electrically interconnected with the second plurality of conductive pillars (bonded through bonding interface 114, “a compound formed by all the solder layers and buffer layers in the two bonding structures, as well as part of the conductive bumps 112 and part of the conductive bumps 113”),
Yu fails to teach:
and wherein the first plurality of conductive pillars and the second plurality of conductive pillars taper from a first diameter in the dielectric interface layer to a second diameter in the first glass layer and the second glass layer,
and wherein the first diameter is greater than the second diameter.
Iwai teaches:
and wherein the first plurality of conductive pillars and the second plurality of conductive pillars taper from a first diameter in the dielectric interface layer to a second diameter in the first glass layer and the second glass layer, (para. 69 “the through hole 120 is provided so as to penetrate between the surface 110a and a surface 110b in the glass layer 110. For example, a through hole 120 of a tsuzumi [hourglass] shape in which a middle portion between the surface 110a and the surface 110b of the glass layer 110 is constricted is provided” see annotated Fig. 21 above)
and wherein the first diameter is greater than the second diameter.
Yu discloses the claimed invention except for the shape of the conductive pillars. Iwai discloses that it is known in the art to provide a through glass vias with a tapered shape in a multi-layer glass stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the method of Yu with the via shape of Iwai for the purpose of increasing the surface area of the bonds. See MPEP 2144. Further, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 13, Yu further teaches:
further comprising aligning the first array of conductive pillars with the second array of conductive pillars prior to the bonding step (para. 87 “When two or more bonding structures need to be stacked (or bonded), simply align the solder layers on the bonding structures.”)
With respect to claim 15, Yu further teaches:
wherein either or both of the first plurality of conductive pillars and the second plurality of conductive pillars are formed within vias induced by a laser. (para. 72 “The method for forming the blind hole 121 in the front side of the body layer 101 generally includes deep etching methods, such as ICP (Inductively Coupled Plasma) etching, laser drilling, wet etching, etc.”
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Iwai (US 2020/0203266 A1) as applied to claim 13 above and further in view of Flemming (US 2021/0257741 A1).
With respect to claim 14, Yu/Iwai teaches all limitations of claim 13 upon which claim 14 depends. Yu/Iwai fails to teach:
wherein the aligning comprises registering a first fiducial on the first glass panel with a second fiducial on the second glass panel.
Flemming teaches:
wherein the aligning comprises registering a first fiducial on the first glass panel with a second fiducial on the second glass panel. (para. 10, “using alignment fiducials and etched keyed structure to align the first and second photodefinable glass substrate wafers”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Yu/Iwai with the teachings of Flemming to use fiducials to align two glass panels. The claim would have been obvious because the technique of using fiducials to assist in alignment during bonding was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Flemming. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Iwai (US 2020/0203266 A1) as applied to claim 12 above and further in view of Ungarish (International Journal of Adhesion and Adhesives, 1991) and Ametek-Coining (Solder Melting Temperature What is it, Why is it Important, 2020).
With respect to claim 16, Yu/Iwai teaches all limitations of claim 12 upon which claim 16 depends. Yu further teaches:
wherein the bonding comprises contacting the first dielectric layer and the second dielectric layer (contacted through the dielectric adhesive layer) at room temperature and subsequently annealing the glass substrate (para. 87 “When two or more bonding structures need to be stacked (or bonded), simply align the solder layers on the bonding structures. The areas between the bonding structures without solder can be filled with a common dielectric adhesive layer. Then, apply a certain pressure and temperature to these bonding structures, causing the solder layers on adjacent bonding structures to fuse together. The buffer layer in the adjacent bonding structure also integrates into the solder layer and forms a compound together with some of the conductive material in the conductive bump. At the same time, the dielectric adhesive layer filled between the bonding structures also solidifies together, thus achieving a dual bonding effect.”)
Yu does not specify what “a certain pressure and temperature” is and therefore does not teach:
at about 1000 C to about 5000 C.
Although Yu does not specify what “common dielectric adhesive” is used or the temperature that it cures at, Ungarish teaches that known dielectric adhesives cure in the claimed temperature range:
“Three film adhesives were included in the study: a high-temperature-curing epoxy (175°C cure), a low-temperature-curing epoxy (120°C cure) and a 175°C curing polyimide”
Yu also does not specify which solder is used for bonding the metal layers or the melting point. Ametek-Coining teaches that well known solders exist within the claimed temperature range:
“A manufacturer can solder a component or components using, for example a high Lead (Pb) solder alloy. These alloys melt in the 300° range. He can then do a secondary solder using a Tin Silver solder (SnAg), which melts in the 220° range. Finally, if necessary, he can do a third solder reflow using an Indium-based solder with a melting point in the 150°C range.”
It would be obvious to modify Yu/Iwai with the teachings of Ungarish and Ametek-Coining to choose solder and dielectric adhesive materials that melt and cure in the range of 100 – 500 degrees C and bond the glass substrates by annealing in the claimed range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as the dielectric adhesive taught by Ungaring and the solder taught by Ametek-Coining, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897