Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on February 10, 2026, April 28, 2026, and May 26, 2026 are being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed April 27, 2026. Claims 1-16 are amended. Claims 17-20 are newly added. The Examiner notes that claims 1-20 are examined.
Specification
The substitute specification filed April 27, 2026 is acceptable and has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, 9-11, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma (US 2011/0147059 A1).
The Examiner notes that the Ma shows only the deposition of the metal layer in the thru-holes for one of the embodiments in Fig. 13 and 14. Although this embodiment is different from the embodiment of Fig. 10G, the teachings of Fig. 13 is applicable to any of the embodiments of multi-layer glass core taught by Ma.
With respect to claim 1, Ma teaches in Fig. 10G:
A substrate (para. [0094] “multi-layer glass core in a substrate”), comprising:
a first glass layer (glass layer 1057b within two-layer structure 1008a);
a second glass layer (glass layer 1057b within two-layer structure 1008b);
a dielectric interface layer (bonding layer 1058x) between a first surface of the first glass layer (bottom surface of 1057b within 1008a) and a first surface of the second glass layer (top surface of 1057b within 1008b);
and conductive pillars (metal layer 1467, which may substantially fill the thru-holes according to para. [0066]) extending through the first glass layer (1057b within 1008a), the dielectric layer (1058x) and the second glass layer (1057b within 1008b),
wherein the conductive pillars taper from a first diameter (see annotated Fig. 10G) in the dielectric layer (1058x) to a second diameter at a second surface (top surface) of the first glass layer and at a second surface (bottom surface) of the second glass layer,
and wherein the first diameter is greater than the second diameter,
the second surface (top surface) of the first glass layer (1057 within 1008a) is farther away from the second glass layer (1057b within 1008b) than the first surface of the first glass layer,
and the second surface (bottom surface) of the second glass layer (1057b within 1008b) is farther away from the first glass layer (1057b within 1008a) than the first surface (bottom surface) of the second glass layer.
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With respect to claim 5, Ma further teaches:
wherein the first glass layer and the second glass layer include one or more of a material comprising silicon and oxygen, soda-lime glass, boro-silicate glass, and alumo-silicate glass. (para. [0028] “Examples of glass materials that may be used with the described embodiments include Pure silica (e.g., approximately 100% SiO2), soda-lime glass, boro-silicate glass, and alumo-silicate glass”)
With respect to claim 6, Ma further teaches:
wherein a thickness of each of the first glass layer and the second glass layer is less than about 500 microns (para [0040] “and in one embodiment each glass layer has a thickness of between approximately 50 and 200 micrometers”)
With respect to claim 17, Ma further teaches:
wherein an individual conductive pillar of the conductive pillars includes a conductive material extending across an entire width of the conductive pillar (para. [0066] “In another embodiment, the metal 1467 deposited over the seed layer 1466 substantially fills the thru-holes 1465.”)
With respect to claim 18, Ma further teaches:
wherein an individual conductive pillar (metal 1467) of the conductive pillars includes one or more conductive materials (metal 1467) extending continuously from the second surface of the first glass layer through the first glass layer, through the dielectric interface layer, through the second glass layer, and to the second surface of the second glass layer (metal extends along the full length of the multilayer glass core, see Fig. 14c).
With respect to claim 20, Ma further teaches:
wherein a pitch of the conductive pillars is less than about 50 microns. (para. [0102] “in one embodiment, a pitch of 50 micrometers or less may be achieved for die-to-package interconnects when using a multi-layer glass core substrate”)
With respect to claim 7, Ma teaches in Fig. 10G and Fig. 14:
An integrated circuit device substrate (para. [0094] “multi-layer glass core in a substrate”), comprising:
a glass panel arrangement (“multilayer glass core”), comprising:
a first glass panel (glass layer 1057b within two-layer structure 1008a);
a second glass panel (glass layer 1057b within two-layer structure 1008b);
a dielectric interface layer (bonding layer 1058x) between the first glass panel (1057b within 1008a) and the second glass panel (1057b within 1008b);
wherein the glass panel arrangement has a bottom surface (bottom surface of 1057b within 1008b) and a top surface (top surface of 1057b within 1008a) opposite the bottom surface,
the bottom surface is a surface of the first glass panel that is farther away from the second glass panel than all other surfaces of the first glass panel,
and the top surface is a surface of the second glass panel that is farther away from the first glass panel than all other surfaces of the second glass panel;
and conductive pillars (metal layer 1467, which may substantially fill the thru-holes according to para. [0066]) extending from the bottom surface to the top surface of the glass panel arrangement (thru-holes which are filled with conductive pillars extend throughout the entire multilayer core),
wherein the conductive pillars (metal layer 1467, which may substantially fill the thru-holes according to para. [0066]) taper from a first diameter in the dielectric interface layer to a second diameter at the bottom surface and at the top surface, and wherein the first diameter is greater than the second diameter (see annotated Fig. 10G for diameters of through holes that are filled by conductive layer in steps described in Fig. 13 and shown in Fig. 14 for another embodiment).
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With respect to claim 9, Ma further teaches:
wherein a thickness of each of the first glass panel and the second glass panel is less than about 500 microns (para [0040] “and in one embodiment each glass layer has a thickness of between approximately 50 and 200 micrometers”)
With respect to claim 10, Ma further teaches in Figs. 1-2:
further comprising an integrated circuit device (IC die 210) conductively with one or more of the conductive pillars (conductors 160, analogous to the conductive pillars in Fig. 14).
With respect to claim 11, Ma further teaches:
wherein the first glass panel and the second glass panel include one or more of soda-lime glass, boro-silicate glass, alumo-silicate glass, or a material comprising silicon and oxygen. (para. [0028] “Examples of glass materials that may be used with the described embodiments include Pure silica (e.g., approximately 100% SiO2), soda-lime glass, boro-silicate glass, and alumo-silicate glass”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ma (US 2011/0147059 A1) as applied to independent claims 1 and 7 above and further in view of Iwai (US 2020/0203266 A1).
With respect to claim 2, Ma teaches all limitations of claim 1 upon which claim 2 depends. Ma fails to teach:
wherein the dielectric interface layer comprises an inorganic material
With respect to claim 2, Iwai teaches:
wherein the dielectric interface layer comprises an inorganic material (para. 77-78, Iwai teaches that the adhesive layer comprises polyimide with glass filler. The glass filler is an inorganic material)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ma to use an inorganic material as at least a portion of the dielectric interface layer as taught by Iwai, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
With respect to claim 3, Iwai further teaches:
wherein the inorganic material includes silicon and oxygen. (para. 77-78, Iwai teaches that the adhesive layer may include glass filler. Para. 68 teaches the use of quartz glass as a glass in this device, which has chemical formula SiO2)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Ma in view of Iwai as explained above.
With respect to claim 8, Ma teaches all limitations of claim 7 upon which claim 8 depends. Ma fails to teach:
wherein the dielectric interface layer includes a material comprising silicon and oxygen or a polyimides
With respect to claim 8, Iwai teaches:
wherein the dielectric interface layer includes a material comprising silicon and oxygen or a polyimides (para. 77, Iwai teaches that the adhesive layer may comprise polyimide.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ma to use polyimide as taught by Iwai, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ma (US 2011/0147059 A1) as applied to independent claim 1 above and further in view of Wiemer (2006 1st Electronic Systemintegration Technology Conference).
With respect to claim 4, Ma teaches all limitations of claim 1 upon which claim 4 depends. Ma fails to teach:
wherein the dielectric interface layer comprises a polymeric material.
Wiemer teaches:
wherein the dielectric interface layer comprises a polymeric material. (Conclusion, “A low temperature adhesive bonding process with thin polymer intermediate layer is proposed and successfully demonstrated. Different bond temperatures between 210~250°C for BCB,” “this method can accommodate different substrates, such as silicon, glass, metals, and other semiconductor materials.”)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ma to use polymers as the dielectric interface layer as taught by Wiemer, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 12, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Ma (US 2011/0147059 A1).
With respect to claim 12, Yu teaches in Fig. 11:
A process of manufacturing a glass substrate for mounting an integrated circuit device, the process comprising:
forming a first plurality of conductive pillars (conductive material filling body 105 and conductive bump 106) extending from a first surface (top surface) of a first glass panel (main body 101 on top of Fig. 11, which may be glass) to a second surface (bottom surface) of the first glass panel, wherein the first glass panel comprises a first dielectric layer (insulating layer 102) at a first surface (top surface) of the first glass panel,
forming a second plurality of conductive pillars (conductive material filling body 105 and conductive bump 106) extending from a first surface (top surface) of a second glass panel (main body 101 on bottom of Fig. 11, which may be glass) to a second surface (bottom surface) of the second glass panel, wherein the second glass panel comprises a second dielectric layer (insulating layer 102);
bonding the first dielectric layer at the first surface (top surface) of the first glass panel (bottom panel) to the second dielectric layer at the second surface (bottom surface) of the second glass panel (top layer) to form a dielectric interface layer (bonded through dielectric adhesion layer 115),
wherein the first plurality of conductive pillars are aligned and bonded with the second plurality of conductive pillars (bonded through bonding interface 114, “a compound formed by all the solder layers and buffer layers in the two bonding structures, as well as part of the conductive bumps 112 and part of the conductive bumps 113”),
Yu fails to teach:
and wherein the first plurality of conductive pillars gradually and continuously decrease in diameter from a first diameter at the first surface of the first glass panel to a second diameter at the second surface of the first glass panel;
and wherein the second plurality of conductive pillars gradually and continuously decrease in diameter from the first diameter at the first surface of the second glass panel to the second diameter at the second surface of the second glass panel
Ma teaches in Figs. 10G and 14:
and wherein the first plurality of conductive pillars (portion of metal 1467 of Fig. 14 formed in the through hole within glass layer 1057b within 1008b in Fig. 10G) gradually and continuously decrease in diameter from a first diameter at the first surface of the first glass panel to a second diameter at the second surface of the first glass panel (thru-hole 1065 that is later filled with metal layer decreases in diameter from top of glass layer 1057b within 1008b to the bottom of the glass layer);
and wherein the second plurality of conductive pillars (portion of metal 1467 of Fig. 14 formed in the through hole within glass layer 1057b within 1008a in Fig. 10G) gradually and continuously decrease in diameter from the first diameter at the first surface of the second glass panel to the second diameter at the second surface of the second glass panel (thru-hole 1065 that is later filled with metal layer decreases in diameter from bottom of glass layer 1057b within 1008a to the top of the glass layer)
Yu discloses the claimed invention except for the shape of the conductive pillars. Ma discloses that it is known in the art to provide a through glass vias with a tapered shape in a multi-layer glass stack. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the method of Yu with the via shape of Ma for the purpose of increasing the surface area of the bonds and for the purpose of selecting etching techniques that naturally lead to tapered through vias when etched form one side of the glass. See MPEP 2144. Further, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have, since it has been held that adjusting the shape of an article involves only routine skill in the art. In re Dailey, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.
With respect to claim 13, Yu further teaches:
further comprising aligning the first plurality of conductive pillars with the second plurality of conductive pillars prior to bonding the first dielectric layer at the first surface of the first glass panel with the second dielectric layer at the first surface of the second glass panel (abstract “When two or more bonding structures need to be stacked (or bonded), simply align the solder layers on the bonding structures.”)
With respect to claim 15, Yu further teaches:
wherein either or both of the first plurality of conductive pillars and the second plurality of conductive pillars are formed within vias. (abstract “the conductive material filling body in the connecting hole”)
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Ma (US 2011/0147059 A1) as applied to claim 13 above and further in view of Flemming (US 2021/0257741 A1).
With respect to claim 14, Yu/Iwai teaches all limitations of claim 13 upon which claim 14 depends. Yu/Iwai fails to teach:
wherein the aligning comprises registering a first fiducial on the first glass panel with a second fiducial on the second glass panel.
Flemming teaches:
wherein the aligning comprises registering a first fiducial on the first glass panel with a second fiducial on the second glass panel. (para. 10, “using alignment fiducials and etched keyed structure to align the first and second photodefinable glass substrate wafers”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Yu/Ma with the teachings of Flemming to use fiducials to align two glass panels. The claim would have been obvious because the technique of using fiducials to assist in alignment during bonding was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement as taught by Flemming. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (CN 102820268 B) in view of Ma (US 2011/0147059 A1) as applied to claim 12 above and further in view of Ungarish (International Journal of Adhesion and Adhesives, 1991) and Ametek-Coining (Solder Melting Temperature What is it, Why is it Important, 2020).
With respect to claim 16, Yu/Ma teaches all limitations of claim 12 upon which claim 16 depends. Yu further teaches:
wherein the bonding comprises contacting the first dielectric layer and the second dielectric layer (contacted through the dielectric adhesive layer) at room temperature and subsequently annealing the glass substrate (para. 87 “When two or more bonding structures need to be stacked (or bonded), simply align the solder layers on the bonding structures. The areas between the bonding structures without solder can be filled with a common dielectric adhesive layer. Then, apply a certain pressure and temperature to these bonding structures, causing the solder layers on adjacent bonding structures to fuse together. The buffer layer in the adjacent bonding structure also integrates into the solder layer and forms a compound together with some of the conductive material in the conductive bump. At the same time, the dielectric adhesive layer filled between the bonding structures also solidifies together, thus achieving a dual bonding effect.”)
Yu does not specify what “a certain pressure and temperature” is and therefore does not teach:
at about 1000 C to about 5000 C.
Although Yu does not specify what “common dielectric adhesive” is used or the temperature that it cures at, Ungarish teaches that known dielectric adhesives cure in the claimed temperature range:
“Three film adhesives were included in the study: a high-temperature-curing epoxy (175°C cure), a low-temperature-curing epoxy (120°C cure) and a 175°C curing polyimide”
Yu also does not specify which solder is used for bonding the metal layers or the melting point. Ametek-Coining teaches that well known solders exist within the claimed temperature range:
“A manufacturer can solder a component or components using, for example a high Lead (Pb) solder alloy. These alloys melt in the 300° range. He can then do a secondary solder using a Tin Silver solder (SnAg), which melts in the 220° range. Finally, if necessary, he can do a third solder reflow using an Indium-based solder with a melting point in the 150°C range.”
It would be obvious to modify Yu/Ma with the teachings of Ungarish and Ametek-Coining to choose solder and dielectric adhesive materials that melt and cure in the range of 100 – 500 degrees C and bond the glass substrates by annealing in the claimed range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to look to analogous art teachings of alternative suitable or useful material such as the dielectric adhesive taught by Ungarish and the solder taught by Ametek-Coining, as the selection of a known material based on its suitability for intended purpose deemed obvious. See MPEP 2144.07.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ma (US 2011/0147059 A1) as applied to independent claim 1 above and further in view of Teig (WO 2019079625 A1).
With respect to claim 19, Ma teaches all limitations of claim 1 upon which claim 19 depends. Ma fails to teach:
wherein a pitch of the conductive pillars is less than about 5 microns.
Teig teaches:
wherein a pitch of the conductive pillars is less than about 5 microns (Claim 1, “at least two of the connections having a center-to-center pitch that is less than 5 microns.” Ma also teaches that the connections may be TGVs in some embodiments.)
Ma teaches the claimed invention except for the pitch of the conductive pillars. Teig teaches that it is known in the art to provide connection with a pitch of less than 5 microns. It would have been obvious to the ordinary artisan prior to the effective filing date of the invention to modify Ma to have conductive connections with a pitch of less than 5 microns for the purpose of miniaturizing a device and since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Response to Arguments
Applicant’s arguments, see page 7, filed April 27, 2026, with respect to claim objections, 112 rejections, and objection to specification have been fully considered and are persuasive. The claim objections, specification objections, and rejections under 35 U.S.C. § 112 have been withdrawn.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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