DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/28/2026 has been entered. Claims 1-20 remain pending in the application. Claims 15 and 18-20 have been withdrawn. Applicant’s amendments have overcome the 112(b) rejection of claim 6 as previously set forth in the Non-Final Office Action mailed on 06/09/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art of Yu et al., (United States Patent Application Publication Number, US 2011/0304999 A1) hereinafter referenced as Yu, in view of Haba et al., (United States Patent Application Publication Number, US 2013/0063918 A1), hereinafter referenced as Haba.
Regarding claim 1, Yu teaches an integrated circuit (IC) device substrate, comprising: a first layer (Fig.1J, element #10, paragraph [0012], rows 4-5) with a first mounting region and a second mounting region (Fig.3, rotated vertically with 180 degrees, first mounting region is the region where the second glass layer, left side element #30, is mounted and second mounting region is the region where element #50 is mounted; Fig.1J and 3 represent variations of the same IC device substrate), wherein the first layer comprises a first plurality of conductive pillars (Fig.1J, elements #20).
Yu teaches the first layer is a dielectric layer (paragraph [0012], rows 4-5). Yu does not teach the dielectric layer is a glass layer. Haba teaches a first layer is made of dielectric material and the dielectric material is glass (Fig.5A, element #30 in Fig.5A, paragraph [0038], rows 7-9, paragraph [0040], rows 1-2). Thus, both references Yu and Haba teach a substrate made of dielectric material used as an interposer. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the dielectric layer disclosed by Yu could have been replaced for the glass layer disclosed by Haba because both serve the same purpose of providing an interposer. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an interposer. Due to the glass properties, a glass interposer has high resistivity and low dielectric constant and therefore can reduce signal loss and crosstalk.
Yu further teaches a first dielectric layer on a major surface of the first dielectric layer (Fig.1J, element #22, paragraph [0014], rows 3-4), wherein the first plurality of conductive pillars extend through a thickness of the first dielectric layer (Fig.1J, elements #20 extend through the vertical thickness of element #22); a second glass layer over the first mounting region of the first glass layer (Fig.1J, element #30, paragraph [0015], rows 1-2), wherein the second glass layer comprises a second plurality of conductive pillars (Fig.1J, elements #40); and a second dielectric layer on a major surface of the second glass layer (Fig.1J, element #24, paragraph [0014], rows 7-8), wherein the second plurality of conductive pillars extend through a thickness of the second dielectric layer (Fig.1J, elements #40 extend through a vertical thickness of element #24), wherein the first dielectric layer is in physical contact with the second dielectric layer (Fig.1J. elements #22 and 24 are in physical contact), and wherein individual conductive pillars of the first plurality of conductive pillars are in physical contact with corresponding individual conductive pillars of the second plurality of conductive pillars (Fig.1J, elements #20 and #40 are in physical contact with each other).
Regarding claim 2, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection. In a different embodiment, Yu further teaches the IC device substrate of claim 1, wherein the major surface of the second glass layer is a first major surface of the second glass layer, the IC device substrate further includes conductive traces connected to at least a portion of the second plurality of conductive pillars, and the conductive traces terminate in solder bump mounting pads at a second major surface of the second glass layer (Fig.7, conductive traces, elements #60 are connected to elements #40 and terminate in solder bumps, elements #42, at the surface opposite the first major surface of the glass layer, element #30). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Yu and disclose the IC device substrate further includes conductive traces connected to at least a portion of the second plurality of conductive pillars, and the conductive traces terminate in solder bump mounting pads at a second major surface of the second glass layer. As disclosed by Yu, this allows the solder bumps to be misaligned with respect to the conductive pillars and be substantially uniformly distributed on the surface of the second glass layer (paragraph [0025], rows 7-12).
Regarding claim 3, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection. Yu further teaches the IC device substrate of claim 1, wherein each of the first dielectric layer and the second dielectric layer includes an inorganic material comprising one or more of silicon, carbon, and nitrogen (both layers #22 and #24 are made of silicon nitride, paragraph [0014], rows 3-4 and 7-8).
Regarding claim 6, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection. Yu further teaches the second glass layer includes one or more of silicon, soda-lime glass, boro-silicate glass, and alumo-silicate glass (paragraph [0015], rows 1-2). As noted in the obviousness rejection of claim 1, Haba teaches the first layer is a glass layer. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to disclose that the first glass layer also includes one or more of silicon, soda-lime glass, boro-silicate glass, and alumo-silicate glass. This would have been obvious to try, since the material compositions for the second glass layer as taught by Yu, would have had a reasonable expectation of success and would yield predictable results. A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product is not of innovation but of ordinary skill and common sense.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, and in view of Farooq et al., (United States Patent Number, US 9219023 B2) hereinafter referenced as Farooq and in view of Chao et al., (United States Patent Number, US 6063711 A) hereinafter referenced as Chao.
Regarding claim 4, the combination of Yu and Haba teaches the IC device substrate of claims 1 and 2 as set forth in the obviousness rejection. Yu further teaches the IC device substrate of claim 3, wherein the inorganic material includes silicon (both layers #22 and #24 are made of silicon nitride, paragraph [0014], rows 3-4 and 7-8). Yu teaches the two dielectric layers, are used as an etch stop when etching glass (glass is mostly composed of silicon oxide, paragraph [0017], rows 4-6). Yu does not teach wherein the inorganic material includes silicon and oxygen. Farooq teaches wherein the inorganic material includes silicon and oxygen (Fig.8, the first and second dielectric layers, elements #13, are oxynitride, column 4, rows 58-62). Chao teaches an oxynitride layer used as an etch stop when etching silicon oxide (abstract). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Farooq and Chao and disclose the inorganic material includes silicon and oxygen. As disclosed by Farook, oxynitride layers can be used to couple two substrates with conductive pillars extending through a thickness of the layers (Fig.8). Furthermore, as disclosed by Chao, the oxynitride layers can be used as an etch stop when etching silicon oxide (glass) and can be made thinner than silicon nitride layers as disclosed by Yu. Using oxynitride dielectric layers makes it possible to avoid cracking problems due to thicker nitride layers (Chao abstract).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, and in view of Chen et al., (United States Patent Application Publication Number, US 2022/0336393 A1) hereinafter referenced as Chen.
Regarding claim 5, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection. The combination of Yu and Haba does not teach the IC device substrate of claim 1, wherein each of the first dielectric layer and the second dielectric layer each includes a polymeric material comprising one or more of polyimide and benzocyclobutene polymers. Chen teaches, wherein the first dielectric layer and the second dielectric layer each comprise a polymeric material chosen from polyimide, benzocyclobutene polymers, and mixtures and combinations thereof (Fig.2C, element #24B and #58, paragraph [0028], rows 9-11, paragraph [0037], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Chen and disclose wherein the first dielectric layer and the second dielectric layer each comprise a polymeric material chosen from polyimide, benzocyclobutene polymers, and mixtures and combinations thereof. Dielectric layers made of polyimide or benzocyclobutene polymers have high thermal stability, high chemical resistance and are easy to process.
Claims 7, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, and in view of Liu et al., (United States Patent Application Publication Number, US 2023/0031430 A1) hereinafter referenced as Liu.
Regarding claim 7, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection. Yu further teaches the IC device substrate of claim 1, further comprising an integrated circuit device on the first dielectric layer in the second mounting region on the first glass layer (Fig.3, second mounting region is the region where element #50 is mounted; the first dielectric layer, element #22 is showed in Fig.1J; Fig.1J and 3 represent variations of the same IC device substrate). The combination of Yu and Haba does not teach wherein the integrated circuit device comprises a dielectric mounting layer bonded with the first dielectric layer. Liu teaches wherein the integrated circuit device comprises a dielectric mounting layer bonded to the first dielectric layer (Fig.3, integrated circuit device, element #202 has a dielectric layer, element #213, bonded to the first dielectric layer, element #113). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liu and disclose the integrated circuit device comprises a dielectric mounting layer bonded to the first dielectric layer. The dielectric layer allows the attachment of the integrated circuit device to the glass layer using hybrid bonding, which is known in the art for high interconnect density and reliability.
Regarding claim 9, Yu teaches an integrated circuit (IC) device substrate, comprising: a first layer (Fig.1J, element #10, paragraph [0012], rows 4-5) with a first mounting region, and a second mounting region (Fig.3, rotated vertically with 180 degrees, first mounting region is the region where the second glass layer, left side element #30, is mounted and second mounting region is the region where element #50 is mounted. Fig.1J and 3 represent variations of the same IC device substrate), wherein the first layer comprises a first plurality of conductive pillars (Fig.1J, elements #20).
Yu teaches the first layer is a dielectric layer (paragraph [0012], rows 4-5). Yu does not teach the first layer is a glass layer. Haba teaches a first layer is made of dielectric material and the dielectric material is glass (Fig.5A element #30, paragraph [0038], rows 7-9, paragraph [0040], rows 1-2). Thus, both references Yu and Haba teach a substrate made of dielectric material used as an interposer. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the dielectric layer disclosed by Yu could have been replaced for the glass layer disclosed by Haba because both serve the same purpose of providing an interposer. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an interposer. Due to the glass properties, a glass interposer has high resistivity and low dielectric constant and therefore can reduce signal loss and crosstalk.
Yu further teaches a first dielectric layer on a major surface of the first glass layer (Fig.1J, element #22, paragraph [0014], rows 3-4), wherein the first plurality of conductive pillars extend through a thickness of the first dielectric layer (Fig.1J, elements #20 extend through the vertical thickness of element #22); a second glass layer over the first mounting region on the first glass layer (Fig.3, element #30, paragraph [0015], rows 1-2), wherein the second glass layer comprises a second plurality of conductive pillars (Fig.3, elements #40), a second dielectric layer on a major surface of the second glass layer (Fig.1J, element #24, paragraph [0014], rows 7-8), wherein the second plurality of conductive pillars extend through a thickness of the second dielectric layer (Fig.1J, elements #40 extend through a vertical thickness of element #24), and wherein individual conductive pillars of the first plurality of conductive pillars are in physical contact with corresponding individual conductive pillars of the second plurality of conductive pillars (Fig.1J, elements #20 and #40 are in physical contact); and an integrated circuit device on the first dielectric layer in the second device mounting region on the first glass layer (Fig.3, second mounting region is the region where element #50 is mounted; the first dielectric layer, element #22 is showed in Fig.1J; Fig.1J and 3 represent variations of the same IC device substrate).
The combination of Yu and Haba does not teach wherein the integrated circuit device comprises a dielectric mounting layer bonded with the first dielectric layer. Liu teaches wherein the integrated circuit device comprises a dielectric mounting layer bonded to the first dielectric layer (Fig.3, integrated circuit device, element #202 has a dielectric layer, element #213, bonded to the first dielectric layer, element #113). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liu and disclose the integrated circuit device comprises a dielectric mounting layer bonded to the first dielectric layer. The dielectric layer allows the attachment of the integrated circuit device to the glass layer using hybrid bonding, which is known in the art for high interconnect density and reliability.
Regarding claim 11, the combination of Yu, Haba and Liu teaches the substrate of claim 9, as set forth in the obviousness rejection. Yu further teaches the IC device substrate of claim 9, wherein each of the first dielectric layer and the second dielectric layer includes an inorganic material comprising one or more of silicon, carbon, and nitrogen (both layers #22 and #24 are made of silicon nitride, paragraph [0014], rows 3-4 and 7-8).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, Liu and in view of Yim et al., (United States Patent Application Publication Number, US 2019/0006549 A1) hereinafter referenced as Yim.
Regarding claim 8, the combination of Yu and Haba teaches the IC device substrate of claim 1 as set forth in the obviousness rejection, and the combination of Yu, Haba and Liu teaches the substrate of claim 7, as set forth in the obviousness rejection. The combination of Yu, Haba and Liu does not teach the IC device substrate of claim 7, wherein the integrated circuit device comprises a photonic integrated circuit device. Yim teaches wherein the integrated circuit device comprises a photonic integrated circuit device (Fig.4, element #102, paragraph [0025], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yim and disclose the integrated circuit device comprises a photonic integrated circuit device. As disclosed by Yim, this allows the manufacture of highly integrated optical modules with a high bandwidth (paragraph [0002]).
Regarding claim 10, the combination of Yu, Haba and Liu teaches the substrate of claim 9, as set forth in the obviousness rejection. The combination of Yu, Haba and Liu does not teach the IC device substrate of claim 9, wherein the integrated circuit device includes a photonic integrated circuit device. Yim teaches wherein the integrated circuit device includes a photonic integrated circuit device (Fig.4, element #102, paragraph [0025], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yim and disclose the integrated circuit device includes a photonic integrated circuit device. As disclosed by Yim, this allows the manufacture of highly integrated optical modules with a high bandwidth (paragraph [0002]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, Liu, Farooq in view of Chao.
Regarding claim 12, the combination of Yu, Haba and Liu teaches the IC device substrate of claim 11 as set forth in the obviousness rejection. Yu further teaches the IC device substrate of claim 11, wherein the inorganic material includes silicon (both layers #22 and #24 are made of silicon nitride, paragraph [0014], rows 3-4 and 7-8). Yu teaches the two dielectric layers, are used as an etch stop when etching glass (glass is mostly composed of silicon oxide, paragraph [0017], rows 4-6). Yu does not teach wherein the inorganic material includes silicon and oxygen. Farooq teaches wherein the inorganic material includes silicon and oxygen (Fig.8, the first and second dielectric layers, elements #13, are oxynitride, column 4, rows 58-62). Chao teaches an oxynitride layer used as an etch stop when etching silicon oxide (abstract). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Farooq and Chao and disclose the inorganic material includes silicon and oxygen. As disclosed by Farook, oxynitride layers can be used to bond two substrates with conductive pillars extending through a thickness of the oxynitride layers (Fig.8). Furthermore, as disclosed by Chao, the oxynitride layers can be used as an etch stop when etching silicon oxide (glass) and can be made thinner than silicon nitride layers as disclosed by Yu. Using oxynitride dielectric layers makes it possible to avoid cracking problems due to thicker nitride layers (Chao abstract).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Haba, Liu and in view of Chen.
Regarding claim 13, the combination of Yu, Haba and Liu teaches the IC device substrate of claim 9 as set forth in the obviousness rejection. The combination of Yu, Haba and Liu does not teach the IC device substrate of claim 9, wherein each of the first dielectric layer and the second dielectric layer each includes a polymeric material. Chen teaches, wherein the first dielectric layer and the second dielectric layer each includes a polymeric material (Fig.2C, element #24B and #58, paragraph [0028], rows 9-11, paragraph [0037], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen and disclose wherein each of the first dielectric layer and the second dielectric layer each includes a polymeric material. Dielectric layers made of polymeric materials such as polyimide or benzocyclobutene polymers have high thermal stability, high chemical resistance and are easy to process.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq in view of Daquan et al., (Chinese Patent Publication CN 102820268 A) hereinafter referenced as Daquan.
Regarding claim 14, Farooq teaches a process of making a glass substrate suitable for mounting an integrated circuit device, the process comprising: providing a first layer (Fig.5, element #11) with a first mounting region and a second mounting region (Fig.5, first mounting region is the bottom region corresponding to elements #45, and the second mounting region is the bottom region where elements #31 is mounted), wherein the first layer comprises a first plurality of conductive pillars (Fig.5, elements #45), a first dielectric layer is on a major surface of the first layer (Fig.5, formed by elements #13 and 16), and the first plurality of conductive pillars extend through a thickness of the first dielectric layer (Fig.5, elements #45 extend through the vertical thickness of element #13); providing a second layer comprising a second plurality of conductive pillars (Fig.8, bottom layer comprises the pillars on the right side of the layer), wherein a second dielectric layer is on a major surface of the second layer (Fig.8, bottom layer #13), and the second plurality of conductive pillars extend through a thickness of the second dielectric layer (Fig.8, the pillars on the right side of the bottom layer extend through the vertical thickness of bottom element #13); and bonding the first dielectric layer with the second dielectric layer such that individual conductive pillars of the first plurality of conductive pillars are in physical contact with respective individual conductive pillars of the second plurality of conductive pillars (Fig.8, the pillars are in physical contact).
Farooq teaches the two layers are semiconductor layers (column 4, rows 1-3). Farook does not teach the two layers are glass layers. Daquan teaches two layers each comprising a plurality of conductive pillars bonded together (Fig.11), where the layers can be made of semiconductor or glass (paragraph [0021]). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Daquan and disclose where the two layers are glass layers. As compared to semiconductor layers, glass substrates offer superior mechanical stability, low warpage, and excellent high-frequency signal integrity.
Regarding claim 16, the combination of Farooq and Daquan teaches the process of claim 14 as set forth in the obviousness rejection. Farooq further teaches the process of claim 14, further comprising mounting an integrated circuit device on the first dielectric layer in the second mounting region of the first glass layer (Fig.5, element #31 is mounted in the second mounting region as defined in the rejection of claim 14), wherein the integrated circuit device comprises a dielectric mounting layer bonded with the first dielectric layer (Fig.5, element #33 is bonded to the element #16, column 8, rows 34-40).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq in view of Daquan and in view of Yim.
Regarding claim 17, the combination of Farooq and Daquan teaches the process of claims 14 and 16 as set forth in the obviousness rejection. The combination of Farooq and Daquan does not teach the process of claim 16 wherein the integrated circuit device comprises a photonic integrated circuit device. Yim teaches wherein the integrated circuit device comprises a photonic integrated circuit device (Fig.4, element #102, paragraph [0025], rows 7-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yim and disclose the integrated circuit device comprises a photonic integrated circuit device. As disclosed by Yim, this allows the manufacture of highly integrated optical modules with a high bandwidth (paragraph [0002]).
Response to Arguments
Applicant’s arguments filed on 08/28/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims 1, 9 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
