DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4-6, 10, 12, 14, 15, 21, and 23 have been amended.
Claims 1-25 have been examined.
The drawing and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 8, 12, 13, 17, 18, 21, 22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2019/0227798 by Plotnikov et al. (hereinafter referred to as “Plotnikov”).
Regarding claims 1, 12, and 21, taking claim 1 as representative, Plotnikov discloses:
an apparatus comprising: decoder circuitry to decode an instance of a single instruction, the single instruction to at least include a prefix and an opcode to indicate execution circuitry is to do perform a particular operation, wherein the prefix comprises at least two bytes and a second of the at least two bytes of the prefix is to provide most significant bits for at least one register identifier, wherein a remainder of the identifier for at least one register are provided by one or more non-prefix fields of the instruction (Plotnikov discloses, at ¶ [0038], a processor with a decode unit to decode instructions. Plotnikov discloses, at Figure 13A and related description, the instruction includes a prefix of at least two bytes and opcode, wherein the second byte of the prefix includes MSBs to identify registers. Plotnikov also discloses, at Figure 13A and related description, the remainder of the identifiers is provided by non-prefix fields, e.g., the Reg field and SIB field. Plotnikov also discloses, at ¶ [0067], executing instructions that have been translated between instruction sets and, at ¶ [0058], storing instructions in memory.); and
execution circuitry to execute the decoded instance of the single according to the opcode to perform the particular operation (Plotnikov discloses, at ¶ [0038], the processor includes an execution unit to execute instructions, which discloses performing the operation according to the opcode.).
Regarding claims 2 and 22, taking claim 2 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
a first byte of the prefix is OxD5 (Plotnikov discloses, at Figure 13A and related description, a prefix having a first byte. The first byte can take any value between 0x00 and 0xFF, which encompasses 0x5D.).
Regarding claims 3 and 13, taking claim 3 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix is to be used in a 64-bit mode (Plotnikov discloses, at ¶ [0160], support for 64 bit mode.).
Regarding claims 7, 17, and 24, taking claim 7 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix is further to indicate usage of a new data destination by the single instruction (Plotnikov discloses, at ¶ [0150], the prefix provides for a three-operand syntax, which discloses indicating usage of a new data destination.).
Regarding claims 8 and 18, taking claim 8 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix comprises four bytes and is to indicate a new data destination (Plotnikov discloses, at Figure 15A and related description, using four bytes for the prefix and, at ¶ [0150], the prefix provides for a three-operand syntax, which discloses indicating usage of a new data destination.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 9, 14-16, 19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov.
Regarding claims 4, 14, and 23, taking claim 4 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
bit positions …of the second of the at least two bytes are to provide most significant bits for a register identifier (Plotnikov discloses, at Figure 13A and related description, the instruction includes a prefix, wherein the second byte of the prefix includes MSBs to identify registers.).
Plotnikov does not explicitly disclose the aforementioned bit positions are 6 and 2. However, the selection of the particular bits represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bits 6 and 2.
Regarding claims 5 and 15, taking claim 5 as representative, Plotnikov discloses the elements of claim 4, as discussed above. Plotnikov also discloses:
bit positions … of the second of the at least two bytes are to provide most significant bits for a register identifier (Plotnikov discloses, at Figure 13A and related description, the instruction includes a prefix, wherein the second byte of the prefix includes MSBs to identify registers.).
Plotnikov does not explicitly disclose the aforementioned bit positions are 5 and 1. However, the selection of the particular bits represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bits 5 and 1.
Regarding claims 6 and 16, taking claim 6 as representative, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix is to indicate an opcode map of the single instruction in …the second of the at least two bytes of the prefix (Plotnikov discloses, at Figure 13A and related description, the second byte of the prefix indicates an opcode map.).
Plotnikov does not explicitly disclose the aforementioned bit position is 7. However, the selection of the particular bit represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bit 7.
Regarding claims 9 and 19, taking claim 9 as representative, Plotnikov discloses the elements of claim 8, as discussed above. Plotnikov also discloses:
… the prefix is to identify a new data destination (Plotnikov discloses, at ¶ [0150], the prefix provides for a three-operand syntax, which discloses indicating usage of a new data destination.).
Plotnikov does not explicitly disclose the aforementioned bit positions are bits 3-6 of a second payload byte. However, the selection of the particular bits represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bits 3-6 of a second payload byte.
Claims 10, 11, 20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov in view of US Publication No. 2013/0297915 by Combs et al. (hereinafter referred to as “Combs”).
Regarding claim 10, Plotnikov discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix comprises four bytes… (Plotnikov discloses, at Figure 15A and related description, using four bytes for the prefix.).
Plotnikov does not explicitly disclose the aforementioned prefix is to indicate a suppression of updates to one or more flags.
However, in the same field of endeavor (e.g., processors) Combs discloses:
a prefix that indicates whether to modify flags (Combs discloses, at Figure 1 and related description, a prefix that indicates whether to modify flags, which discloses indicating suppression of updates to one or more flags.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include indication of suppression of flag updates, as disclosed by Combs, in order to improve performance by reducing unnecessary updates and complexity. See Combs, ¶ [0002].
Regarding claims 11, 20, and 25, taking claim 11 as representative, Plotnikov discloses the elements of claim 10, as discussed above. Plotnikov does not explicitly disclose the flags are overflow, carry, parity, adjust, sign, and zero.
However, in the same field of endeavor (e.g., processors) Combs discloses:
the flags are overflow, carry, parity, adjust, sign, and zero (Combs discloses, at Figure 1 and related description, “Flags 107 may include a carry flag (CF), an overflow flag (OF), a sign flag (SF), a zero flag (ZF), an auxiliary carry flag (AF), or a parity flag (PF), or a combination thereof.)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include the specific flags mentioned because these flags are widely used in many architectures to communicate state information.
Response to Arguments
On page 5 of the response filed June 22, 2026 (“response”), the Applicant argues, “As noted in MPEP 707.07(d), "[t]he examiner should, as a part of the first Office action on the merits, identify any claims which he or she judges, as presently recited, to be allowable and/or should suggest any way in which he or she considers that rejected claims may be amended to make them allowable." As this was not done in the first Office action on the merits, the Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions in any subsequent action. Providing prescribed guidance is in the interest of compact prosecution.”
Though fully considered, the Examiner respectfully disagrees. It is not apparent how any of the rejected claims could be amended to be allowable. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 5 of the response the Applicant argues, “The Office Action objects to the drawings. Applicant has amended the text FIG. 16 and the sheet number of all figures in the interest of compact prosecution. Applicant notes that the citation in the CFR uses the term "should," which is understood by the Office, courts, and the general English language as being hortatory, but not mandatory. Shall the Office present this objection to Applicant in another matter, Applicant will petition the Office for clarification as to what is or is not required based on common and legal usage of the word "shall" or "should."”
Though fully considered, the Examiner respectfully disagrees. 37 CFR 1.84 sets forth “Standards for drawings.” The Applicant is aware of the standard specified for sheet numbering as spelled out in the cited section. The Examiner is unaware of any valid reason why the Applicant’s drawings should not be held to those standards. Nor has the Applicant presented any such reason. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 6-7 of the response the Applicant argues, “The Office Action cites FIG. 13A and assert that "the instruction includes a prefix of at least two bytes and opcode, wherein the second by of the prefix includes MSBs to identifier registers." Obviously, that does not provide any level of specificity as to what the Office asserts may be MSBs in the cited VEX prefix 1302. Applicant is going to guess R or X or B as each of those do provide ONE bit for a register identifier (e.g., and VVVV would provide all (and not just the MSBs) of an identifier. Applicant is confused as how a single bit such as R becomes MSBs as Applicant presumes the "s" in MSBs indicates a plurality of bits. But Plotnikov, as cited, for example the R bit of the prefix, does not appear to describe a plurality of bits for that are MSBs for a particular register identifier as claimed.”
Though fully considered, the Examiner respectfully disagrees. The RXB field obviously includes multiple bits. See Figure 13A and related description, e.g., ¶ [0152] et seq. Each of these bits provides the MSB for one of the register identifiers. This discloses the claim limitation “provide most significant bits for at least one register identifier.” That is, the RXB field provides most significant bits for the identifiers for Rrrr, Xxx, and Bbbb register indices. The Applicant appears to urge a more narrow interpretation, i.e., that the claim requires multiple MSBs for a single register identifier. However, that is not what is claimed. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 7 of the response the Applicant argues the remaining independent claims are allowable for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The reasons set forth in the remarks and rejections presented above, including those regarding the independent claims, are applicable to these claims.
On page 7 of the response the Applicant states, “If the Examiner believes that this application is not in condition for allowance in view of this response, the Applicant requests an examiner interview.”
Please feel free to call the Examiner at the number below to schedule an interview.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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