DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 7, 10, 11, 12, 14, 20, 21, 22, 24, and 25 have been amended.
Claims 1-25 have been examined.
The drawing and claim objections in the previous Office Action have been addressed and are withdrawn.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16, and 18-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2019/0227798 by Plotnikov et al. (hereinafter referred to as “Plotnikov”) in view of US Publication No. 2008/0320247 by Morfey et al. (hereinafter referred to as “Morfey”).
Regarding claims 1, 11, and 21, taking claim 1 as representative, Plotnikov discloses:
an apparatus comprising: decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode to indicate execution circuitry is to …, wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations (Plotnikov discloses, at ¶ [0038], a processor with a decode unit to decode instructions. Plotnikov discloses, at Figure 13A and related description, an instruction that includes a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode to indicate what execution circuitry is to do, wherein a payload of the prefix includes MSBs to identify the first and second source operand locations. Plotnikov also discloses, at ¶ [0067], executing instructions that have been translated between instruction sets and, at ¶ [0058], storing instructions in memory.); and
execution circuitry to execute the decoded instance of the single instruction according to the opcode… (Plotnikov discloses, at ¶ [0038], the processor includes an execution unit to execute instructions.).
Plotnikov does not explicitly disclose the aforementioned instruction is to push data from the identified first source operand location and the identified second source operand location onto a stack.
However, in the same field of endeavor (e.g., processors) Morfrey discloses:
pushing data from a first source operand location and a second source operand location onto a stack (Morfrey discloses, at Table 57, a push instruction that pushes data from specified registers onto the stack.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include the push instruction disclosed by Morfrey in order to improve performance by reducing power associated with executing multiple instructions. See Morfrey, ¶ [0546].
Regarding claims 2, 12, and 22, taking claim 2 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the first and second source operand locations are registers (Plotnikov discloses, at Figure 13A and related description, the sources are stored in registers.).
Regarding claims 3, 13, and 23, taking claim 3 as representative, Plotnikov, as modified, discloses the elements of claim 2, as discussed above. Plotnikov also discloses:
the registers are 64-bit registers (Plotnikov discloses, at ¶ [0165], using 64-bit registers.).
Regarding claims 4, 14, and 24, taking claim 4 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix is to include …bits for each of the first and second source operands to be used as most significant bits of a register identifier (Plotnikov discloses, at Figure 13A and related description, a payload of the prefix includes MSBs to identify the first and second source operand locations.).
Plotnikov does not explicitly disclose two bits for each of the first and second source operands. Instead, Plotnikov discloses a single bit for each of the two source operands. See, e.g., REX field 1305. However, whether to use one, two, or more bits represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use two bits per operand.
Regarding claims 5 and 15, taking claim 5 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix comprises four bytes (Plotnikov discloses, at Figure 15A and related description, using four bytes for the prefix.).
Regarding claims 6 and 16, taking claim 6 as representative, Plotnikov, as modified, discloses the elements of claim 5, as discussed above. Plotnikov does not explicitly disclose bit position 18 of a payload of the prefix indicates support for a push pop acceleration. However, Plotnikov discloses that the prefix includes various fields indicating operations supported by the instruction. It would have been obvious to include indication of support for a push pop acceleration. Likewise, the selection of the particular bit represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bit 18 to indicate support for a push pop acceleration.
Regarding claims 8 and 18, taking claim 8 as representative, Plotnikov, as modified, discloses the elements of claim 5, as discussed above. Plotnikov does not explicitly disclose bit position 20 of a payload of the prefix is to be set to 1. However, selecting particular values of individual bits represents choosing between a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to set bit 20 to 1.
Regarding claims 9 and 19, taking claim 9 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov does not explicitly disclose the opcode is OxFF. However, selecting particular values of the opcode bits represents choosing between a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use 0xFF as the opcode.
Regarding claims 10, 20, and 25, taking claim 10 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the decoder circuitry is further to decode an instance of a different single instruction, the instance of the different single instruction to at least include a prefix, one or more fields to identify a first destination operand location, one or more fields to identify a second destination operand location, and an opcode to indicate execution circuitry is to …, wherein the prefix comprises at least two bytes and a second of the two bytes of the prefix is to provide most significant bits to identify at least one of the identified first and second destination operand locations (Plotnikov discloses, at ¶ [0038], a processor with a decode unit to decode instructions. Plotnikov discloses, at Figure 13A and related description, an instruction that includes a prefix, one or more fields to identify a first destination operand location, one or more fields to identify a second destination operand location, and an opcode to indicate what execution circuitry is to do, wherein the second byte of the prefix includes MSBs to identify at least one of the first and second destination operand locations. Plotnikov also discloses, at ¶ [0067], executing instructions that have been translated between instruction sets and, at ¶ [0058], storing instructions in memory.); and
the execution circuitry is to execute the decoded different instruction according to the opcode …(Plotnikov discloses, at ¶ [0038], the processor includes an execution unit to execute instructions.).
Plotnikov does not explicitly disclose the aforementioned instruction is to pop data to the identified first destination operand and the identified second destination operand from stack.
However, in the same field of endeavor (e.g., processors) Morfrey discloses:
popping data from a stack to a first destination operand location and a second destination operand location onto a stack (Morfrey discloses, at Table 57, a pop instruction that pops data from the stack to specified registers.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include the pop instruction disclosed by Morfrey in order to improve performance by reducing power associated with executing multiple instructions. See Morfrey, ¶ [0546].
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov in view of Morfey in view of US Publication No. 2016/0179545 by Garifullin et al. (hereinafter referred to as “Garifullin”)
Regarding claims 7 and 17, taking claim 7 as representative, Plotnikov, as modified, discloses the elements of claim 6, as discussed above. Plotnikov also discloses:
…acceleration is supported by a memory renaming circuitry … (Plotnikov discloses, at ¶ [0043], acceleration and, at Figure 17 and related description, renaming, which discloses acceleration is to be supported by a memory renaming circuitry.).
Plotnikov does not explicitly disclose the aforementioned acceleration is push pop and the aforementioned memory renaming circuitry is to maintain load/store pair operations.
However, in the same field of endeavor (e.g., processors) Morfey discloses:
push and pop operations (Morfrey discloses, at Table 56, push and pop operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include push and pop instructions, as disclosed by Morfey, in order to improve performance by facilitating efficient memory access. Morfrey, ¶ [0546].
Also, in the same field of endeavor (e.g., processors) Garifullin discloses:
maintain load/store pairs (Garifullin discloses, at ¶ [0154], maintaining load/store pairs.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include maintaining load/store pairs, as disclosed by Garifullin, in order to improve performance by facilitating efficient use of registers.
Response to Arguments
On page 6 of the response filed May 28, 2026 (“response”), the Applicant argues, “As noted in MPEP 707.07(d), "[t]he examiner should, as a part of the first Office action on the merits, identify any claims which he or she judges, as presently recited, to be allowable and/or should suggest any way in which he or she considers that rejected claims may be amended to make them allowable." As this was not done in the first Office action on the merits, the Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions in any subsequent action. Providing prescribed guidance is in the interest of compact prosecution.”
Though fully considered, the Examiner respectfully disagrees. It is not apparent which, if any, part of the application could serve as basis for allowable claims. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On pages 7-8 of the response the Applicant argues, “The Examiner relies on Morfey to teach the claimed "push" instruction. However, Applicant respectfully submits that the combination of Plotnikov and Morfey fails to teach or suggest a prefix payload providing most significant bits to identify the source operands of a push instruction. Specifically, Morfey's push instruction does not utilize encoded register identifiers that can be extended by a prefix. Instead, Morfey uses a "RegList" bitmask to identify the registers to be pushed onto the stack. As shown in Morfey's Table 57, the 32-bit encoding of the push instruction utilizes a "RegList[14:6]" field. A bitmask defines register inclusion by individual bit positions (e.g., bit 1 corresponds to R1, bit 2 corresponds to R2, etc.), rather than utilizing a distinct binary value (e.g., 001 for R1) that can be logically extended by a prefix (e.g., 1001 for R9). Because of this architectural difference, one cannot logically or architecturally append a prefix from Plotnikov's EVEX prefix to Morfey's RegList bitmask to expand the register file. Therefore, combining Plotnikov's prefix with Morfey's push instruction would not yield the claimed invention, and the Examiner's rejection relies on an impermissible modification that does not result in the claimed subject matter.”
Though fully considered, the Examiner respectfully disagrees. The Applicant argues it would be impossible to modify Morfey to include Plotnikov’s prefix. The Examiner respectfully disagrees. However, the point is moot as the Examiner did not propose modifying Morfey to include Plotnikov’s prefix. Instead, the Examiner proposed modifying Plotnikov’s instruction set to include push and pop instructions. While Plotnikov does not specifically mention push and pop instructions, they are supported by the x86 architecture. Therefore, modifying Plotnikov as suggested would be within the ordinary skill of those in the art and would result in the claimed subject matter. Accordingly, the Applicant’s arguments are deemed unpersuasive.
On page 9 of the response the Applicant argues, “Furthermore, the proposed combination would destroy the fundamental principle of operation of Morfey's instruction set, thereby teaching away from the combination. The Examiner proposes combining Plotnikov's instruction prefix with Morfey's push instruction in order to "improve performance." However, Plotnikov explicitly describes the EVEX prefix as a four-byte prefix (see Plotnikov at paragraph [0204]: "EVEX Prefix (Bytes 0-3)... is encoded in a four-byte form"). Conversely, Morfey's architecture is meticulously designed to maximize "high code density" by utilizing highly compressed 16-bit (2-byte) instructions. As explicitly stated in Morfey at paragraphs [0525] and [0526], "This leads to 56 k 16 bit instructions... Efficient function entry and exit is essential for good code density. In the preferred embodiment, efficient function entry is provided by the push instruction." Modifying Morfey's highly compressed 2- byte push instruction by appending Plotnikov's 4-byte prefix would triple the instruction's size. Such a modification would completely destroy the "good code density" that Morfey explicitly states is the primary purpose of its push instruction (see also Morfey at paragraph [0546]). Under MPEP 2143.01, a proposed modification cannot render the prior art unsatisfactory for its intended purpose. Because the proposed modification would destroy Morfey's intended purpose of achieving high code density, the prior art teaches away from the proposed combination. A person of ordinary skill in the art would not be motivated to append a massive 4- byte prefix to an instruction specifically engineered to save space, as doing so contradicts the explicit design goals of the Morfey reference.”
Though fully considered, the Examiner respectfully disagrees. As discussed above, the Applicant’s arguments regarding modification to Morfey are not dispositive as the Examiner proposed modifying Plotnikov to include the well-known functions of push and pop. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
Prosecution Insights