DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-25 have been examined.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statements dated March 1, 2024, April 19, 2024, and February 21, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. Copies of the PTOL-1449s initialed and dated by the Examiner are attached to the instant office action.
Drawings
The drawings are objected to because of the following informalities.
The format of the sheet numbering is improper. The figures therefore fail to comply with 37 CFR 1.84(t), which states “The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking.” The word “of” should be replaced by an oblique line on all sheets.
Element 1607 of Figure 16 includes the text, “AND/OF.” Please amend to, “AND/OR.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-25 are objected to because of the following informalities.
Claim 1 recites, at line 5, “circuitry is to do push data.” This appears to be a typographical error. Applicant may have intended, “circuitry is to [[do]] push data.” Claims 10, 11, 20, 21, and 25 have similar language and are similarly objected to.
Claim 1 recites, at line 7, “a payload of the prefix to provide.” This appears to be a typographical error. Applicant may have intended, “a payload of the prefix is to provide.” Claims 11, 21, and 25 have similar language and are similarly objected to.
Claim 10 recites, at lines 1-2, “an instance of single instruction. This appears to be a typographical error. Applicant may have intended, “an instance of the single instruction.” Claims 20, 21, and 25 have similar language and are similarly objected to.
Claim 21 includes, at line 3, double commas. This appears to be a typographical error.
Claims 2-10, 12-20, and 22-25 are objected to as depending from objected to base claims and failing to remedy the deficiencies of those claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites, at lines 2-3, “the instance of the single instruction to at least include a prefix.” This language is ambiguous and renders the scope of the claims indefinite. The instance either does or does not include a prefix. “To at least include,” makes it impossible to conclusively determine whether the prefix is included. For purposes of examination, this limitation is interpreted as, “the instance of the single instruction includes a prefix.” Claims 10, 11, 20, 21, and 25 have similar language and are similarly rejected.
Claim 1 recites, at lines 5-6 and line 10, “the identified first source operand.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the first source operand location.” Claims 10, 11, 20, 21, and 25 have similar language and are similarly rejected.
Claim 1 recites, at line 6 and lines 10-11, “the identified second source operand.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the second source operand location.” Claims 10, 11, 20, 21, and 25 have similar language and are similarly rejected.
Claim 2 recites, at line 1, “the first and second source operands.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the first and second source operand locations.” Claims 4, 12, 14, 22, and 24 have similar language and are similarly rejected.
Claim 7 recites, at line 1, “push pop acceleration is to be supported.” This language is ambiguous and renders the scope of the claims indefinite. The acceleration either is or is not supported. “To be supported,” makes it impossible to conclusively determine whether the acceleration is supported. For purposes of examination, this limitation is interpreted as, “push pop acceleration is [[to be]] supported.”
Claim 10 recites, at line 2, “the instance of the single instruction.” There are multiple possible antecedent bases for this limitation, rendering the scope of the claims indefinite. The same is true for the following limitations in claim 10: “the prefix,” “the execution circuitry,” “the decoded instruction,” and “the opcode.” Claims 20 and 25 have similar language and are similarly rejected.
Claim 10 recites, at line 5, “the identified destination source operand.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the second destination operand location.” Claims 20 and 25 have similar language and are similarly rejected.
Claim 10 recites, at lines 9-11, “the execution circuitry is to execute the decoded instruction according to the opcode to push data from the identified first source operand and the identified second source operand onto the stack.” This limitation renders the claims indefinite because it cannot be determined whether the limitation requires a second push operation of the source operands, in addition to the push operation in claim 1. A second push operation is inconsistent with the written description. For purposes of examination, the limitation is interpreted as requiring a pop operation from the stack to the destination operand locations. Claims 20 and 25 have similar language and are similarly rejected.
Claims 2-10, 12-20, and 22-25 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16, and 18-25 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2019/0227798 by Plotnikov et al. (hereinafter referred to as “Plotnikov”) in view of US Publication No. 2008/0320247 by Morfey et al. (hereinafter referred to as “Morfey”).
Regarding claims 1, 11, and 21, taking claim 1 as representative, Plotnikov discloses:
an apparatus comprising: decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode to indicate execution circuitry is to do…, wherein a payload of the prefix to provide most significant bits to identify at least one of the first and second source operand locations (Plotnikov discloses, at ¶ [0038], a processor with a decode unit to decode instructions. Plotnikov discloses, at Figure 13A and related description, an instruction that includes a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode to indicate what execution circuitry is to do, wherein a payload of the prefix includes MSBs to identify the first and second source operand locations. Plotnikov also discloses, at ¶ [0067], executing instructions that have been translated between instruction sets and, at ¶ [0058], storing instructions in memory.); and
execution circuitry to execute the decoded instance of the single instruction according to the opcode… (Plotnikov discloses, at ¶ [0038], the processor includes an execution unit to execute instructions.).
Plotnikov does not explicitly disclose the aforementioned instruction is to push data from the identified first source operand and the identified second source operand onto a stack.
However, in the same field of endeavor (e.g., processors) Morfrey discloses:
pushing data from a first source operand location and a second source operand location onto a stack (Morfrey discloses, at Table 57, a push instruction that pushes data from specified registers onto the stack.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include the push instruction disclosed by Morfrey in order to improve performance by reducing power associated with executing multiple instructions. See Morfrey, ¶ [0546].
Regarding claims 2, 12, and 22, taking claim 2 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the first and second source operands are registers (Plotnikov discloses, at Figure 13A and related description, the sources are stored in registers.).
Regarding claims 3, 13, and 23, taking claim 3 as representative, Plotnikov, as modified, discloses the elements of claim 2, as discussed above. Plotnikov also discloses:
the registers are 64-bit registers (Plotnikov discloses, at ¶ [0165], using 64-bit registers.).
Regarding claims 4, 14, and 24, taking claim 4 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix is to include …bits for each of the first and second source operands to be used as most significant bits of a register identifier (Plotnikov discloses, at Figure 13A and related description, a payload of the prefix includes MSBs to identify the first and second source operand locations.).
Plotnikov does not explicitly disclose two bits for each of the first and second source operands. Instead, Plotnikov discloses a single bit for each of the two source operands. See, e.g., REX field 1305. However, whether to use one, two, or more bits represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use two bits per operand.
Regarding claims 5 and 15, taking claim 5 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the prefix comprises four bytes (Plotnikov discloses, at Figure 15A and related description, using four bytes for the prefix.).
Regarding claims 6 and 16, taking claim 6 as representative, Plotnikov, as modified, discloses the elements of claim 5, as discussed above. Plotnikov does not explicitly disclose bit position 18 of a payload of the prefix indicates support for a push pop acceleration. However, Plotnikov discloses that the prefix includes various fields indicating operations supported by the instruction. It would have been obvious to include indication of support for a push pop acceleration. Likewise, the selection of the particular bit represents one of a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use bit 18 to indicate support for a push pop acceleration.
Regarding claims 8 and 18, taking claim 8 as representative, Plotnikov, as modified, discloses the elements of claim 5, as discussed above. Plotnikov does not explicitly disclose bit position 20 of a payload of the prefix is to be set to 1. However, selecting particular values of individual bits represents choosing between a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to set bit 20 to 1.
Regarding claims 9 and 19, taking claim 9 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov does not explicitly disclose the opcode is OxFF. However, selecting particular values of the opcode bits represents choosing between a limited number of possibilities that are obvious alternatives that a person having ordinary skill in the art would consider based on the circumstances. Accordingly, it would have been obvious to use 0xFF as the opcode.
Regarding claims 10, 20, and 25, taking claim 10 as representative, Plotnikov, as modified, discloses the elements of claim 1, as discussed above. Plotnikov also discloses:
the decoder circuitry is further to decode an instance of single instruction, the instance of the single instruction to at least include a prefix, one or more fields to identify a first destination operand location, one or more fields to identify a second destination operand location, and an opcode to indicate execution circuitry is to …, wherein the prefix comprises at least two bytes and a second of the two bytes of the prefix is to provide most significant bits to identify at least one of the first and second destination operand locations (Plotnikov discloses, at ¶ [0038], a processor with a decode unit to decode instructions. Plotnikov discloses, at Figure 13A and related description, an instruction that includes a prefix, one or more fields to identify a first destination operand location, one or more fields to identify a second destination operand location, and an opcode to indicate what execution circuitry is to do, wherein the second byte of the prefix includes MSBs to identify at least one of the first and second destination operand locations. Plotnikov also discloses, at ¶ [0067], executing instructions that have been translated between instruction sets and, at ¶ [0058], storing instructions in memory.); and
the execution circuitry is to execute the decoded instruction according to the opcode …(Plotnikov discloses, at ¶ [0038], the processor includes an execution unit to execute instructions.).
Plotnikov does not explicitly disclose the aforementioned instruction is to pop data to the identified first destination operand and the identified second destination operand from stack.
However, in the same field of endeavor (e.g., processors) Morfrey discloses:
popping data from a stack to a first destination operand location and a second destination operand location onto a stack (Morfrey discloses, at Table 57, a pop instruction that pops data from the stack to specified registers.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include the pop instruction disclosed by Morfrey in order to improve performance by reducing power associated with executing multiple instructions. See Morfrey, ¶ [0546].
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Plotnikov in view of Morfey in view of US Publication No. 2016/0179545 by Garifullin et al. (hereinafter referred to as “Garifullin”)
Regarding claims 7 and 17, taking claim 7 as representative, Plotnikov, as modified, discloses the elements of claim 6, as discussed above. Plotnikov also discloses:
…acceleration is to be supported by a memory renaming circuitry … (Plotnikov discloses, at ¶ [0043], acceleration and, at Figure 17 and related description, renaming, which discloses acceleration is to be supported by a memory renaming circuitry.).
Plotnikov does not explicitly disclose the aforementioned acceleration is push pop and the aforementioned memory renaming circuitry is to maintain load/store pair operations.
However, in the same field of endeavor (e.g., processors) Morfey discloses:
push and pop operations (Morfrey discloses, at Table 56, push and pop operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include push and pop instructions, as disclosed by Morfey, in order to improve performance by facilitating efficient memory access. Morfrey, ¶ [0546].
Also, in the same field of endeavor (e.g., processors) Garifullin discloses:
maintain load/store pairs (Garifullin discloses, at ¶ [0154], maintaining load/store pairs.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Plotnikov to include maintaining load/store pairs, as disclosed by Garifullin, in order to improve performance by facilitating efficient use of registers.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20080301401 by Honda discloses pushm and popm that pushes/pops a plurality of instructions.
US 20020138715 by Minematsu discloses mpush and mpop that pushes/pops a plurality of instructions.
US 20020103991 by Overkamp discloses push pop multiple for multiple registers.
US 6349383 by Col discloses push/pop two operands in a single instruction.
US 20190220284 by Gupta discloses memory renaming and load/store pairs.
US 10838729 by Al-Otoom discloses renaming and stack push/pop.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183