DETAILED ACTION
This action is responsive to the application filed on 12/30/2022. Claims 1-25 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-25 are objected to because of the following informalities:
In regards to claim 1, lines 6 and 12 each include an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 1, lines 3-4 and improve readability of the claim.
In regards to claim 1, line 11 the limitation “instance of the single” should be amended to “instance of the single instruction” to use language consistent with claim 1, line 2 and improve readability of the claim.
In regards to claim 2, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 1, lines 3-4 and improve readability of the claim.
In regards to claim 3, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 1, lines 3-4 and improve readability of the claim.
In regards to claim 9, line 2 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 1, lines 3-4 and improve readability of the claim.
In regards to claim 11, lines 7 and 13 each include an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 11, lines 4-5 and improve readability of the claim.
In regards to claim 11, line 12 the limitation “instance of the single” should be amended to “instance of the single instruction” to use language consistent with claim 11, line 2 and improve readability of the claim.
In regards to claim 12, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 11, lines 4-5 and improve readability of the claim.
In regards to claim 13, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 11, lines 4-5 and improve readability of the claim.
In regards to claim 19, line 2 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 11, lines 4-5 and improve readability of the claim
In regards to claim 21, line 7 includes an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 21, lines 4-5 and improve readability of the claim.
In regards to claim 22, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 21, lines 4-5 and improve readability of the claim.
In regards to claim 23, line 1 an instance of the limitation “first source operand” which should be amended to “first source operand location” to use language consistent with claim 21, lines 4-5 and improve readability of the claim.
Claims 2-10, 12-20 and 22-25 are dependent upon one or more claims above and therefore are similarly objected to for including the deficiencies of one or more claims above.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “An apparatus” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…conditionally perform a comparison of data…based at least in part on an evaluation of a source condition” which describe a process that under its broadest reasonable interpretation encompasses mental processes and/or mathematical calculations. That is other than reciting generic computing components (e.g. decoder circuitry, execution circuitry to execute instructions and stack memory) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses conditionally performing a comparison of data based on an evaluation of source condition; wherein the evaluation is a mental process and the comparison can be considered a mental process and a math calculation (see paragraphs 00375-00376 and 00381]: wherein the evaluation and comparison which may encompass a subtraction operation is disclosed. Also note claim 9, explicitly indicates comparison is subtraction), thus the limitations encompass mental processes and mathematical calculations (MPEP 2106.04(a)(2)(I)(C) and (III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation and/or mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” and “Mental Processes” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
decoder circuitry to decode an instance of single instruction, the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a first source operand location, and an opcode to indicate execution circuitry… from the identified first source operand to the identified second source operand… condition code…flags register… wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations; and execution circuitry to execute the decoded instance of the single according to the opcode… from the identified first source operand and the identified second source operand…the stack
update a flags register…push data onto the stack
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein the first source operand is a register and the destination operand is a memory location”, which discloses a particular data source used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 1, further recites “…wherein the first source operand and the second source operand are registers”, which discloses a particular data source used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 3, further recites “…wherein the prefix is to include two bits for each of the first and second source operands to be used as most significant bits of a register identifier”, which discloses the prefix of the instruction used in the abstract idea of claim 1. The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 1, further recites “…wherein the source condition code is to be provided by the prefix”, which discloses the prefix of the instruction used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1 further recites “…wherein when the comparison is to not be performed, a proper subset of flags of a flags register are to be inverted” which ties the abstract idea of claim 1 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Further, the limitation states inverting flags of a register (e.g. updating a flags register) which can be the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 6, further recites “…wherein the proper subset of flags includes an overflow flag, a sign flag, a zero flag, and a carry flag”, which discloses the types of flags used in the abstract idea of claim 6. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, dependent upon claim 1, further recites “…wherein bit position 20 of a payload of the prefix is to be set to 1”, which discloses bits of the prefix of the instruction used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, dependent upon claim 1, further recites “…wherein when the comparison is to be performed, data from the second source operand is subtracted from the first source operand and condition codes generated from the subtraction are to be stored in the flags register”, which discusses the abstract idea of the comparison of claim 1 comprising math (i.e. subtraction) and writing a result to a register based on the abstract idea. Thus, the claim recites additional limitations which detail insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 10, dependent upon claim 1, further recites “…wherein the source condition code encodes a condition to test for”. Thus, the additional limitation ties the abstract idea to a particular type of condition e.g. a particular field of use or technological environment (MPEP 2106.05(h)). The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 11 is similarly rejected on the same basis as claim 1 above.
Claims 12-20 are similarly rejected on the same basis as claims 2-10 above.
Regarding claim 21:
Subject Matter Eligibility Analysis Step 1:
Claim 21 recites “A method” and thus a process, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 21 recites “…conditionally perform a comparison of data…based at least in part on an evaluation of a source condition” which describe a process that under its broadest reasonable interpretation encompasses mental processes and/or mathematical calculations. That is other than reciting generic computing components (e.g., execution circuitry) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses conditionally performing a comparison of data based on an evaluation of source condition; wherein the evaluation is a mental process and the comparison can be considered a mental process and a math calculation (see paragraphs 00375-00376 and 00381]: wherein the evaluation and comparison which may encompass a subtraction operation is disclosed. Also note claim 9, explicitly indicates comparison is subtraction), thus the limitations encompass mental processes and mathematical calculations (MPEP 2106.04(a)(2)(I)(C) and (III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical calculation and/or mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” and “Mental Processes” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 21 further recites additional elements of
translating an instance of single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture, the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a first source operand location, and an opcode to indicate execution circuitry… from the identified first source operand to the identified second source operand… condition code…flags register… wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations; decoding the one or more instructions of the second instruction set architecture; and executing the decoded one or more instructions of the second instruction set architecture according to the opcode of the instance of single instruction of a first instruction set architecture
update a flags register
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)); and (b) recites insignificant extra-solution activity (i.e. data outputting) (See MPEP 2106.05 (g)).
Therefore, claim 21 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). While, (b) recites insignificant extra-solution activity of data outputting (see MPEP 2106.05(g)) which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)).
Therefore, based on the discussion of the additional elements above, claim 21 is not patent eligible.
Claim 22, dependent upon claim 21, further recites “…wherein the first source operand is a register and the destination operand is a memory location”, which discloses a particular data source used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 23, dependent upon claim 21, further recites “…wherein the first source operand and the second source operand are registers”, which discloses a particular data source used in the abstract idea of claim 1. Thus, the additional limitation ties the abstract idea to a particular type of data, e.g. a particular field of use or technological environment (MPEP 2106.05(h)). Also, the limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 24, dependent upon claim 23, further recites “…wherein the prefix is to include two bits for each of the first and second source operands to be used as most significant bits of a register identifier”, which discloses the prefix of the instruction used in the abstract idea of claim 1. The limitation ties the abstract idea to using mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Furthermore, based on applicant’s own admission in paragraphs [0001 and 0056], the use of instruction prefixes including payload extensions in the form of extra register identifier bits has been used in past processors, thus those claimed elements are also well-understood, routine and conventional (MPEP 2106.05(d)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 25, dependent upon claim 21 further recites “…wherein when the comparison is to not be performed, a proper subset of flags of a flags register are to be inverted” which ties the abstract idea of claim 21 to mere instructions used on a computer, using the words “apply it” with the judicial exception or merely uses a computer as a tool to perform an abstract idea (See MPEP 2106.05(f)). Further, the limitation states inverting flags of a register (e.g. updating a flags register) which can be the insignificant extra-solution activity of data outputting, which is also a well-understood, routine and conventional activity (See MPEP 2106.05(d and g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 1, the limitation “…the instance of the single instruction to at least include… an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand to the identified second source operand based at least in part on an evaluation of a source condition code and update a flags register, and execution circuitry to execute the decoded instance of the single according to the opcode to push data from the identified first source operand and the identified second source operand onto the stack” fails to comply with the written description requirement because the original disclosure does not properly describe a single instruction including an opcode (i.e. a single opcode) that causes execution circuitry to perform a conditional comparison and push source operand data on a stack in sufficient detail that one skilled in the art can reasonably conclude the inventor had possession of the claimed invention.
Specifically, paragraphs [00185-00187] and Figs. 7-8 disclose a single instruction including an opcode which indicates to an execution circuit to push data from two source operands onto a stack in a memory. While, paragraphs [00304-00308] and Figs. 18-19 disclose another single instruction including an opcode which indicate to an execution circuit to perform a conditional comparison of data based on an evaluation of a source condition code to update a flags register. However, the original disclosure does not appear to describe a single instruction including an opcode (e.g. a single or same opcode) which indicates to an execution circuit to perform both a push operation on a stack and a conditional comparison to update flags register as claimed (e.g. each operation is referring to a single “opcode” in the claim).
While the disclosure discloses each of the different instructions with different opcodes (e.g. CCMP and PUSH2 instructions) being able to include a EVEX2 prefix, this is not the same as a single instruction including an opcode to perform two different operations as claimed. Thus, the disclosure does not appear to provide support for the current claim language. (Note that the issue of a lack of adequate written description may arise even for an original claim when an aspect of the claimed invention has not been described with sufficient particularity such that one skilled in the art would recognize that the applicant had possession of the claimed invention)
The examiner suggests the applicant amend the claims with support from the specification to indicate a first instruction (e.g. a CCMP) including an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand to the identified second source operand based at least in part on an evaluation of a source condition code and update a flags register, and execution circuitry to execute a second instruction (e.g. PUSH2) according to an opcode to push data from the identified first source operand and the identified second source operand onto a stack.
Claim 11 is similarly rejected on the same basis as claim 1 above.
Claims 2-10 and 12-20 are dependent upon one of the claims above and therefore are similar rejected on the same basis as one of the claims above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 1, lines 6-7 the limitation stating “…the identified first source operand to the identified second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of line 3 or a “first source operand” of line 4; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 1, lines 9-10 the limitation stating “…the first and second source operand locations” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of line 3 or a “first source operand” of line 4; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 1, lines 12-13 the limitation stating “…the identified first source operand and the identified second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of line 3 or a “first source operand” of line 4; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 1, last line the limitation “the stack” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis, as there is no prior recitation of “a stack”.
In regards to claim 2, lines 1-2 the limitation stating “…the first source operand…the destination operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 1, line 3 or a “first source operand” of claim 1, line 4 and (2) the destination operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a destination operand”.
In regards to claim 3, lines 1-2 the limitation stating “…the first source operand and the second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 1, line 3 or a “first source operand” of claim 1, line 4; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 4, lines 1-2 the limitation stating “…the first and second source operands” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 1, line 3 or a “first source operand” of claim 1, line 4; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 9, line 2 the limitation “the second source operand” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 11, lines 7-8 the limitation stating “…the identified first source operand to the identified second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of lines 4-5 or a “first source operand” of lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 11, lines 10-11 the limitation stating “…the first and second source operand locations” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of lines 4-5 or a “first source operand” of lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 11, lines 13-14 the limitation stating “…the identified first source operand and the identified second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of lines 4-5 or a “first source operand” of lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 11, last line the limitation “the stack” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis, as there is no prior recitation of “a stack”.
In regards to claim 12, lines 1-2 the limitation stating “…the first source operand…the destination operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 11, lines 4-5 or a “first source operand” of claim 11, lines 5-6 and (2) the destination operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a destination operand”.
In regards to claim 13, lines 1-2 the limitation stating “…the first source operand and the second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 11, lines 4-5 or a “first source operand” of claim 11, lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 14, lines 1-2 the limitation stating “…the first and second source operands” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 11, lines 4-5 or a “first source operand” of claim 11, lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 19, line 2 the limitation “the second source operand” lacks clarity. The limitation lacks clarity because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 21, lines 7-8 the limitation stating “…the identified first source operand to the identified second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of lines 4-5 or a “first source operand” of lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 21, lines 10-11 the limitation stating “…the first and second source operand locations” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 21, lines 4-5 or a “first source operand” of claim 21, lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 22, lines 1-2 the limitation stating “…the first source operand…the destination operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 21, lines 4-5 or a “first source operand” of claim 21, lines 5-6 and (2) the destination operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a destination operand”.
In regards to claim 23, lines 1-2 the limitation stating “…the first source operand and the second source operand” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 21, lines 4-5 or a “first source operand” of claim 21, lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
In regards to claim 24, lines 1-2 the limitation stating “…the first and second source operands” lacks clarity. The limitation lacks clarity because (1) it is unclear if the first source operand is referring a “first source operand” of claim 21, lines 4-5 or a “first source operand” of claim 21, lines 5-6; and (2) the second source operand is unclear because it lacks proper antecedent basis, as there is no prior recitation of “a second source operand”.
Claims 2-10, 12-20 and 22-25 are dependent upon one or more claims above and therefore are similarly rejected on the same basis as one or more claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins, PGPUB No. 2016/0179538, and further in view of Seal, PGPUB No. 2013/0097408.
In regards to claim 21, Collins discloses A method comprising: translating an instance of single instruction of a first instruction set architecture to one or more instructions of a second instruction set architecture ([0071-0073 and Fig. 8]: wherein x86 instructions are converted to instructions of a different instruction set architecture) the instance of the single instruction to at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a first source operand location ([0160, 0170 and 0178]: wherein single instruction format includes a prefix field (element 1702), source operand field (element 1744) and a source operand field (1746) (See Figs. 16-17)) wherein a payload of the prefix is to provide most significant bits to identify at least one of the first and second source operand locations ([0166-0167]: wherein payload (byte 1) of EVEX prefix provides most significant bits (highest bits of register indexes) to identify one of the first or second operand locations) decoding the one or more instructions of the second instruction set architecture; and executing the decoded one or more instructions of the second instruction set architecture. ([0035-0036 and 0072]: wherein a core which executes a different instruction set decodes and executes the converted instructions)
Collins does not disclose comprising: an instance of the single instruction to at least include one or more fields to identify a first source operand location, one or more fields to identify a first source operand location and an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand to the identified second source operand based at least in part on an evaluation of a source condition code and update a flags register nor executing the instance of the single instruction according to the opcode of the instance of the single instruction. Collins does generally disclose conditionally executing predicated instructions; however, Collins does not disclose a conditional compare instruction.
Seal discloses an instance of the single instruction to at least include one or more fields to identify a first source operand location, one or more fields to identify a first source operand location ([0070-0071 and 0076]: wherein a conditional compare instruction includes one or more fields to identify a first source operand register and a second source operand register) and an opcode to indicate execution circuitry is to conditionally perform a comparison of data from the identified first source operand to the identified second source operand based at least in part on an evaluation of a source condition code and update a flags register ([0070-0071 and 0077]: wherein an opcode of CCMP instruction indicates processing circuitry is to conditionally perform a comparison of data from the first and second source operands based at least in part on evaluating a test condition code (Cond) and update a condition code flags of a status register (element 15)(See Figs. 3A-B and 5)) executing the instance of the single instruction according to the opcode of the instance of the single instruction ([0076-0077]: wherein the CCMP instruction is decoded and executed)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify instruction set of Collins, which includes conditional instructions, to include a conditional compare instruction as taught in Seal. It would have been obvious to one of ordinary skill in the art because the conditional compare instruction allows for testing of a chained sequence of comparisons of different types and thus can be used more widely and is hence more easily usable by compilers (Seal [0016])
In regards to claim 22, the combination of Collins and Seal discloses The method of claim 21 (see rejection of claim 21 above) wherein the first source operand is a register and the destination operand is a memory location. (Collins [0178]: wherein first source is a register and destination is a memory location |Seal [0071 and 0077-0078]: wherein first source is a register and destination is a status register)
In regards to claim 23, the combination of Collins and Seal discloses The method of claim 21 (see rejection of claim 21 above) wherein the first source operand and second source operands are registers. (Collins [0178]: wherein first source and second source are registers |Seal [0071, 0077-0078])
In regards to claim 24, the combination of Collins and Seal discloses The method of claim 21 (see rejection of claim 21 above) wherein the prefix is to include two bits for each of the first and second source operands to be used as most significant bits of a register identifier. (Collins [0166-0167 and 0178]: wherein EVEX prefix includes two bits for each of the first and second source operands to be used as the most significant bits of a register identifier (e.g. bits R and R’ for a first source and bits B and R’ for example; see elements 1705 and 1710 of Fig. 17))
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Collins, Seal, and further in view of Dent, USPAT. No. 6,314,504.
In regards to claim 25, the combination of Collins and Seal discloses The method of claim 21 (see rejection of claim 21 above) wherein when the comparison is to not be performed, a proper subset of flags of a flags register are to be changed. (Seal [0071 and 0078]: wherein when the comparison is not performed a proper subset of flags are set using a fail condition state)
The combination of Collins and Seal thus far does not disclose a proper subset of flags of a flags register are to be inverted. Seal discloses the flags register being set to a programmable fail condition that can be any programmable value (see [0021-0023]), however Seal has not explicitly stated that the fail condition can indicate an inversion of flags.
Dent discloses a proper subset of flags of a flags register are to be inverted. (Column 12, lines 46-50: wherein bits of a condition register are inverted)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the failure condition set in status register of Collins and Seal to include inversion of flags in the status register as in Dent. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (setting a state of a status register by inverting bits as taught in Dent) for another (generically setting a state of a status register as taught in Seal) to yield predictable results (setting a failed state in a status register by inverting the bits) (MPEP 2143, Example B).
Conclusion
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183