DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20, are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claims 1, 14, the metes and bounds of the claimed invention are vague and inexplicitly defined as a result of limitation “a semiconductor nanoribbon” and “a partial semiconductor nanoribbon”. These claims are indefinite because it is not clear what/or how they are used together within a single device architecture? The specification or drawings do not provide any clear explanation to this limitation, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claim is rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
Regarding Claim 17, the metes and bounds of the claimed invention are vague and inexplicitly defined as a result of limitation “etching the channel region of the first semiconductor nanoribbon without etching the channel regions of semiconductor nanoribbons of the plurality of semiconductor nanoribbons other than the first semiconductor nanoribbon”. These claims are indefinite because it is not clear what/or how this approach relies on the chemical difference between the material of the first nanoribbon and the surrounding materials? The specification or drawings do not provide any clear explanation to this limitation, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claim is rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-16, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Lilak et al., US 2019/0196830 A1.
Claims 1-2, 8. Lilak et al., disclose a device (such as the one in fig. 1, item 100) comprising:
-a transistor (item 128) comprising:
-a semiconductor nanoribbon (item 130-1) comprising:
-a first source or drain region (item 118-1);
-a channel region (item 106-1);
-and a second source or drain region (item 118-1), wherein the channel region is connected to the first source or drain region and the second source or drain region (as seen in the structure of fig. 1);
-and a partial semiconductor nanoribbon (item 130-1) comprising:
-a third source or drain region (item 118-2);
-and a fourth source or drain region (item 118-2), wherein the partial semiconductor nanoribbon is located on the semiconductor nanoribbon (as seen in the structure of fig. 1).
Claim 3. Lilak et al., disclose the device of claim 1, further comprising: a substrate (item 102), wherein the transistor is located on the substrate; and a second transistor located on the substrate, wherein the second transistor is between the transistor and the substrate (as seen in the structure of fig. 1).
Claims 4-6, 9-10, 12. Lilak et al., disclose the device of claim 3, wherein one of the transistors and the second transistor is a PMOS transistor, wherein the other of the transistor and the second transistor is an NMOS transistor, wherein a gate of the transistor is connected to a gate of the second transistor (this limitation would read through [0022] wherein is disclosed the S/D materials 118 may include a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, S/D materials 118 may include dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D materials 118 may include one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. For p-type metal oxide semiconductor (PMOS) transistors, S/D materials 118 may include, for example, group IV semiconductor materials such as silicon, germanium, silicon germanium, germanium tin, or silicon germanium alloyed with carbon. Example p-type dopants in silicon, silicon germanium, and germanium include boron, gallium, indium, and aluminum. For n-type metal oxide semiconductor (NMOS) transistors, S/D materials 118 may include, for example, group III-V semiconductor materials such as indium, aluminum, arsenic, phosphorous, gallium, and antimony, with some example compounds including indium aluminum arsenide, indium arsenide phosphide, indium gallium arsenide, indium gallium arsenide phosphide, gallium antimonide, gallium aluminum antimonide, indium gallium antimonide, or indium gallium phosphide antimonide).
Claims 7, 11. Lilak et al., disclose the device of claim 3, wherein a separation between the transistor and the second transistor is less than 30 nanometers, (this limitation would read through [0029] wherein is disclosed in some embodiments, the difference between the gate lengths 158 of two device strata 130 having different gate lengths 158 may be greater than 6 nanometers (e.g., greater than 12 nanometers, or greater than 18 nanometers).
Claim 13. Lilak et al., disclose the processor comprising the device of claim 1 (this limitation would read through [0029] wherein is disclosed the IC structure 100 may be part of a device that includes memory and logic devices (e.g., in a single die 1502, as discussed below), such as a processor and cache).
Claims 14-16. Lilak et al., disclose a device (such as the one in fig. 1, item 100) comprising: a substrate (item 102);
-a first transistor (item 130-1) located on the substrate, wherein the first transistor comprises a first plurality of semiconductor nanoribbons stacked on top of each other, wherein the plurality of semiconductor nanoribbons comprises one or more complete nanoribbons and one or more partial semiconductor nanoribbons (as seen in the structure of fig. 1);
-and a second transistor (item 130-2) located on the substrate next to the first transistor, wherein the second transistor comprises a plurality of complete semiconductor nanoribbons stacked on top of each other,
-wherein a height of semiconductor nanoribbons of the first transistor from the substrate is within 5 nanometers of a height of semiconductor nanoribbons of the second transistor from the substrate (this limitation would read through [0029] wherein is disclosed an individual one of the semiconductor wires has a height between 5 nanometers and 30 nanometers.
Allowable Subject Matter
Claims 17-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899