DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of invention Group II, claims 1-15, in the reply filed on 3/4/2026 is acknowledged. Claim s 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/4/2026 . Information Disclosure Statement The information disclosure statement filed on 12/30/2022 has been acknowledged and a signed copy of the PTO-1449 is attached herein. Claim Objections Claim 6 is objected to because of the following informalities: Claim 6 recites “… an isolating dielectric metal…” The term “dielectric metal” appears to be a typo error. Also, the specification at Par [0023] discloses “ an isolating dielectric metal such as, silicon nitride ( SiNx ), silicon boron carbonitride ( SiBCN ), silicon boronitride ( SiBN ), silicon carbon nitride ( SiCN ), silicon oxynitride ( SiON ), ” a ll of which are dielectric materials rather than metals . Therefore, the Examiner concludes that the “isolating dielectric metal” is a typo error for “an isolating dielectric material.” For the purpose of examination, the limitation is interpreted as “an isolating dielectric material.” Appropriate correction is required. Claim Rejections - 35 USC § 112 Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites the limitation” wherein the metal is selected from a group …” in line 1. Claim 10 depends from claim 9, which depends from claim 1. There is insufficient antecedent basis for the limitation “the metal …” in the claim chain. Neither claim 9 nor claim 1 introduces any element identified as “a metal”. However, claim 3 recites “the backside-connecting via is without metal voids,” thereby establishing the backside-connecting via comprising a metal. For the purpose of examination, the Examiner assumes that claim 10 depends from claim 3. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 5-6, 11, 13-15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 2021/0028112 A1, hereinafter “Kim”) . In regards to claim 1 , Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising: a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049] -[ 0051]) ; a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN; a device layer comprising: a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]) ; a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]) ; a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]) ; and a second spacer (164 on a second side of buried conductive wiring 120 within trench ST , See also Par [0035] ) , wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162 ; See also Fig. 3); the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162 ; See also Fig. 3) ; and the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]) ; and a backside-connecting via (conductive thru structure 250 , See Par [0036] ) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]) , the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]) , the first spacer , and the second spacer (a poretion of the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3 , See also Par [0037]) ; wherein the backside-connecting via is in electrical contact with the first transistor (Conductive through structure 250 is electrically connected to the source/drain region 110 of the first transistor, See also Pars [0036], [0044] and [0048]) . In regards to claim 15 , Kim discloses (See, for example, Fig. 2) a semiconductor device array comprising: a backside power distribution network (BSPDN) (Second wiring portion ML2 including metal wirings M2 and M3; See also Pars [0049] -[ 0051]) ; a buried power rail (BPR) (120 in trench ST, See in Fig. 1) in contact (See, for example, Pars [0034] and [0036]) with the BSPDN; a device layer comprising: a first transistor (FINFET formed on active fin 105 on a first side of trench ST; including source/drain region 110 and gate structure GS, See also, Pars [0027] and [0028]) ; a second transistor (FINFET formed on active fin 105 on a second, opposite side of trench ST, See also, Par [0027]) ; a first spacer (164 on a first side of buried conductive wiring 120 within trench ST, See also Par [0035]) ; and a second spacer (164 on a second side of buried conductive wiring 120 within trench ST, See also Par [0035]) , wherein: the first transistor is in contact with the first spacer (active fin 105 on the first side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162 ; See also Fig. 3); the second transistor is in contact with the second spacer (active fin 105 on the second side of trench ST is in contact with 164 through the active region 102 and device isolation layer 162 ; See also Fig. 3) ; the first spacer neighbors the second spacer ( 164 on opposite sides of 120 are adjacent to each other within trench ST, See also Fig. 3 and Par [0035]) ; and the first transistor neighbors the second transistor (Active fins 105 on opposite sides of trench ST are neighboring transistors arranged on the active region 102, See also, Par [0033]) ; and a backside-connecting via (conductive thru structure 250, See Par [0036]) that is in contact with the first transistor (through buried conductive wiring 120 and contact structure 180 which contacts source/drain, See Pars [0044] and [0048]) , the BPR (See, 250 directly contacts 120, See also Par [0036]-[0037]) , the first spacer , and the second spacer (a portion of the conductive through structure 250 contacts 164 on both sides of 120…indicated by contact area CT1 in Fig. 3 , See also Par [0037]) . wherein: the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037] -[ 0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions) ; the backside-connecting via is in electrical contact with a top surface of the first transistor (250 is electrically connected to the source/drain region 110 of the first transistor. The contact structure 180 includes a first contact area 180A that contacts a top surface of the source/drain region 110, See also Par [0044]) ; the first spacer (164 ) and a first additional spacer (162/162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]) ; and the second spacer (164) and a second additional spacer (162/162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]) . In regards to claim 2 , Kim discloses (See, for example, Fig. 2) the second spacer prevents a short resulting from electrical contact between the second transistor and the backside-connecting via (Pars [0037] -[ 0038] teaches that forming 164 prevents undesired shorts between 250 and adjacent active regions ) . In regards to claim 5 , Kim discloses (See, for example, Fig. 5 ) a lower width of the backside-connecting via (250 is wider at the bottom, See Fig. 2)) beneath the first spacer and the second spacer (below 164 ) is wider than (250 gets narrow towards to the spacers) a middling width (width below the top surface of the 250T) of the backside-connecting via (250) between the first spacer and the second spacer. In regards to claim 6 , Kim discloses (See, for example, Fig. 2) the first spacer and the second spacer comprise an isolating dielectric metal (“filling insulation portion 164”, See, for example, Par [0066]) . In regards to claim 11 , Kim discloses (See, for example, Figs. 2 and 3) the first spacer (164) and a first additional spacer (162b) surround the first transistor (surround the first active fin 105; See also Pars [0030] and [0035]) ; and the second spacer (164) and a second additional spacer (162b) surround the second transistor (surround the first active fin 105; See also Pars [0030] and [0035]) . In regards to claim 13 , Kim discloses (See, for example, Figs. 2-3, Kim) that a third transistor is surrounded by a third spacer and a third additional spacer; and the third transistor is not in contact with the backside-connecting via (a plurality of active fins 105 arranged on the active region 102, See Figs. 1 and 2 and Par [0027]. The active fins 105 that are not adjacent to the trench ST containing the buried conductive wiring 120 and the conductive through structure 250 are not in contact with the backside-connecting via. These non-adjacent transistors are surrounded by respective portions of the device isolation layer 162 on their respective sides, including 162b, See also Par [0030]) . In regards to claim 14 , Kim discloses (See, for example, Figs. 2-3) the first transistor and the second transistor are selected from a group consisting of a fin field effect transistor ( FinFET ), a vertical transport FET (VTFET), a semiconductor memory structure, and combinations thereof (See Pars [0027] and [0028] where the transistors are FINFET devices formed on active fins 105 with source/drain regions 110 and gate structures GS) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 3-4, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim . In regards to claim 3 , Kim discloses all limitations of claim 1 above except that the backside-connecting via is without metal voids. However, forming a conductive via without metal voids is a well known in the art of semiconductor metallization because having voids would increase electrical resistance and degrade device reliability. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to form the backside-connecting via without voids because it is well-known in the art of semiconductor metallization to have a connecting metal via without voids because having voids would increase electrical resistance and degrade device reliability. In regards to claim 4 , Kim discloses (See, for example, Figs. 2 and 3) the backside-connecting via (250) comprises a bottom in contact with the BPR (120) . Kim further teaches (See Par [0039]) that a n upper end or end portion 250T of the conductive through structure 250 may be located lower than a level L1 of an upper surface 102T of the active region 102. In this manner, mutual electrical interference may be suppressed by ensuring a sufficient distance from the active fin 105 without forming the conductive through structure 250 to the upper surface 102T of the active region 102. For example, the conductive through structure 250 may have a size (e.g., a diameter or a width) of 20 nm to 500 nm, and a distance (e.g., a depth) of 200 nm to 3000 nm. However, Kim fails to explicitly teach the backside-connecting via comprises a bottom in contact with the BPR, wherein a width of the bottom is at least one half of a top width of the backside-connecting via. It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to arrive at a bottom width that is at least one half of the top width since it has been held that such design choice would ensure reliable electrical connection, and where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art and . In re Aller, 105 USPQ 233. In regards to claim 10 , Kim as modified above discloses (See, for example, Fig. 2, Kim) the metal is selected from a group consisting of Cobalt (Co) and Tungsten (W) (See Pars [0056]) . In regards to claim 12 , Kim discloses (See, for example, Figs. 2-3) all limitations of claim 1 except that the first spacer and the second spacer have a thickness between five and twenty nanometers (nm). Notwithstanding, it would have been an obvious matter of design choice bounded by well - known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose , 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart , 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc. , 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey , 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff , 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990). Claim s 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Huang et al. (US 2022/0375860 A1, hereinafter “Huang”) . In regards to claims 7 and 8, Kim discloses all limitations of claim 6 above except that the isolating dielectric metal comprises a nitride based dielectric material ; and the nitride based dielectric material is selected from a group consisting of silicon nitride ( SiN.sub.x ), silicon boron carbonitride ( SiBCN ), silicon boronitride ( SiBN ), silicon carbon nitride ( SiCN ), silicon oxynitride ( SiON ), and combinations thereof. Huang while disclosing transistors having backside power rails teaches the isolating dielectric metal comprises a nitride based dielectric material ( The gate spacers 113 may include any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectric materials, and/or combinations thereof. The gate spacers 113 may have multiple films, such as dual films (e.g., a silicon oxide film and a silicon nitride film) or three films (a silicon oxide film; a silicon nitride film; and a silicon oxide film). , See Fig. 17, See Par [0036]) ; and the nitride based dielectric material is selected from a group consisting of silicon nitride ( SiN.sub.x ), silicon boron carbonitride ( SiBCN ), silicon boronitride ( SiBN ), silicon carbon nitride ( SiCN ), silicon oxynitride ( SiON ), and combinations thereof (See, for example, Par [0036]) . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Huang because having the dielectric material of Huang would help provide etch selectivity during backside processing and enhanced dielectric isolation between the conductive through structure a n d adjacent active regions . Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Ju et al. (US 2021/0351303 A1, hereinafter “Ju”) . In regards to claim 9 , Kim discloses all limitations of claim 1 above except that each of the first transistor and the second transistor comprises a nanosheet device; and the first spacer and the second spacer each comprise a nanosheet spacer. Ju while disclosing back-side power rail device teaches (See, for example, Fig. 1) each of the first transistor and the second transistor comprises a nanosheet device (See, for example, Pars [0025], [0038] -[ 0039]) ; and the first spacer and the second spacer each comprise a nanosheet spacer (inner 128, and 134, See also Pars [0025], [0048], and [0051]) . Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Kim by Ju because this would offer superior electrostatic control, reduced sub0channel leakage, variable sheet width for flexible power performance optimization, and compatibility with backside power rail configurations. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350 . The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T. . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270- 3042 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERMIAS T WOLDEGEORGIS/ Primary Examiner, Art Unit 2893