DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 10/24/2023 has been considered.
Drawings
The drawings filed on 12/30/2022 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 12/30/2022 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chang (US 2021/0375761).
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Regarding claim 1, Chang (US 2021/0375761) discloses:
A monolithic semiconductor structure, comprising:
a device layer having a front side and a back side, the device layer comprising:
a front side interlevel dielectric layer (96, ¶0054); and
a field-effect transistor within the front side interlevel dielectric layer, the field- effect transistor including a channel region (55, ¶0013), a gate (102, ¶0014) adjoining the channel region (55), and first and second source/drain regions (92, ¶0014) extending laterally from the channel region;
a back-end-of-line interconnect layer (120, ¶0070) over the front side of the device layer, the back-end- of-line interconnect layer (120) being electrically connected to the device layer (through gate contact 114, ¶0063);
a back side interlevel dielectric layer (125, ¶0080) over the back side of the device layer;
a back side source/drain contact (129 and 130 taken together extending from S/D 92, ¶0067 ¶0082, ¶0084) comprising metal (¶0084, ¶0067), the back side source/drain contact (129/130) directly contacting a bottom surface of the first source/drain region (92) and extending within the back side interlevel dielectric layer (125); and
a bottom dielectric isolation layer structure (100, ¶0081) comprising a horizontal portion and a pair of vertical portions extending from the horizontal portion, the horizontal portion being between the gate (102) and the back side interlevel dielectric layer (125) , the pair of vertical portions adjoining the back side source/drain contact (129/130, figure 27a-c).
Regarding claim 2, Chang further discloses:
a front side source/drain contact (110 and 112 taken together, ¶0067) comprising metal (¶0067) and directly contacting a top surface of the second source/drain region (92), the front side source/drain contact (112) being electrically connected to the back-end-of-line interconnect layer (120; and
a back side interconnect layer (140) over the back side of the device layer, the back side source/drain contact (129, 130) being electrically connected to the back side interconnect layer (140).
Regarding claim 3, Chang further discloses:
wherein the pair of vertical portions of the bottom dielectric isolation layer structure (100) adjoin the gate (102) and the back side interlevel dielectric layer (125).
Regarding claim 4, Chang further discloses:
shallow trench isolation regions (68, ¶0081) within the back side interlevel dielectric layer (125), the pair of vertical portions of the bottom dielectric isolation layer structure (100) extending, respectively, between the back side source/drain contact (129/130) and a pair of the shallow trench isolation regions (68).
Regarding claim 5, Chang further discloses:
wherein the channel region (55) comprises a stack of nanosheet semiconductor layers (¶0013).
Regarding claim 6, Chang further discloses:
a gate stack (102) between the nanosheet semiconductor layers, the gate stack comprising the gate (102), the horizontal portion of the bottom dielectric isolation layer structure (100) adjoining a bottom surface of the gate stack.
Regarding claim 7, Chang further discloses:
a carrier wafer (150, ¶0075) bonded to a top surface of the back-end-of-line interconnect layer (120).
Regarding claim 8, Chang further discloses:
wherein the shallow trench isolation regions (68) extend deeper into the back side interlevel dielectric layer (125) than the pair of vertical portions of the bottom dielectric isolation layer structure (100).
Regarding claim 9, Chang discloses:
A monolithic semiconductor structure, comprising:
a device layer including a front side and a back side, the device layer comprising:
a front side interlevel dielectric layer (96); and
field-effect transistors within the front side interlevel dielectric layer, each of the field-effect transistors including a channel region (55), a gate (102) adjoining the channel region (55), and first and second source/drain regions (92) extending laterally from the channel region;
a back-end-of-line interconnect layer (120) over the front side of the device layer, the back-end- of-line interconnect layer (120) being electrically connected to the device layer (through gate contact 114, ¶0063);
a back side interlevel dielectric layer (125) over the back side of the device layer;
back side source/drain contacts (129/130) comprising metal (¶0084, ¶0067), each of the back side source/drain contacts directly contacting, respectively, one of the first and second source/drain regions of one of the field-effect transistors and extending within the back side interlevel dielectric layer (125); and
bottom dielectric isolation layer structures (100) comprising, respectively, horizontal portions and pairs of vertical portions extending, respectively, from each of the horizontal portions, each of the horizontal portions being between the gate (102) of one of the field-effect transistors and the back side interlevel dielectric layer (125), each of the pairs of vertical portions adjoining, respectively, one of the back side source/drain contacts (129/130).
Regarding claim 10, Chang further discloses:
wherein the device layer comprises an integrated circuit and the second source/drain regions (92) of a plurality of the field-effect transistors are electrically connected, respectively, to front side source/drain contacts (112) extending within the front side interlevel dielectric layer (96).
Regarding claim 11, Chang further discloses:
wherein each of the pairs of vertical portions of each bottom dielectric isolation layer structure (100) adjoins the gate (102) of one of the field- effect transistors and the back side interlevel dielectric layer (125).
Regarding claim 12, Chang further discloses:
shallow trench isolation regions (68) within the back side interlevel dielectric layer (125), each pair of vertical portions of each bottom dielectric isolation layer structure (100) extending, respectively, between the back side source/drain contact (129/130) of one of the field-effect transistors and a pair of the shallow trench isolation regions (68).
Regarding claim 13, Chang further discloses
wherein the channel region (55) of each of the field-effect transistors comprises a stack of nanosheet semiconductor layers (¶0013).
Regarding claim 14, Chang further discloses:
a gate stack between the nanosheet semiconductor layers of each of the field-effect transistors, the gate stack comprising the gate (102) of each field-effect transistor, the horizontal portion of each bottom dielectric isolation layer structure (100) adjoining a bottom surface of the gate stack of one of the field-effect transistors.
Regarding claim 15, Chang further discloses:
a carrier wafer (150, ¶0075) bonded to a top surface of the back-end-of-line interconnect layer (120).
Regarding claim 16, Chang further discloses:
wherein the shallow trench isolation regions (68) extend deeper into the back side interlevel dielectric layer (125) than the pair of vertical portions of the bottom dielectric isolation layer structure (100).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, the prior art does not disclose “a first bottom dielectric isolation layer extending horizontally over the semiconductor substrate; a second bottom dielectric isolation layer beneath and extending parallel to the first bottom dielectric isolation layer, a top layer of the semiconductor substrate being between the first bottom dielectric isolation layer and the second bottom dielectric isolation layer, the first dielectric isolation layer including an opening exposing a top surface portion of the top layer of the semiconductor substrate”, “growing first and second source/drain regions, the first source/drain region being grown on first exposed edge portions of the semiconductor channel layers and on the sacrificial semiconductor placeholder, the second source/drain region being grown on second exposed edge portions of the semiconductor channel layers and on the top surface portion of the top layer of the semiconductor substrate”, “replacing the sacrificial gate with a metal gate”, and “replacing the sacrificial placeholder with a back side source/drain contact comprising metal” in combination with the remaining claimed features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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