DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/27/2026 has been entered. Claims 1-19 and newly added claim 20, remain pending in the application. Claims 4-15 have been withdrawn as corresponding to non-elected species.
Specification
The disclosure is objected to because of the following informalities: for paragraph numbers greater than 100, the format should include only one “0” before the number (Example: [00100] should read [0100]). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek (United States Patent Application Publication Number, US 2020/0105783 A1), hereinafter referenced as Baek.
Regarding claim 1, Baek teaches a semiconductor structure, comprising: a stack structure comprising gate layers and first dielectric layers disposed alternately (Fig.2, gate layers, element #180a, and dielectric layers, element #120a are disposed alternately); first gate isolation structures extending along a first direction and arranged at intervals along a second direction (insulation layer, element #190 showed in Fig.3 as part of element #160 showed in Fig.1, extends in the horizontal direction at intervals along the vertical direction), first gate isolation structures dividing the stack structure (Fig.3, left and right elements #190 divide the structure) into at least one block (Fig.1, block between the top and bottom elements #190, corresponding to top and bottom elements #160, respectively) comprising a memory region (Fig.1, memory cell, element #A, paragraph [0033], rows 3-4) and a connection region (Fig.1, memory cell, element #B, paragraph [0033], rows 4-5) that are distributed along the first direction (Fig.1, elements #A and #B are distributed along horizontal direction), the first direction being perpendicular to the second direction (Fig.1, horizontal direction is perpendicular to the vertical direction); and conductive structures in the connection region (Fig.1, elements #202, paragraph [0031], rows 3-5), each conductive structure being electrically connected with one gate layer, and different conductive structures being electrically connected with different gate layers (paragraph [0075], rows 10-12, and paragraph [0154], rows 8-16), any two adjacent ones of the conductive structures having a spacing therebetween (Fig.1, elements #202 have a spacing therebetween), each conductive structure comprising an upper end and a lower end opposite to the upper end, the lower end being disposed in the same layer as the gate layer (Fig.33A, element #200 comprises an upper end, which is the top end of element #200 and a lower end opposite to the upper end, element #270b, the lower end being disposed in the same layer as the gate layer, paragraph [0172], rows 1-5) and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction (Fig.3, upper ends of elements #202 are located at the same vertical height, paragraph [0076], rows 2-4, and in Fig.1 are arranged in columns along the vertical direction, each column including two elements; therefore, the orthographic projections of upper ends of the two elements #202 disposed in the same column overlap in a reference plane perpendicular to vertical direction).
Regarding claim 2, Baek teaches the semiconductor structure of claim 1 as set forth in the anticipation rejection. Baek further teaches the semiconductor structure of claim 1, wherein the conductive structures are arranged in multiple columns, each column including at least two conductive structures disposed along the second direction each column including two elements (Fig.1, elements #202 are arranged in columns along the vertical direction, each column including two elements #202), and the orthographic projections of the upper ends of the at least two conductive structures of the same column on the reference plane overlapping (Fig.3, upper ends of elements #202 are located at the same vertical height, paragraph [0076], rows 2-4, and in Fig.1 are arranged in columns along the vertical direction, each column including two elements; therefore, the orthographic projections of upper ends of the two elements #202 disposed in the same column overlap in a reference plane perpendicular to vertical direction).
Regarding claim 18, Baek teaches the semiconductor structure of claim 1 as set forth in the anticipation rejection. Baek teaches a three-dimensional (3D) memory, comprising: a semiconductor structure (Fig.2) comprising: a stack structure comprising gate layers and first dielectric layers disposed alternately (Fig.2, gate layers, element #180a, and dielectric layers, element #120a are disposed alternately); first gate isolation structures extending along a first direction and arranged at intervals along a second direction (insulation layer, element #190 showed in Fig.3 as part of element #160 showed in Fig.1, extends in the horizontal direction at intervals along the vertical direction), the first gate isolation structures dividing the stack structure (Fig.3, left and right elements #190 divide the structure) into at least one block (Fig.1, block between the top and bottom elements #190, corresponding to top and bottom elements #160, respectively) comprising a memory region (Fig.1, memory cell, element #A, paragraph [0033], rows 3-4) and a connection region (Fig.1, memory cell, element #B, paragraph [0033], rows 4-5) that are distributed along the first direction (Fig.1, elements #A and #B are distributed along horizontal direction), the first direction being perpendicular to the second direction (Fig.1, horizontal direction is perpendicular to the vertical direction); and conductive structures in the connection region (Fig.1, elements #202, paragraph [0031], rows 3-5, each conductive structure being electrically connected with one gate layer, and different conductive structures being electrically connected with different gate layers (paragraph [0075], rows 10-12 and paragraph [0154], rows 8-16), any two adjacent ones of the conductive structures having a spacing therebetween (Fig.1, elements #202 have a spacing therebetween), each conductive structure comprising an upper end and a lower end opposite to the upper end, the lower end being aligned with the one the gate layer (Fig.33A, element #200 comprises an upper end, which is the top end of element #200 and a lower end opposite to the upper end, element #270b, which is horizontal and therefore aligned with the gate layer) and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction(Fig.3, upper ends of elements #202 are located at the same vertical height, paragraph [0076], rows 2-4, and in Fig.1 are arranged in columns along the vertical direction, each column including two elements; therefore, the orthographic projections of upper ends of the two elements #202 disposed in the same column overlap in a reference plane perpendicular to vertical direction); and a periphery device electrically connected with the semiconductor structure (paragraph [0034], rows 3-5, paragraph [0075], rows 10-12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Baek, in view of Liu et al., (United States Application Publication Number, US 2020/0235121 A1) hereinafter referenced as Liu.
Regarding claim 3, Baek teaches the semiconductor structure of claims 1 and 2 as set forth in the anticipation rejection. Baek does not teach the semiconductor structure of claim 2, wherein a spacing between the upper ends of two adjacent ones of the conductive structures of the same column is greater than or equal to 500 nm. Liu teaches the semiconductor structure wherein a spacing between the upper ends of two adjacent ones of the conductive structures of the same column may range from 250nm to about 1400nm (Fig.1B, the distance between conductive structures, elements #116 located in the connection region, element #130, is between 250nm and 1400nm, paragraph [0048], rows 15-17). The claimed range, greater than or equal to 500nm, overlaps with the range disclosed by Liu and therefore a prima facie case of obviousness exists (MPEP 2144.05). As disclosed by Liu, stress exists in the metal layer(s) of the conductive structures and the dielectric layer(s) surrounding them, and spacing apart the adjacent conductive structures in the same column can help mitigate this stress.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Baek, in view of Kim et al., (United States Application Publication Number, US 2022/0115344 A1) hereinafter referenced as Kim.
Regarding claim 19, Baek teaches a memory system, comprising: a three-dimensional (3D) memory comprising (Fig.1 and Fig.2): a semiconductor structure comprising (Fig.2): a stack structure comprising gate layers and first dielectric layers disposed alternately (Fig.2, gate layers, element #180a, and dielectric layers, element #120a are disposed alternately); first gate isolation structures extending along a first direction and arranged at intervals along a second direction (insulation layer, element #190 showed in Fig.3 as part of element #160 showed in Fig.1, extends in the horizontal direction at intervals along the vertical direction), the first gate isolation structures dividing the stack structure (Fig.3, left and right elements #190 divide the structure) into at least one block (Fig.1, block between the top and bottom elements #190, corresponding to top and bottom elements #160, respectively) comprising a memory region (Fig.1, memory cell, element #A, paragraph [0033], rows 3-4) and a connection region (Fig.1, memory cell, element #B, paragraph [0033], rows 4-5) that are distributed along the first direction (Fig.1, elements #A and #B are distributed along horizontal direction), the first direction being perpendicular to the second direction (Fig.1, horizontal direction is perpendicular to the vertical direction); and conductive structures in the connection region (Fig.1, elements #202, paragraph [0031], rows 3-5, each conductive structure being electrically connected with one gate layer, and different conductive structures being electrically connected with different gate layers (paragraph [0075], rows 10-12 and paragraph [0154], rows 8-16), any two adjacent ones of the conductive structures having a spacing therebetween (Fig.1, elements #202 have a spacing therebetween), each conductive structure comprising an upper end and a lower end opposite to the upper end, the lower end being aligned with the one gate layer,
(Fig.33A, element #200 comprises an upper end, which is the top end of element #200 and a lower end opposite to the upper end, element #270b, which is horizontal and therefore aligned with the gate layer) and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction (Fig.3, upper ends of elements #202 are located at the same vertical height, paragraph [0076], rows 2-4, and in Fig.1 are arranged in columns along the vertical direction, each column including two elements; therefore, the orthographic projections of upper ends of the two elements #202 disposed in the same column overlap in a reference plane perpendicular to vertical direction); and a periphery device electrically connected with the semiconductor structure (paragraph [0034], rows 3-5, paragraph [0075], rows 10-12).
Baek does not teach a controller electrically connected with the 3D memory to control the 3D memory to store data. Kim teaches a controller electrically connected with a 3D memory to control the 3D memory to store data (Fig.18, element #1200, paragraph [0133], rows 3-6 and paragraph [0141], rows 8-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kim and disclose a controller electrically connected with the 3D memory to control the 3D memory to store data. As disclosed by Kim, the controller allows access to and control of the 3D memory in response to commands according to a predetermined firmware.
Claims 1, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al., (United States Patent Application Publication Number, US 2019/0019872 A1), hereinafter referenced as Lim, in view of Baek.
Regarding claim 1, Lim teaches a semiconductor structure, comprising: a stack structure comprising gate layers and first dielectric layers disposed alternately (Fig.11L, gate layers, element #230, and dielectric layers, element #220); first gate isolation structures extending along a first direction and arranged at intervals along a second direction (Fig.10, regions between stack structures #ST have isolation trenches, elements #227, extending along horizontal direction and arranged along vertical direction), first gate isolation structures dividing the stack structure into at least one block comprising a memory region and a connection region that are distributed along the first direction (Fig.10, elements #ST comprise a memory region, element #DR and a connection region, element #CR), the first direction being perpendicular to the second direction (Fig.10, horizontal direction is perpendicular to the vertical direction), and conductive structures in the connection region (Fig.11L, elements #260), each conductive structure being electrically connected with one gate layer and different conductive structures being electrically connected with different gate layers (Fig.11L, each element #260 is connected to one gate layer, element #230, and different elements #260 are connected to different elements #230), any two adjacent ones of the conductive structures having a spacing therebetween (Fig.11L, elements #260 have a spacing therebetween), each conductive structure comprising an upper end and a lower end opposite to the upper end, the lower end being disposed in the same layer as the gate layer (Fig.11L, upper end is the top end and lower end in the bottom end, lower end is disposed in the same layers as the gate layers, elements #230).
Lim does not teach orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction. Lim teaches the conductive structures are arranged in multiple columns, each column including a conductive structure disposed along the second direction (Fig.10), and upper ends of the conductive structures are located at the same vertical height( Fig.11L). Baek teaches wherein the conductive structures are arranged in multiple columns, each column including at least two conductive structures disposed along the second direction (Fig.1, elements #202 are arranged in columns along the vertical direction, each column including two elements #202), and orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction (Fig.3, upper ends of elements #202 are located at the same vertical height, paragraph [0076], rows 2-4, and in Fig.1 are arranged in columns along the vertical direction, each column including two elements; therefore, the orthographic projections of upper ends of the two elements #202 disposed in the same column overlap in a reference plane perpendicular to vertical direction). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Baek and disclose the conductive structures are arranged in multiple columns, each column including at least two conductive structures disposed along the second direction orthographic projections of upper ends of at least two of the conductive structures on a reference plane at least partially overlapping, and the reference plane being perpendicular to the second direction. Arranging the conductive structures in columns including at least two conductive structures, and having the orthographic projections of the conductive structures at least partially overlap in a plane parallel to the fist direction and perpendicular to the second direction, provides a reduce device footprint the first direction.
Regarding claim 16, the combination of Lim and Baek teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Lim further teaches the semiconductor structure of claim 1, wherein each of the conductive structures comprises: a first portion disposed in the same layer as the gate layer and electrically connected with the gate layer the first portion being the lower end of the conductive structure (Fig.11L, element #261); and a second portion connected with the first portion and running through the stack structure upwards (Fig.11L, element #262), an orthographic projection of the second portion on the first portion being located within extent of the first portion (Fig.1A and 1B, teaches the orthographic projection of the second portion, element #162, which is equivalent with element #262, on the first portion, element #161 which is equivalent to element #262, being located within extent of the first portion).
Regarding claim 20, the combination of Lim and Baek teaches the semiconductor structure of claim 1 as set forth in the obviousness rejection. Lim further teaches the semiconductor structure of claim 1, wherein in the stack structure, the gate layers and the first dielectric layers are disposed alternately along a third direction perpendicular to the first direction and the second direction (Fig.11L layers #230 and #220 are disposes alternately along vertical direction, D3, which is perpendicular to the first and second directions, D1 and D2, see Fig.10 for directions), and the different conductive structures are different in size from the upper end to the lower end along the third direction (Fig.11L, the size increases form the lower end to the upper end, see also Fig.1A and 1B).
Allowable Subject Matter
Claim 17 is allowed if written in independent form.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 17, the cited prior art does not teach or fairly suggests, along with other
claimed features: “wherein the gate layer comprises a body portion in the memory region, and second conductive pathways on two sides of the first gate isolation structures, the second conductive pathways extending along the first direction, and being electrically connected with the body portion, and the first portion being electrically connected with the second conductive pathway;”.
Response to Arguments
Applicant’s arguments filed on 01/27/2026 have been fully considered but they
are not persuasive.
Applicant’s arguments with respect to claims 1 and 18 have been considered but are not considered persuasive. As noted in the above rejection of claim 1, Fig.33A of Baek shows the conductive structure, element #202, having a lower, element #207b, aligned with the gate layer #180. Furthermore, claim 1 was also rejected using the combination of the Lim and Baek, based on new ground of rejection that does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claim 20 have been considered but are moot since the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899