DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-15 are pending in this application. Acknowledgement is made of the amendment received 4/20/26 cancelling claims 16-20.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-15) in the reply filed on 4/20/26 is acknowledged. Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Claims 1-15 are examined in this Office action.
Information Disclosure Statement
An information disclosure statement has not been received. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 7, and 11 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Lilak et al. (US Patent Application Publication No 2021/0305388) hereinafter referred to as Lilak.
Per Claim 1 Mishra discloses a transistor structure device, (see figure 2A) comprising
a first channel material layer (106, upper) in a stack with a second channel material layer (106 lower), wherein each of the first and second channel material layers span a distance between a source terminal (214, left) and a drain terminal (214, right); (as in figure 1A)
a dielectric material layer (112) between the first and second channel material layers, wherein the dielectric material layer also spans the distance between the source and drain terminals; (as in figure 1A) and
a gate structure (including (108 and 110)) between the first and second channel material layers, wherein the gate structure spans less than the distance between the source terminal and the drain terminal, and wherein the gate structure comprises: (as in figure 1A)
a gate insulator (110) in contact with the dielectric material layer; and
a gate material (108) in contact with the gate insulator (as in figure 1A)
Per Claim 6 Mishra discloses the device of claim 1 including where the dielectric material layer (112) is in direct contact with the first channel material layer (106, upper) or the second channel material layer (106, lower) (as in figure 1A)
Per Claim 7 Mishra discloses the device of claim 6 including where the dielectric material layer (112, upper) is in direct contact with the first channel material layer (106, upper) and the transistor structure further comprises a second dielectric material layer (112, lower) in direct contact with the second channel material (106 lower). (as in figure 1A)
Per Claim 11 Mishra discloses the device of claim 1 including where the gate structure is between the dielectric material layer and the first channel material layer.
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Claims 13 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Nidhi et al. (US Patent Application Publication No 2021/0184032) hereinafter referred to as Nidhi.
Per Claim 13 Nidhi discloses a system device, (see figure 2A) comprising
an integrated circuit (IC) die (100) comprising a transistor structure, the transistor structure (see [0013]) comprising:
a stack of nanoribbons (110) coupled between a source terminal (S) and a drain terminal (D);
a gate structure (130) coupled to channel regions of the nanoribbons, the gate structure comprising a gate insulator (131) and a gate material (135); and
an intervening dielectric material layer (118/140) between each of the nanoribbons and in contact with the source terminal and drain terminal, the intervening dielectric material layer having a different composition than the gate insulator; and
a spacer between the source or drain structure and the gate structure (132); and
a power supply (battery) coupled to the IC die (see figure 6).
Allowable Subject Matter
Claims 2-5, 8-10, 12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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