DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Interview
Applicant’s arguments see page 7 of Remarks, filed on 12/23/2025 with respect to the Examiner Interview summary, seems to state that the proposed amendment would overcome the 35 U.S.C § 103 rejection of the Non-Final Office Action mailed on 10/01/2025, while the summary of the interview reflects that the proposed amendment of claim 10 appears to overcome the 35 U.S.C § 103 rejection of the Non-Final Office Action mailed on 10/01/2025 but that further search and consideration are required.
In response to page 8 of the Remarks dated filed on 12/23/2025 , Examiner clarifies that the parties agreed that the amendments filed on 12/23/2026 would appear to overcome the prior art as applied in the Office Action mailed on 10/01/2025, however claim 10 is not in condition for allowance as discussed in the Claim Rejections - 35 USC § 103 section below.
Election/Restrictions
Claims 1-9 are canceled and claims 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025. Claims 10-14 and 18-29 are still pending.
Response to Amendment
The amendment filed on 12/23/2025 has been accepted and entered. Claims 10-14 and 18-29 remain pending in this application. Applicant’s amendments to the Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed on 10/01/2025.
Claim Objections
Claims 22-27 and 29 is/are objected to because of the following informalities:
Claim 22 recites " the interleaved second dielectric layers and first dielectric layers" in line 3, but should read -- the interleaved second dielectric layers and the first dielectric layers--.
Claim 24 recites " the interleaved second dielectric layers and first dielectric layers" in line 4, but should read -- the interleaved second dielectric layers and the first dielectric layers--.
Claim 25 recites " the interleaved second dielectric layers and first dielectric layers" in line 3, but should read -- the interleaved second dielectric layers and the first dielectric layers--.
Claim 26 recites " the interleaved second dielectric layers and first dielectric layers" in lines 3-4, but should read -- the interleaved second dielectric layers and the first dielectric layers--.
Claim 29 recites " the interleaved second dielectric layers and first dielectric layers" in line 3, but should read -- the interleaved second dielectric layers and the first dielectric layers--.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11, 13-14, 18-19, and 21-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), and further in view of Izumi et al. (US20160093524A1-Izumi24).
Regarding claim 10, Baek83 discloses a three-dimensional (3D) memory device (Vertical memory device-Title), comprising:
a first region of a stack structure (first region 50-Fig 1), the first region comprising
interleaved conductive layers (gate electrode 180a-Fig 2, [0052] L 1-3) and
first dielectric layers (First dielectric 120a-Fig 2; layer 120a may include silicon oxide-[0066] L 9-11; 180a and 120a are spaced apart from each other so interleaved-[0044] Lines L1-6, Fig 2);
a second region of the stack structure, (second region 52-Fig 1), the second region comprising interleaved second dielectric layers (second dielectric layers 122a-Fig 2; 122a may include silicon nitride, silicon oxynitride-[0066] L9-11 ) and
the first dielectric layers(122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2); and
word line pick-up structures (two word line pick-up structures 202-Fig 3),
each extending along a sidewall of an opening into the second region of the stack structure (structures 202 vertically extending along an opening 192 in the second region 52-Fig 1, Fig2, Fig28).
Baek83 does not teach a three-dimensional (3D) memory device
wherein a buffer comprising a dielectric material and
covering the sidewall
is disposed between the second dielectric layers and one of the word line pick-up structures,
wherein a surface of the buffer has a plurality of bumps along a direction parallel to the sidewall, and
wherein bottommost ends of the word line pick-up structures are arranged at different depths and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths.
Ahn97 teaches a three-dimensional (3D) memory device
wherein a buffer comprising a dielectric material (insulating layer 146-Examiner's annotated Fig 26)
covering the sidewall (Layer 146 covering the sidewall of the word line pick-up structure WLC-Examiner's annotated Fig 26)
is disposed between the second dielectric layers and the word line pick-up structure (Layer 146 is between the layers 120 and the word line pick-up structure WLC-Examiner's annotated Fig 26), and
wherein a surface of the buffer has a plurality of bumps along a direction parallel to the sidewall (bumps on layer 146on the vertical sidewall-Examiner's annotated Fig 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 as taught by Ahn97 for the purpose of improving the semiconductor device reliability (Ahn97: [0116] L 8-9).
Ahn97 does not teach a three-dimensional (3D) memory device
wherein bottommost ends of the word line pick-up structures are arranged at different depths and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths.
Izumi24 teaches a three-dimensional (3D) memory device
wherein bottommost ends of the word line pick-up structures are arranged at different depths (Bottommost ends of the word line 66 A/B/C/D/E/F are arranged at different depths-Examiner’s annotated Fig 16) and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths (Bottommost ends of the word line 66 A/B/C/D/E/F are connected to respective conductive layers 46A/B/C/D/E/F, corresponding at different depths-Examiner’s annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
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Regarding claim 11, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Ahn97 further teaches a three-dimensional (3D) memory device
wherein a contact spacer (182-Examiner's annotated Fig 26) is formed between the buffer and the one of the word line pick-up structures (contact spacer 182 formed between buffer 146 and word-line pick up structure WLC-Examiner's annotated Fig 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Izumi24 as taught by Ahn97 for the purpose of improving the semiconductor device reliability (Ahn97: [0116] L 8-9).
Regarding claim 13, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures comprises: an interconnect line at a bottom of the word line pick-up structure (interconnect line 108a at the bottom of word line pick-up structure 202-Fig 3, [0037] L5-6),
wherein the interconnect line is in contact with one of the conductive layers ( (Lower wiring 108 includes the interconnect line 108 a- [0037] L 1-2; pad pattern 180c connected to conductive layers 180a and lower wiring 108-[0060] L 3-5; so interconnect line 108a is connected to conductive layer 180a) ;
a contact structure electrically coupled to the interconnect line (contact structure 180c coupled to interconnect line 202a-Fig 33A, [0171] L 1-3); and
a filler that fills a remaining portion of the opening (filler 202 filling opening 192-Fig 28, Fig 29).
Regarding claim 14, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Ahn97 further teaches a three-dimensional (3D) memory device
wherein each of the plurality of bumps laterally corresponds to one of the first dielectric layers in the second region of the stack structure (bumps corresponding to layer 120-Examiner's annotated Fig 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Izumi24, as taught by Ahn97 for the purpose of improving the semiconductor device reliability (Ahn97: [0116] L 8-9).
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Regarding claim 18, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the sidewall of the opening has a sidewall shoulder (Sidewall of 202a has a shoulder 270b-Examiner's annotated Fig 33B).
Regarding claim 19, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the word line pick-up structures extend into the second region of the stack structure at different depths (Sidewall of 202a has a shoulder 270b so two different depths-Examiner's annotated Fig 33B).
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Regarding claim 21, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device (Vertical memory device-Title) wherein:
the second region of the stack structure (second region 52-Fig 1) comprising
the interleaved second dielectric layers (second dielectric layers 122a-Fig 2; 122a may include silicon nitride, silicon oxynitride-[0066] L9-11 ) and
the first dielectric layers(122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2).
Baek83 and Ahn97 combination does not disclose a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures vertically extends through only a portion of the second region of the stack structure.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures vertically extends through only a portion of the second region of the stack structure (the one of the word line structures 66 D vertically extends through only the top portion of the second region of the stack structure-Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
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Regarding claim 22, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 21, as noted above.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures extends through a first portion of the second region of the stack structure comprising the interleaved second dielectric layers and first dielectric layers (Top portion of the second region 300 above the one of the word line pick-up structures 66D-Examiner's annotated Fig 16),
a second portion of the second region of the stack structure being arranged below the one of the word line pick-up structures (Second/Bottom portion of the second region 300 below the one of the word line pick-up structures 66D -Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
Regarding claim 23, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 22, as noted above.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein an interconnect line is interposed between the first portion of the second region of the stack structure and the second portion of the second region of the stack structure (Interconnect line/ conductive line 46C interposed between the first portion and the second portion, connected to word line structure 66D -Examiner's annotated Fig 16),
the one of the word line pick-up structures being electrically connected to a corresponding conductive layer through the interconnect line (Interconnect line/ conductive line 46C interposed between the first portion and the second portion, connected to word line structure 66D and conductive line 46C -Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
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Regarding claim 24, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein the bottommost ends of the word line pick-up structures are electrically connected to the respective conductive layers through respective interconnect lines interposed in the second region of the stack structure comprising the interleaved second dielectric layers and first dielectric layers (Bottommost ends of the word line pick-up structures 66 A/B/C/D/E/F electrically connected to respective Interconnect line/ conductive line 46F/E/D/C/B/A interposed in the second region 300 -Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
Regarding claim 25, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device (Vertical memory device-Title)
wherein the word line pick-up structures (two word line pick-up structures 202-Fig 3) extend through the second region of the stack structure comprising the interleaved second dielectric layers and first dielectric layers (word line pick-up structures 202 vertically extending through the second region 52 comprising interleaved second dielectric layers 122a and first dielectric layers 120a, 122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2-Fig 1, Fig2, Fig28),
dummy channel structures being arranged in the second region of the stack structure (Dummy channel structures 150 arranged in second region 52-Fig 1, [0069]).
Regarding claim 26, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures (word line pick-up structures 202-Fig 3) comprises
a contact structure extending through the second region of the stack structure comprising the interleaved second dielectric layers and first dielectric layers (word line pick-up structures 202 comprising contact structure 202 vertically extending through the second region 52 comprising interleaved second dielectric layers 122a and first dielectric layers 120a, 122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2-Fig 1, Fig2, Fig28),
the contact structure being electrically connected with a corresponding conductive layer through an interconnect line interposed in the second region of the stack structure (word line pick-up structures/contact structures 202 electrically connected with a corresponding conductive layer 180a through an interconnect line 180c interposed in the second region 52 of the stack structure-[0060] L3-5, Fig 2).
Regarding claim 27, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 26, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the interconnect line extends laterally in the second region of the stack structure (interconnect line 180c laterally/horizontally extending in the second region 52 of the stack structure-[0060] L1-5, Fig 2).
Baek83 and Ahn97 combination does not teach a three-dimensional (3D) memory device
wherein the interconnect line extends laterally below the one of the word line pick-up structures.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein the interconnect line extends laterally below the one of the word line pick-up structures (Interconnect line/ conductive line 46C laterally extending in the second region below the one of the word line structures 66D and conductive line 46C -Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
Regarding claim 28, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the word line pick-up structures are arranged between slit structures laterally extending in the second region (Word line pick-up structures 202 arranged between slit structures 160 laterally extending in the second region 52-Fig 1).
Regarding claim 29, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 10, as noted above.
Baek83 further discloses a three-dimensional (3D) memory device
wherein the one of the word line pick-up structures extends through the second region of the stack structure comprising the interleaved second dielectric layers and first dielectric layers (word line pick-up structures 202 vertically extending through the second region 52 comprising interleaved second dielectric layers 122a and first dielectric layers 120a, 122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2-Fig 1, Fig2, Fig28); and
the one of the word line pick-up structures is electrically connected to a corresponding conductive layer, extending from the first region to the second region, through an interconnect line (one of word line pick-up structures/contact structures 202 electrically connected with a corresponding conductive layer 180a through an interconnect line 180c interposed in the second region 52 of the stack structure-[0060] L3-5, Fig 2)
Baek83 and Ahn97 combination does not teach a three-dimensional (3D) memory device wherein
Wherein the one of the word line pick-up structures electrically connected to a corresponding conductive layer below the one of the word line pick-up structures.
Izumi24 further teaches a three-dimensional (3D) memory device wherein
Wherein the one of the word line pick-up structures electrically connected to a corresponding conductive layer below the one of the word line pick-up structures(Interconnect line/ conductive line 46C laterally extending in the second region below the one of the word line structures 66D and conductive line 46C -Examiner's annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
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Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Lee et al. (US US9997537-Lee37).
Regarding claim 12, Baek83, Ahn97, and Izumi24 combination teaches all the elements of claim 11, as noted above.
Izumi24 further teaches a three-dimensional (3D) memory device
wherein the buffer comprises a dielectric material selected from a group consisting of silicon oxide, silicon oxynitride, and a mixture of silicon oxide and silicon oxynitride (buffer layer 64 comprises silicon oxide-[0083]L11-12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
Baek83, Ahn97, and Izumi24 combination does not teach a three-dimensional (3D) memory device
wherein the contact spacer and the buffer each comprise a dielectric material selected from a group consisting of silicon oxide, silicon oxynitride, and a mixture of silicon oxide and silicon oxynitride.
Lee37 teaches a three-dimensional (3D) memory device
wherein the contact spacer (contact spacer upper portion of 320-Examiner's annotated Fig 20) and the buffer (lower portion of 320-Examiner's annotated Fig 24) each comprise a dielectric material selected from a group consisting of silicon oxide, silicon oxynitride, and a mixture of silicon oxide and silicon oxynitride (Layer 320 is formed of silicon oxide-C20 L45-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the three-dimensional (3D) memory device of Baek83 in view of Ahn97, and further in view of Izumi24, as taught by Lee37 for the purpose of improving the breakdown voltage (Lee37: C5 L 35-37).
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Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Kim et al. (US20210265383-Kim83).
Regarding claim 20, Baek83 discloses a system (vertical memory device and wiring structure-[0002] L 1-4), comprising:
a three-dimensional (3D) memory device ( plurality of memory cells vertically stacked so a three-dimensional memory device),
the 3D memory device comprising:
a first region of a stack structure (first region 50-Fig 1),
the first region comprising interleaved conductive layers (gate electrode 180a-Fig 2) and first dielectric layers (First dielectric 120a-Fig 2; layer 120a may include silicon oxide-[0066] L 9-11; 180a and 120a are spaced apart from each other so interleaved-[0044] Lines L1-6, Fig 2);
a second region of the stack structure, (second region 52-Fig 1)
the second region comprising interleaved second dielectric layers (second dielectric layers 122a-Fig 2; 122a may include silicon nitride, silicon oxynitride-[0066] L9-11 ) and the first dielectric layers(122a and 120a are repeatedly stacked apart from each other so interleaved-[0066] L3-5, Fig 2); and
word line pick-up structures (two word line pick-up structures 202-Fig 3),
each extending along a sidewall of an opening into the second region of the stack structure (structures 202 vertically extending along an opening 192 in the second region 52-Fig 1, Fig2, Fig28).
Baek83 does not teach a system comprising
a 3D memory device configured to store data,
wherein a buffer comprising a dielectric material and
covering the sidewall
is disposed between the second dielectric layers and one of the word line pick-up structures,
wherein a surface of the buffer has a plurality of bumps along a direction parallel to the sidewall, and
wherein bottommost ends of the word line pick-up structures are arranged at different depths and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths, and
a memory controller coupled to the 3D memory device and configured to control the 3D memory device.
Ahn97 teaches a system
wherein a buffer (layer 146- Examiner's annotated Fig 26) covering the sidewall is disposed between the second dielectric layers and the word line pick-up structure (Layer 146 is between the layers 120 and the word line pick-up structure WLC-Examiner's annotated Fig 26), and
wherein a surface of the buffer has a plurality of bumps along a direction parallel to the sidewall (bumps on layer 146on the vertical sidewall-Examiner's annotated Fig 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Baek83 as taught by Ahn97 for the purpose of improving the semiconductor device reliability (Ahn97: [0116] L 8-9).
Ahn97 does not teach a system comprising
a 3D memory device configured to store data,
a memory controller coupled to the 3D memory device and configured to control the 3D memory device, and
wherein bottommost ends of the word line pick-up structures are arranged at different depths and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths.
Kim83 teaches a system comprising
a 3D memory device configured to store data ([0208] L1-2), and
a memory controller coupled to the 3D memory device and configured to control the 3D memory device ([0209], Fig 17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Baek83 in view of Ahn97 as taught by Kim83 for the purpose of reducing the interference between memory cells that are stacked (Kim83: [0057] L13-14).
Kim83 does not teach a system
wherein bottommost ends of the word line pick-up structures are arranged at different depths and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths.
Izumi24 teaches a system
wherein bottommost ends of the word line pick-up structures are arranged at different depths (Bottommost ends of the word line 66 A/B/C/D/E/F are arranged at different depths-Examiner’s annotated Fig 16) and
electrically connected to respective conductive layers, in the first region, corresponding to the different depths (Bottommost ends of the word line 66 A/B/C/D/E/F are connected to respective conductive layers 46A/B/C/D/E/F, corresponding at different depths-Examiner’s annotated Fig 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Baek83 in view of Ahn97, and further in view of Kim83, as taught by Izumi24 for the purpose of forming continuous contact without interface (Izumi24: [0101]).
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Response to Arguments
Applicant’s arguments see pages 7-12 of Remarks, filed on 12/23/2025 with respect to claim(s) 10-29 have been considered. The Remarks appear to assert that Baek et al. (US20200105783-Baek83) does not teach the newly added limitations; this assertion is addressed in the rejections set forth above.
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations of claims 10 and 20. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 10 and 20 have been amended to further define the claimed subject matter see pages 2-6 of Amendments to Claims, filed on 12/23/2025.
Claim(s) 10-11, 13-14, 18-19, and 21-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), and further in view of Izumi et al. (US20160093524A1-Izumi24), as described above.
Therefore, claim(s) 10-11, 13-14, 18-19, and 21-29 stand rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), and further in view of Izumi et al. (US20160093524A1-Izumi24).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Lee et al. (US US9997537-Lee37), as described above.
Therefore, claim(s) 12 stands rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Lee et al. (US US9997537-Lee37).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Kim et al. (US20210265383-Kim83), as described above.
Therefore, claim(s) 20 stands rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US20200105783-Baek83) in view of Ahn et al. (US 20200402997-Ahn97), in view of Izumi et al. (US20160093524A1-Izumi24), and further in view of Kim et al. (US20210265383-Kim83).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (US20240107761A1-Wang61) teaches a three-dimensional (3D) memory device comprising world line structures (106-Fig) wherein bottommost ends of the word line pick-up structures are arranged at different depths and electrically connected to respective conductive layers, in the first region, corresponding to the different depths (Fig 2, Fig 4).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 01/14/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812