Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/04/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8, 12-15 and 21-22, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (Pub. No.: US 2020/0006230).
Re claim 1, Tsai teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (54/46) disposed over a copper or copper alloy layer (132/62, FIG. 3B, [0032]);
forming a via opening (122, FIG. 3C) in the dielectric layer exposing a portion of the copper or copper alloy layer (132/62);
disposing a copper-barrier layer (bottom layer 142, [0032], note that “via barrier layer 142 includes more than is a via barrier multi-layer”) in the via opening, which directly contacts the exposed portion of the copper or copper alloy layer (62/132);
disposing an oxophilic layer (upper layer of 142, FIG. 3D, ¶ [0033], note that it is obvious that multi-layer is including at least more than one layer) on the copper-barrier layer;
after disposing the oxophilic layer (142), filling the via opening with tungsten to form a tungsten via (152, [0034]); and
forming an electronic device (82, [0022]) in electrical contact with the copper or copper alloy layer by way of the tungsten via;
wherein the deposition of the copper-barrier layer (bottom layer 142) and the deposition of at least an initial portion of the oxophilic layer (upper layer of 142) are performed in a same deposition chamber (note that “Via barrier layer 142 is conformally deposited by PVD, CVD, ALD, electroplating, electroless plating”, [0033] and it mentioned the single PVD or CVD).
Re claim 2, Tsai teaches the method of claim 1 wherein:
the disposing of the copper-barrier layer (bottom layer 142, [0033], note that barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) in the via opening includes disposing a tantalum layer, a tantalum nitride layer or a combination thereof; and
the disposing of the oxophilic layer includes disposing a titanium layer, a titanium nitride layer, or a combination thereof (upper layer of 142, note that via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride), said upper layer 142 is including titanium nitride this time) on the copper-barrier layer comprising the tantalum layer, the tantalum nitride layer, or the combination thereof.
Re claim 3, Tsai, FIG. 3F teaches the method of claim 1 wherein the disposing of the copper-barrier layer and the disposing of the tantalum nitride layer are performed using a single deposition chamber which is a chemical vapor deposition (CVD) chamber, physical vapor deposition (PVD) chamber, or a combined PVD/CVD chamber, and the semiconductor wafer is not exposed to air (note that “Via barrier layer 142 is conformally deposited by PVD, CVD, ALD, electroplating, electroless plating”, [0033] and it mentioned the single PVD or CVD) between the end of the disposing of the copper-barrier layer and an end of the disposing of the oxophilic layer (multiple layers of the same 142).
Re claim 4, Tsai, FIG. 3F teaches the method of claim 3 wherein the disposing of the oxophilic layer on the copper-barrier layer includes:
disposing a titanium layer on the copper-barrier layer; and
disposing a titanium nitride layer on the titanium layer (“For example, via barrier layer 142 includes a first sub-layer that includes titanium and a second sub-layer that includes titanium nitride”, [0033]).
Re claim 5, Tsai, FIG. 3F teaches the method of claim 3 wherein the semiconductor wafer is not exposed to air (by using ultra-high vacuum CVD process, [0022]) between the end of the disposing of the copper-barrier layer (142) and an end of the filling of the via opening with tungsten (132, [0032]).
Re claim 8, Tsai, FIG. 3F teaches the method of claim 1 further comprising: after the filling of the via opening with tungsten to form the tungsten via, performing chemical mechanical polishing (CMP) (FIG. 3E → 3F, [0040]) planarize a surface including a top surface of the tungsten via and a top surface of the dielectric layer.
Re claim 12, Tsai, FIG. 3G teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (54/46) disposed over a copper or copper alloy layer (132);
forming a via opening (122) in the dielectric layer exposing a portion of the copper or copper alloy layer;
disposing a copper-barrier layer (bottom layer 142) in the via opening which directly contacts the exposed portion of the copper or copper alloy layer (132), wherein the copper-barrier layer includes a tantalum layer, a tantalum nitride layer or a combination thereof (“via barrier layer 142 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy…..via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride)”, [0033]);
disposing an oxophilic layer including a titanium nitride layer, a titanium layer, or a combination thereof on the copper-barrier layer (upper layer of 142, note that via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride), said upper layer 142 is including titanium nitride this time) wherein the semiconductor wafer is not exposed to air (by using ultra-high vacuum CVD process, [0022]) during a time interval encompassing the deposition of the copper-barrier layer and the deposition of at least an initial portion of the oxophilic layer;
after disposing the oxophilic layer, filling the via opening with a metal (152) to form a metal via; and
forming an electronic device [0022] in electrical contact with the copper or copper alloy layer by way of the metal via.
Re claim 13, Tsai, FIG. 3G teaches the method of claim 12 wherein the filling the via opening with a metal comprises filling the via opening with tungsten to form the metal via as a tungsten via (152).
Re claim 14, Tsai, FIG. 3G teaches the method of claim 12 wherein the semiconductor wafer is not exposed to air (by using ultra-high vacuum CVD process, [0022]) during a time interval encompassing the deposition of the copper-barrier layer (bottom layer 142) and the deposition of entire the oxophilic layer (upper layer of 142).
Re claim 15, Tsai, FIG. 3G teaches the method of claim 12 wherein the semiconductor wafer is not exposed to air (by using ultra-high vacuum CVD process, [0022]) a time interval encompassing the deposition of the copper-barrier layer (bottom layer 142) and the deposition of the oxophilic layer (upper layer of 142) and the filling of the via opening (122) with the metal to form the metal via (152).
Re claim 21, Tsai, FIG. 3G teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (54/46) disposed over a copper or copper alloy layer (132/62);
forming a via opening (122) in the dielectric layer exposing a portion of the copper or copper alloy layer;
disposing a copper-barrier layer (bottom layer 142) in the via opening, which directly contacts the exposed portion of the copper or copper alloy layer (132/62);
disposing an oxophilic layer (upper layer of 142) including a titanium nitride layer, a titanium layer, or a combination thereof on the copper-barrier layer wherein the semiconductor wafer is not exposed to air during a time interval encompassing the deposition of the copper-barrier layer and the deposition of the oxophilic layer;
after disposing the oxophilic layer, filling the via opening with a metal to form a metal via (152); and
forming an electronic device [0022] in electrical contact with the copper or copper alloy layer by way of the metal via.
Re claim 22, Tsai, FIG. 3G teaches the integrated circuit fabrication method of claim 21, wherein the copper-barrier layer includes a tantalum layer and a tantalum nitride layer (bottom layer 142),
wherein the method further comprises exposing the semiconductor wafer to air after the end of disposing of the oxophilic layer (upper 132) and before filling the via opening (note that “Via bulk layer 152 is formed by a non-selective deposition process. For example, a blanket deposition process, such as CVD”, [0034] and CVD (Chemical Vapor Deposition) process wherein the chemical deposit in [Vapor= Gas = Air] formed).
Re claim 24, Tsai, FIG. 3G teaches the integrated circuit fabrication method of claim 21, wherein:
the disposing of the copper-barrier layer in the via opening includes disposing a tantalum layer, a tantalum nitride layer, or a combination thereof (bottom layer 142, note that “via barrier layer 142 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy…..via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride)”, [0033]); and
the disposing of the oxophilic layer includes disposing a titanium layer, a titanium nitride layer, or a combination thereof (upper layer of 142, note that via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride), said upper layer 142 is including titanium nitride this time) on the copper-barrier layer comprising the tantalum layer, the tantalum nitride layer, or the combination thereof (lower 142 layer.
Claim(s) 1-3, 5, 8, 11-15 and 21-22, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pub. No.: US 2021/0257293) in view of Peng (Patent No.: US 9466525).
Re claim 1, Lee teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (270) disposed over a copper or copper alloy layer (236/240, FIG. 2H, ¶ [0026]);
forming a via opening (280) in the dielectric layer exposing a portion of the copper or copper alloy layer (236/240);
disposing a copper-barrier layer (294A, FIG. 3, [0044]) in the via opening;
disposing an oxophilic layer (294B) on the copper-barrier layer;
after disposing the oxophilic layer (294B), filling the via opening with copper to form a copper via (296, [0034]); and
forming an electronic device (of FIG. 8) in electrical contact with the copper or copper alloy layer (236/240) by way of the copper via (296);
wherein the deposition of the copper-barrier layer (294A) and the deposition of at least an initial portion of the oxophilic layer (296B) are performed in a same deposition chamber.
Re claim 12, Lee teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (270) disposed over a copper or copper alloy layer (236, FIG. 2H, ¶ [0026]);
forming a via opening (280) in the dielectric layer exposing a portion of the copper or copper alloy layer (270);
disposing a copper-barrier layer in the via opening, wherein the copper-barrier layer includes a tantalum layer, a tantalum nitride layer or a combination thereof (294A, FIG. 3, [0044], note that “first barrier layer 294A, second barrier layer 294B, and copper bulk layer 296 are similar respectively to diffusion barrier layer 232, first barrier layer 234A, second barrier layer 234B” and “first barrier layer 234A includes tantalum, tantalum nitride, titanium, titanium nitride”, [0026]);
disposing an oxophilic layer (294B) including a titanium nitride layer, a titanium layer, or a combination thereof on the copper-barrier layer, wherein the semiconductor wafer is not exposed to air (note that the deposition is taking place in ultra-high vacuum CVD, [0051], note that “many CVD processes are performed in a vacuum chamber”) during a time interval encompassing the deposition of the copper-barrier layer and the deposition of at least an initial portion of the oxophilic layer;
after disposing the oxophilic layer, filling the via opening with a metal to form a metal via (296); and
forming an electronic device (of FIG. 8) in electrical contact with the copper or copper alloy layer by way of the metal via.
Re claim 21, Lee, FIG. 3 teaches an integrated circuit fabrication method comprising:
providing a semiconductor wafer including a dielectric layer (270) disposed over a copper or copper alloy layer;
forming a via opening (280) in the dielectric layer exposing a portion of the copper or copper alloy layer;
disposing a copper-barrier layer (294A) in the via opening;
disposing an oxophilic layer including a titanium nitride layer, a titanium layer, or a combination thereof on the copper-barrier layer wherein the semiconductor wafer is not exposed to air (ultra-high vacuum CVD) during a time interval encompassing the deposition of the copper-barrier layer (294A) and the deposition of the oxophilic layer (294B);
after disposing the oxophilic layer, filling the via opening with a metal to form a metal via (296); and
forming an electronic device (of FIG. 8) in electrical contact with the copper or copper alloy layer by way of the metal via;
wherein the method further comprises exposing the semiconductor wafer to air after the end of disposing of the oxophilic layer (294B) and before filling the via opening (296, note the 296 is deposit by CVD=Chemical [Vapor=Vapor=Air] Deposition).
In re claims 1, 12 and 21, Lee fails to teach disposing a copper-barrier layer in the via opening, which directly contacts the exposed portion of the tungsten via.
Peng teaches disposing a copper-barrier layer (34, FIG. 5 → 6, col. 4, lines 16-24) in the via opening, which directly contacts the exposed portion of the tungsten via (36, col. 4, lines 18-24).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of avoiding degradation in the performance of the resulting metal interconnect structures as taught by Peng, BACKGROUND.
Re claim 2, in the combination, Lee teaches the method of claim 1 wherein:
the disposing of the copper-barrier layer in the via opening includes disposing a tantalum layer, a tantalum nitride layer, or a combination thereof (294A, FIG. 3, [0026], note that “first barrier layer 294A, second barrier layer 294B, and copper bulk layer 296 are similar respectively to diffusion barrier layer 232, first barrier layer 234A, second barrier layer 234B, and copper bulk layer 296”, [0044] and “first barrier layer 234A includes tantalum, tantalum nitride, titanium, titanium nitride”, [0026]); and
the disposing of the oxophilic layer (294B, note that titanium is an element with a high affinity for oxygen, readily forming stable oxides or bonding with oxygen-containing molecules) includes disposing a titanium layer, a titanium nitride layer, or a combination thereof (294B/234B, note that “second barrier layer 234B includes tantalum, tantalum alloy, titanium, titanium alloy”, [0026]) on the copper-barrier layer comprising the tantalum layer, the tantalum nitride layer, or the combination thereof (294A/234A).
Re claim 3, in the combination, Lee, FIG. 3 teaches the method of claim 1 wherein the disposing of the copper-barrier layer and the disposing of the tantalum nitride layer are performed using a single deposition chamber which is a chemical vapor deposition (CVD) chamber, physical vapor deposition (PVD) chamber, or a combined PVD/CVD chamber (single CVD, [0025]), and the semiconductor wafer is not exposed to air between the end of the disposing of the copper-barrier layer and an end of the disposing of the oxophilic layer (294B is formed immediately right next to 294A).
Re claim 5, in the combination, Lee, FIG. 3 teaches the method of claim 3 wherein the semiconductor wafer is not exposed to air between the end of the disposing of the copper-barrier layer (294A) and an end of the filling of the via opening with tungsten (294B).
Re claim 8, in the combination, Peng, FIG. 7 teaches the method of claim 1 further comprising: after the filling of the via opening with tungsten to form the tungsten via, performing chemical mechanical polishing (CMP) planarize a surface including a top surface of the tungsten via and a top surface of the dielectric layer.
Re claim 11, in the combination, Lee teaches the method of claim 1 wherein the formed via opening has a maximum lateral dimension at its intersection with the copper or copper alloy layer of 50 nm or less (“Copper bulk layer 236 has a thickness t3, which, in some embodiments, is about 20 nm to about 40 nm”, FIG. 2C, [0027]) and a ratio of via opening height (“ILD layer 270 has a thickness t8 of about 60 nm to about 90 nm”, FIG. 2G, [0041]) to maximum lateral dimension at its intersection with the copper or copper alloy layer of 1.6 or larger.
Re claim 13, in the combination, Peng teaches the method of claim 12 wherein the filling the via opening with a metal comprises filling the via opening with tungsten to form the metal via as a tungsten via (36, FIG. 6, col. 4, lines 15-25).
Re claim 14, in the combination, Lee, FIG. 3 teaches the method of claim 12 wherein the semiconductor wafer is not exposed to air during a time interval (ultra-high vacuum CVD) encompassing the deposition of the copper-barrier layer (294A) and the deposition of entire the oxophilic layer (294B).
Re claim 15, in the combination, Lee, FIG. 3 teaches the method of claim 12 wherein the semiconductor wafer is not exposed to air a time (ultra-high vacuum CVD) interval encompassing the deposition of the copper-barrier layer (294A) and the deposition of the oxophilic layer (294B) and the filling of the via opening with the metal to form the metal via (296).
Re claim 22, in the combination, Lee, FIG. 3 teaches the integrated circuit fabrication method of claim 21, wherein the copper-barrier layer includes a tantalum layer and a tantalum nitride layer.
Re claim 24, in the combination, Lee, FIG. 3 teaches the integrated circuit fabrication method of claim 21, wherein:
the disposing of the copper-barrier layer in the via opening includes disposing a tantalum layer, a tantalum nitride layer, or a combination thereof (294A/234A, [0044]/[0026]); and
the disposing of the oxophilic layer includes disposing a titanium layer, a titanium nitride layer, or a combination thereof on the copper-barrier layer comprising the tantalum layer, the tantalum nitride layer, or the combination thereof (294B/234B, note that “second barrier layer 234B includes tantalum, tantalum alloy, titanium, titanium alloy”, [0026]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Tsai differs from the claim invention by not disclosing wherein the formed via opening has a maximum lateral dimension at its intersection with the copper or copper alloy layer of 50 nm or less and a ratio of via opening height to maximum lateral dimension at its intersection with the copper or copper alloy layer of 1.6 or larger.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Hsueh (Pub. No.: US 2021/0287994).
Re claim 9/17, Tsai teaches all the limitation of claim 1.
Tsai fails to teach the limitation of 9.
Hsueh teaches wherein the electronic device is a nonvolatile memory device (MRAM, FIG. 6, ¶ [0051]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing the RC delay within the integrated chip as taught by Hsueh, [0051]).
In re claim 17, Tsai differs from the claim invention by not disclosing the via opening has a maximum lateral dimension of 65 nm and a vertical/lateral aspect ratio of 1.6 or larger.
However, Applicant has not disclosed that the ranges are for particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to include the above said teaching, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."); In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969) (Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions.). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997).
Re claim 10, in the combination, Hsueh teaches the method of claim 9 wherein the nonvolatile memory device is a magnetoresistive random access memory (MRAM) (MRAM, FIG. 6, ¶ [0051]).
Response to Arguments
Applicant's arguments with respect to claims 1-5, 8-15, 17 and 21, 23 on the remarks filed on 05/04/2026 have been considered but are not persuasive because Tsai, FIG. 3G still reads on:
disposing a copper-barrier layer (bottom layer 142) in the via opening which directly contacts the exposed portion of the copper or copper alloy layer (132), wherein the copper-barrier layer includes a tantalum layer, a tantalum nitride layer or a combination thereof (“via barrier layer 142 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy…..via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride)”, [0033]);
disposing an oxophilic layer including a titanium nitride layer, a titanium layer, or a combination thereof on the copper-barrier layer (upper layer of 142, note that via barrier layer 142 includes tantalum and nitrogen (for example, tantalum nitride) or titanium and nitrogen (for example, titanium nitride), said upper layer 142 is including titanium nitride this time) wherein the semiconductor wafer is not exposed to air (by using ultra-high vacuum CVD process, [0022]) during a time interval encompassing the deposition of the copper-barrier layer and the deposition of at least an initial portion of the oxophilic layer.
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
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