DETAILED ACTION
This action is responsive to the amendment received October 24, 2025. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
The Japanese office action was not considered because and English translation was not provided.
Claim Objections
Claims 1-7, 9, and 16-20 are objected to because of the following informalities:
In claim 1, “comprising an insulating material comprises an organic material” should be changed to “comprising an organic insulating material”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneya (US 2015/0270324) in view of Nishimura et al. (US 2013/0153904), all of record.
(Re Claim 1) Yoneya teaches a thin-film transistor, comprising:
an insulating substrate (Fig. 1: 11, ¶43); a gate electrode (21); a first gate insulating layer comprising an insulating material comprises an organic material (22, ¶46); a second gate insulating layer comprising an inorganic insulating material (23, ¶47) the second gate insulating layer having a first edge and a second edge bounding an upper surface and a lower surface of the second gate insulating layer (as shown); a semiconductor layer (24, ¶48); an insulating protective layer (31); a source electrode (25A/B); and a drain electrode (25A/B), wherein the second gate insulating layer has a thickness that is smaller than a thickness of the first gate insulating layer (¶47), and wherein the second gate insulating layer is formed only in an area overlapping the semiconductor layer or the insulating protective layer (Fig. 1).
Yoneya is silent regarding wherein seen from a cross-sectional side view, the drain electrode and source electrode are spaced apart from the second gate insulating layer from the first edge to the second edge of the second gate insulating layer. This is because Yoena adopts a conventional process wherein the S/D electrodes are conformally blanket deposited directly on the channel and surrounding insulating layers. A PHOSITA desiring to make, use, and improve upon Yoneya’s TFT would be motivated to look top related art for potential modifications and improvements. Related art from Nishimura teaches a conventional TFT (Fig. 2) wherein the S/D electrodes are deposited conformally over and directly on the channel like Yoneya, and also teaches an improvement in a second embodiment (Fig. 6) wherein a protective layer 9 is deposited over the TFT layers prior to depositing the S/D electrodes (13as/ad). This protective etch stop layer protects the channel from damage when etching the S/D electrodes (¶105). A PHOSITA would find it obvious to incorporate Nishimura’s protective layer 9 in Yoneya’s TFT to protect the channel from damage when etching the S/D electrodes, and in doing so, when seen from a cross-sectional side view, the drain electrode and source electrode are then spaced apart from the second gate insulating layer, by protective layer 9, from the first edge to the second edge of the second gate insulating layer. Also note with this modification, protective layer 9 is another insulating protective layer (in addition to layer 31 noted above), and the S/D electrodes 25A/25B will then be deposited over layer 9 and into openings exposing the S/D regions of the semiconductor layer, similar to layers 13as/ad in Nishimura.
(Re Claim 2) wherein the semiconductor layer comprises silicon or an oxide of a metal selected from the group consisting of indium, gallium, zinc and tin (¶85).
(Re Claim 3) wherein the second gate insulating layer has a thickness in a range of from 2 - 100 nm (¶47).
(Re Claim 4) wherein the second gate insulating layer comprises silicon oxide (¶47).
(Re Claim 5) wherein the second gate insulating layer comprises silicon nitride (¶47).
(Re Claim 6) wherein the first gate insulating layer comprises an organic polymer material (¶46).
(Re Claim 7) wherein the insulating protective layer comprises an organic material comprising fluorine (¶49).
(Re Claim 16) wherein the first gate insulating layer (22) has a first edge and a second edge (Fig. 1) bounding an upper surface and a lower surface of the first gate insulating layer1, and wherein, seen from the cross-sectional side view, the drain electrode and source electrode are spaced apart from the first gate insulating layer, by the additional protective layer 9 as modified above, from the first edge to the second edge of the first gate insulating layer (Yoneya’s Fig. 1 with Nishimura’s layer 9 from Fig. 6).
(Re Claim 17) comprising, in this order, in a vertical direction seen from the cross-sectional side view (Fig. 1): the insulating substrate (11); the gate electrode (21); the first gate insulating layer (22): the second gate insulating layer (23); the semiconductor layer (24) and the insulating protective layer (protective layer 9 as modified), and the source and drain electrodes (25A/B deposited on layer 9 as discussed above).
(Re Claim 19) wherein the second gate insulating layer comprises an oxide of aluminum (¶47).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneya and Nishimura et al. as applied above, and further in view of Jinbo (US 2009/0289256) and Dairiki et al. (US 2009/0218576), all of record.
(Re Claim 9) A thin-film transistor array, comprising: a plurality of thin-film transistors of claim 1 (see claim 1 rejection above), plurality formed in the display, e.g. see Figs. 1-3 and ¶¶8-9,40-42.
Yoneya is silent regarding wherein second gate insulating layers and insulating protective layers are formed in respective regions in each of which wiring of gate electrodes intersects wiring of source electrodes since Yoneya does not show a cross section at this location. A PHOSITA would be motivated to look to related display art to teach how layers are arranged at other locations. Related art from Jinbo similarly teaches a bottom gate (104) TFT with first (105) and second (106) gate dielectrics and shows where the gate line crosses the source line (Fig. 3 at D-C), that the layers corresponding to the transistor at section A-B are similarly and simultaneously formed in section C-D (Figs. 4A-4E, 5A-5E, 7A-7D, 8A-D). Related art from Dairiki also shows where the gate line crosses the source line (Fig. 10 at C-D), the same stack of layers are formed when the transistor is formed (section A-B) and shows a protective layer (67 and/or 69) is also formed simultaneously in each region of the device (Fig. 11E). Simultaneously forming the same layers in each region according to Jinbo and Dairiki results in a more simplified and efficient process requiring fewer steps and thus saving time and cost than if the layers are individually and separately processed in each region. Thus, in view of the prior art a PHOSITA would find it obvious to simultaneously form the same layers in each region in Yoneya’s display.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoneya and Nishimura et al. as applied above, and further in view of Okazaki et al. (US 2015/0171116), all of record.
(Re Claim 18) wherein the second gate insulating layer comprises an oxide of a metal selected from the group consisting of tantalum, hafnium, and yttrium.
(Re Claim 20) wherein the second gate insulating layer comprises an oxide of zirconium.
Yoneya is silent regarding the high-k metal oxide dielectrics of claims 18 and 20. Yoneya does teach a high-k aluminum oxide dielectric layer (¶47), albeit one of the lower-k of all the high-k dielectrics conventionally used. A PHOSITA desiring to make, use, and improve upon Yoneya’s TFT would be motivated to look to related art to teach alternative dielectrics which may offer advantages. Related art from Okazaki teaches the gate insulator layer may be selected from silicon oxide or aluminum oxide (the same materials disclosed by Yoneya), and further teaches high-k metal oxides such as hafnium oxide, yttrium oxide, zirconium oxide film, and tantalum oxide are all suitable, art-recognized, alternatives. These are also higher-k dielectrics than Yoneya’s disclosed materials and can provide the same insulating properties for a considerably thinner layer, and therefore improved gate capacitance. In light of Okazaki, a PHOSITA would find it obvious to use alternative higher-k metal oxide gate dielectrics, e.g. HfO2, ZrO2, etc., for improved device performance.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
1 It is noted, the left and right “edges” of the first gate insulating layer 2 shown in Fig. 1A are not real and are simply due to the way the section A-B is depicted, noting lack of edges in Fig. 1B indicating the layers extend beyond the cross section, consistent with conventional active matrix display substrates. Regardless, the “edges” of 22 in Yoneya’s Fig. 1 section will be similarly applied.