Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-5, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Licausi (PGPub No. 20180294267) in further view of Sung (PGPub No. 20200027777) and Chang (US Patent No. 9583485).
Regarding claim 1, Licausi teaches a semiconductor structure, comprising: a substrate (Fig. 7 points to a semiconductor structure comprising a substrate 18.); a plurality of fins, formed on the substrate (Fig. 9 points to fin structures 36.); a plurality of isolation structures, formed on the substrate, each isolation structure being sandwiched between adjacent fins (Id. points to gap fill material 40 (isolation structures).); and a power rail, located within a first isolation structure of the plurality of isolation structures, a top surface of the power rail is lower than top surfaces of the plurality of fins, a bottom of the power rail is lower than bottoms of all of the plurality of fins, and the bottom of the power rail is lower than bottoms of all of the plurality of isolation structures (Figs. 9-11 and [0041-42] point to the formation of a trench 45 (a first isolation structure) which is then filled with a liner 46 and a metal fill material 48 to fabricate a buried power rail.), and the top surfaces of the remaining portions of the first isolation structure are higher than the top surface of the power rail (Figs. 9-11 point to the gap fill material 40 (isolation structures) and the metal fill material 48 (power rail)).
Licausi fails to teach wherein sidewalls of the power rail are surrounded by remaining portions of the first isolation structure, wherein the remaining portions are portions of the first isolation structure that remain after forming the power rail within the first isolation structure, and top surfaces of the remaining portions of the first isolation structure of the plurality of isolation structures are lower than top surfaces of other isolation structures of the plurality of isolation structures.
Sung teaches wherein sidewalls of the power rail are surrounded by remaining portions of the first isolation structure, wherein the remaining portions are portions of the first isolation structure that remain after forming the power rail within the first isolation structure (Figs. 1B and 2A-2F point to a semiconductor device comprising a buried power rail 145 formed within a portion of an isolation oxide layer 134 (first isolation structure).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Licausi and Sung, such that portions of the first isolation structure remain to surround the power rail in order to provide a liner that further insulates/isolates the power rail from any undue interference.
Licausi et al. still fails to teach top surfaces of the remaining portions of the first isolation structure of the plurality of isolation structures are lower than top surfaces of other isolation structures of the plurality of isolation structures.
Chang teaches top surfaces of the remaining portions of the first isolation structure of the plurality of isolation structures are lower than top surfaces of other isolation structures of the plurality of isolation structures (Fig. 5C point to a FinFET device structure comprising a first etched gate dielectric layer 134′a (first isolation structure) with a height H9 and a second etched gate dielectric layer 134′b (other isolation structures) with a greater height H10.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Chang, such that the top surface of the first isolation structure is positioned lower than the top surfaces of the other isolation structures in order to create space for future components which could interact with the power rail buried in the first isolation structure and/or improve communication with said power rail by lowering the level of isolation created by the first isolation structure.
Regarding claim 2, Licausi teaches a metal layer, formed on the power rail (Fig. 12 points to a capping material 52 (metal layer).).
Regarding claim 3, Licausi teaches wherein: the metal layer is made of a metal material including cobalt, tungsten, copper, ruthenium, platinum, or a combination thereof ([0043] points to the capping material 52 (metal layer) being any barrier material that will prevent electro-migration issues, e.g., Co or Ru, associated with the buried power rail.).
Regarding claim 4, Licausi teaches wherein: the bottom surface of the power rail is lower than a top surface of the substrate (Fig. 11 points to the buried power rail formed from the liner 46 and metal fill material 48.).
Regarding claim 5, Licausi teaches wherein: the power rail is made of a material including ruthenium, copper, graphene, or a combination thereof ([0041] points to using the metal fill material 48 to fabricate the buried power rail, which can be a high melting temperature metal, e.g., Ru, W, Co, Mo, to enable high thermal budget flow.).
Regarding claim 13, Licausi teaches wherein: each isolation structure sandwiched between adjacent fins is in direct physical contact with the adjacent fins (Fig. 9 points to the gap fill material 40 (isolation structure).).
Regarding claim 14, Licausi teaches wherein: the top surfaces of the plurality of fins are coplanar with top surfaces of other isolation structures of the plurality of isolation structures (Fig. 7 points to fin structures 36/38 and gap fill material 40 (isolation structures).).
Regarding claim 15, Licausi teaches wherein: the top surface of the power rail is formed without having any portion of the first isolation structure there-on (Fig. 11 points to metal fill material 48 (power rail) with a top surface exposed to recess 50.).
Claim(s) 6-7, 10-12, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Licausi et al. in further view of Lin (PGPub No. 20150060959).
Regarding claim 6, Lin teaches wherein: a mask layer is formed on the remaining portions of the first isolation structure and further on the top surfaces of the plurality of fins (Fig. 14 point to a FinFET comprising an etch stop layer 38 (mask layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that an etch stop/mask layer is formed on the top surfaces of the first isolation structure and the plurality of fins in order to provide an interface that adequately protects the underlying regions.
Regarding claim 7, Lin teaches wherein: the mask layer is made of a material including silicon nitride, aluminum nitride, silicon carbide, or a combination thereof (Claim 10 points to the etch stop layer (mask layer) comprising silicon nitride.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that the etch stop/mask layer comprises silicon nitride in order to provide an interface that adequately protects the underlying regions.
Regarding claim 10, Licausi in combination with Lin teaches wherein: an interface between the mask layer and the remaining portions of the first isolation structure is above the top surface of the power rail (Figs. 11 and [0042] of Licausi point to the buried power rail formed from the recessed liner 46 and metal fill material 48. Fig. 14 of Lin further points to the etch stop layer 38 (mask layer) positioned on the top surface of the STI region 30 (first isolation structure).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that etch stop/mask layer interfaces with the first isolation structure at a surface above the power rail in order to provide an interface without directly contacting the power rail.
Regarding claim 11, Lin teaches wherein: the mask layer further covers the top surfaces of other isolation structures of the plurality of isolation structures (Fig. 14 and [0031] point to the etch stop layer 38 deposited over both the active fins 22 (plurality of fins) and the STI region(s) 30 (plurality of isolation structures).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that an etch stop/mask layer is formed on the top surfaces of the plurality of isolation structures and the plurality of fins in order to provide an interface that adequately protects the underlying regions.
Regarding claim 12, Lin teaches wherein: the mask layer is in direct contact with the top surfaces of the plurality of fins and the top surfaces of the plurality of isolation structures (Fig. 14 and [0031] point to the etch stop layer 38 deposited over both the active fins 22 (plurality of fins) and the STI region(s) 30 (plurality of isolation structures).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that an etch stop/mask layer is directly formed on the top surfaces of the plurality of isolation structures and the plurality of fins in order to provide an interface that adequately protects the underlying regions.
Regarding claim 16, Licausi in combination with Lin teaches wherein: a total width of the remaining portions of the first isolation structure of the plurality of isolation structures along a direction parallel to the substrate is smaller than a width of any one of other isolation structures of the plurality of isolation structures along the direction parallel to the substrate (Fig. 1 of Lin points to a FinFET comprising STI regions 30 (plurality of isolation structures) arranged such that each region is the same shape/width. Figs. 9-11 and [0041-42] of Licausi further point to the formation of a trench 45 (a first isolation structure) which is then filled with a liner 46 and a metal fill material 48 to fabricate a buried power rail. In light of these references, it is considered obvious that the material 48 (power rail) of Licausi could be formed within one of the STI regions (first isolation structure) of Lin, which would require etching/removing said region, reducing its total width, in order for the power rail to fit in place.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that each structure of the plurality of isolation structures is given the same shape/width in order to simplify the fabrication process and/or provide the same level of isolation to each of the adjacent fins.
Regarding claim 17, Lin teaches wherein: a total width of the power rail and the remaining portions of the first isolation structure of the plurality of isolation structures along a direction parallel to the substrate is equal to a width of any one of other isolation structures of the plurality of isolation structures along the direction parallel to the substrate (Fig. 1 points to a FinFET comprising STI regions 30 (plurality of isolation structures) arranged such that each region is the same shape/width.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Licausi et al. and Lin, such that each structure of the plurality of isolation structures is given the same shape/width in order to simplify the fabrication process and/or provide the same level of isolation to each of the adjacent fins.
Response to Arguments
Applicant’s arguments, see Remarks, filed 06/03/2026, with respect to the rejection(s) of amended claim 1 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Licausi et al. in further view of Sung (PGPub No. 20200027777).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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