DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, the limitation “the center insulating layer” is unclear because as to how it is related to the “insulating layer” of claim 9. Specifically, as disclosed the center insulating layer appears to be a portion of the insulating layer, however as recited appears to require a separate element.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schuele et al. (20170133550; herein “Schuele”).
Regarding claim 1, Schuele discloses in Fig. 4A, 12B and related text a display device comprising
a substrate (1200);
a first assembly electrode (818, see [0065]) and a second assembly electrode (816, see [0065]) separated and disposed on the substrate;
an insulating layer (layer above 816/818; see also 1700/1706, Figs. 17F,H and [0108]) disposed on the first assembly electrode and the second assembly electrode;
an assembly barrier wall (1202) comprising an assembly hole and disposed on the insulating layer;
a plating layer (e.g. 812/814, see [0065]) electrically connected to the first assembly electrode and the second assembly electrode; and
a semiconductor light emitting device (300, see [0058]) disposed in the assembly hole and electrically connected to the first assembly electrode and the second assembly electrode by the plating layer;
wherein at least one portion of the plating layer is in contact (e.g. thermal or electrical contact) with a lateral side surface of the semiconductor light emitting device.
Regarding claim 2, Schuele further discloses wherein the insulating layer comprises a center insulating layer (e.g. at least the portion between 812 and 814) disposed on a bottom surface of the semiconductor light emitting device and an edge insulating layer (e.g. portion under 1202) disposed spaced apart from a peripheral area of the center insulating layer.
Regarding claim 3, Schuele further discloses wherein the center insulating layer comprises a recess of the insulating layer (e.g. the recess between 812 and 814 in a first example interpretation; the recess filled by 812 in a second interpretation) and a first thickness of the center insulating layer (e.g. thickness at portion between 812 and 814) is smaller than a second thickness of the edge insulating layer (e.g. thickness above 1404, see also Fig. 14B).
Regarding claim 4, Schuele further discloses wherein the plating layer comprises
a first plating layer (812) disposed between the semiconductor light emitting device and the center insulating layer;
a second plating layer (814) disposed between the lateral side surface of the semiconductor light emitting device and the first and second assembly electrodes; and
wherein the second plating layer is in contact (e.g. electrical or thermal contact) with the first plating layer.
Regarding claim 5, Schuele further discloses wherein the first plating layer (812) is disposed in the recess of the center insulating layer (in the second interpretation where the recess is interpreted as the recess filled by 812).
Regarding claim 6, Schuele further discloses
wherein one end of the second plating layer (814) is in contact (e.g. electrical or thermal contact) with at least one upper surface of each of the first and second assembly electrodes exposed by the center insulating layer and the edge insulating layer (see Fig. 12B and also Fig. 13C), and
wherein another end of the second plating layer is in contact with the first plating layer and is in contact with (e.g. electrical or thermal contact) the lateral side surface of the semiconductor light emitting device.
Regarding claim 7, Schuele further discloses
wherein the semiconductor light emitting device comprises a first conductivity type semiconductor layer (e.g. 402), an active layer (406) and a second conductivity type semiconductor layer (404) sequentially arranged (see [0060]), and
wherein the second conductivity type semiconductor layer comprises a protruding region in which a lateral side surface of the second conductivity type semiconductor layer extends laterally further than the first conductivity type semiconductor layer (see Fig. 4A); and
wherein the second plating layer is electrically connected to both the first assembly electrode and the second assembly electrode (see Fig. 12B).
Regarding claim 8, Schuele further discloses wherein the first plating layer (812) is also disposed below the protruding region (e.g. at a lower level, see Fig. 12B).
Regarding claim 9, Schuele discloses in Fig. 4A, 12B and related text a display device comprising
a substrate (1200);
a first assembly electrode (818, see [0065]) and a second assembly electrode (816, see [0065]) separated and disposed on the substrate;
an insulating layer (layer above 816/818; see also 1700/1706, Figs. 17F,H and [0108]) disposed on the first assembly electrode and the second assembly electrode;
an assembly barrier wall (1202) comprising an assembly hole and disposed on the insulating layer;
a plating layer (e.g. 812/814, see [0065]) electrically connected to the first assembly electrode and the second assembly electrode; and
a semiconductor light emitting device (300, see [0058]) disposed in the assembly hole and electrically connected to the first assembly electrode and the second assembly electrode by the plating layer,
wherein the semiconductor light emitting device comprises a first conductivity type semiconductor layer (e.g. 402), an active layer (406) and a second conductivity type semiconductor layer (404) sequentially arranged (see [0060]), and
wherein the second conductivity type semiconductor layer comprises a protruding region in which a side portion of the second conductivity type semiconductor layer extends laterally further than the first conductivity type semiconductor layer (see Fig. 4A);
wherein at least one portion of the plating layer is in contact (e.g. thermal or electrical contact) with a lateral side surface of the semiconductor light emitting device.
Note that the limitation “plating layer” claims recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Regarding claim 10, Schuele further discloses wherein the plating layer (812/814) comprises,
a first plating layer (e.g. 812) disposed between the semiconductor light emitting device and a center insulating layer (e.g. portion between 812 and 814), and
a second plating layer (e.g. 814) disposed between the lateral side surface of the semiconductor light emitting device and one of the first and second assembly electrodes;
wherein the second plating layer is in contact (e.g. electrical or thermal contact) with the first plating layer.
Regarding claim 11, Schuele further discloses
wherein the semiconductor light emitting device further comprises a passivation layer (408, see [0060]; see also Fig. 4A) on lateral surfaces of the first conductivity type semiconductor layer (402), the active layer (406) and the second conductivity type semiconductor layer (404), and
wherein an edge of the passivation layer ends at the protruding region (see Fig. 4A),
wherein the plating layer is electrically connected to both the first assembly electrode and the second assembly electrode (see Fig. 12B).
Regarding claim 12, Schuele discloses in Fig. 4A, 12B and related text a display device comprising
a substrate (1200);
a first assembly electrode (818, see [0065]) and a second assembly electrode (816, see [0065]) separated and disposed on the substrate;
an insulating layer (layer above 816/818; see also 1700/1706, Figs. 17F,H and [0108]) disposed on the first assembly electrode and the second assembly electrode, and including an insulation layer hole that exposes at least one of the first assembly electrode and the second assembly electrode;
an assembly barrier wall (1202) comprising an assembly hole and disposed on the insulating layer;
a conductive layer (e.g. 812/814, see [0065]) including a plating layer electrically connected to the first assembly electrode and the second assembly electrode; and
a semiconductor light emitting device (300, see [0058]) disposed in the assembly hole and electrically connected to the first assembly electrode and the second assembly electrode;
wherein at least one portion of the plating layer is in contact (e.g. thermal or electrical contact) with a lateral side surface of the semiconductor light emitting device.
Note that the limitation “plating layer” claims recites a process, however the claim is directed to a product. Therefore, this limitation is considered to be product by process limitations. "Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Regarding claim 13, Schuele further disclose wherein the plating layer (812/814) is configured to connect the semiconductor light emitting device to the first assembly electrode and the second assembly electrode.
Regarding claim 14, Schuele further discloses wherein the plating layer includes:
a first plating layer (812) interposed between the semiconductor light emitting device and the insulating layer; and
a second plating layer (814) in the insulation layer hole and connected to (e.g. at least electrically) the semiconductor light emitting device and the first and second assembly electrodes;
wherein the second plating layer is in contact (e.g electrical or thermal contact) with the first plating layer.
Regarding claim 15, Schuele further discloses
wherein the semiconductor light emitting device includes a first conductivity type semiconductor layer (e.g. 402), an active layer (406) and a second conductivity type semiconductor layer (404) stacked sequentially (see [0060]), and
wherein the second conductivity type semiconductor layer includes a protruding region that extends laterally further than the first conductivity type semiconductor layer (see Fig. 4A).
Regarding claim 16, Schuele further discloses wherein the second conductivity type semiconductor layer includes a step formed by the protruding region (see Fig. 4A).
Regarding claim 17, (Original) The display device according to claim 15, wherein the second plating layer covers a lateral surface of the protruding semiconductor layer of the second conductivity type semiconductor layer, and
Wherein the second plating layer is electrically connected to both the first assembly electrode and the second assembly electrode (see Fig. 12B).
Regarding claim 18, Schuele further discloses
wherein the semiconductor light emitting device further comprises a passivation layer (408, see [0060]; see also Fig. 4A) on lateral surfaces of the first conductivity type semiconductor layer (402), the active layer (406) and the second conductivity type semiconductor layer (404),
wherein an edge of the passivation layer ends at the protruding region (see Fig. 4A), and
wherein a surface of the protruding semiconductor layer, a surface of the second plating layer, and the edge of the passivation layer are aligned (e.g. in the interpretation where the plating layer further includes 308, see [0058]).
Regarding claim 20, Schuele further discloses wherein the insulating layer hole delineates the insulating layer into a center insulating layer (e.g. portion between 812 and 814) corresponding to the semiconductor light emitting device and an edge insulating layer (e.g. portion under 1202) corresponding to the assembly barrier wall.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakaino et al. (US 20200088920; herein “Sakaino”).
Regarding claim 19, Schuele further discloses a light- transmitting material (e.g. 2100, see [0123; see also between the assembly barrier wall and the semiconductor light emitting device, and extending to the surface of the protruding region, but does not explicitly disclose the material is a resin.
In the same field of endeavor, Sakaino teaches a light emitting device comprising a light-transmitting material which is a resin (see [0176]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Schuele by having the light-transmitting material be a resin, as taught by Sakaino, in order to employ a material with excellent formability, transparency, heat resistance, and the like to be used as the binder resin (see Sakaino [0176]).
Response to Arguments
Applicant's arguments filed 2/13/2026 have been fully considered but are moot in view of the new grounds of rejection presented above. Specifically, it is noted that, in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Therefore the claim limitation “contact” has been given its broadest reasonable interpretation and does not require direct physical contact.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 4/13/2026
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