Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 9-10, 21-22, 26, 29 and 30 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Volant (Pub. No.: US 8709936).
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Re claim 1, Volant, Fig. 6 teaches an interconnect structure, comprising:
a first metal via (92-2/94) having a bottom surface disposed on a uniform horizontal top surface of a first metal line (122) of a first metallization layer disposed in a dielectric layer (124 of 120), wherein the uniform horizontal top surface of the first metal line (122) is below a top surface of the dielectric layer, and wherein the first metal via (92-2/94) includes a first portion (bottom portion of 92-2/94) disposed in the dielectric layer (124 of 120) and a second portion (top portion of 92-2/94) extending above the dielectric layer;
a first liner layer (88) disposed on the dielectric layer and on sidewalls and a top surface of the first metal via (92-2/94) extending above the dielectric layer; and
a second metallization layer (82) comprising a first metal line disposed on the first liner layer (88) disposed on the dielectric layer (124 of 120) and on the sidewalls and the top surface of the first metal via (92-2/94) extending above the dielectric layer.
Re claim 2, Volant, Fig. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first portion [FP] extends from the first metal line of the first metallization layer (122) to a top surface of the dielectric layer (124 of 120) and the second portion [SP] extending extends above the top surface of the dielectric layer and within the first metal line of the second metallization layer (82).
Re claim 6, Volant, Fig. 6 teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a single layer (88).
Re claim 9, Volant, Fig. 6 teaches the interconnect structure according to claim 1, wherein the first liner layer (88) is disposed on sidewalls of the first metal via (92-2/94/96).
Re claim 10, Volant, Fig. 6 teaches the interconnect structure according to claim 1, further comprising:
a second metal via (82) disposed on a second metal line of (94) the first metallization layer;
a second liner layer (96) disposed on the dielectric layer (86) and the second metal via; and
a second metal line (94) of the second metallization layer disposed on the second liner layer.
Re claim 21, Volant, Fig. 6 teaches an integrated circuit comprising one or more interconnect structures, wherein at least one of the one or more interconnect structures comprises:
a first metal via (92-2/94) having a bottom surface disposed on a uniform horizontal top surface of a first metal line of a first metallization layer (122) disposed in a dielectric layer (124 of 120), wherein the uniform horizontal top surface of the first metal line (92-2/94) is below a top surface of the dielectric layer (124 of 120), and wherein the first metal via includes a first portion [FP] disposed in the dielectric layer and a second portion [SP] extending above the dielectric layer;
a first liner layer (88) disposed on the dielectric layer and on sidewalls and a top surface of the first metal via extending above the dielectric layer; and
a second metallization layer (82) comprising a first metal line disposed on the first liner layer (88) disposed on the dielectric layer and on the sidewalls and the top surface of the first metal via (92-2/94) extending above the dielectric layer.
Re claim 22, Volant, Fig. 6 teaches the integrated circuit according to claim 21, the first portion [FP] extends from the first metal line of the first metallization layer to a top surface of the dielectric layer (122) and the second portion [SP] extends above the top surface of the dielectric layer and within the first metal line (122) of the second metallization layer.
Re claim 26, Volant, Fig. 6 teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a single layer (88).
Re claim 29, Volant, Fig. 6 teaches the integrated circuit according to claim 21, wherein the first liner layer (88) is disposed on sidewalls of the first metal via (92-2/94/96).
Re claim 30, Volant, Fig. 6 teaches the interconnect structure according to claim 21, further comprising:
a second metal via (82) disposed on a second metal line of (94) the first metallization layer;
a second liner layer (96) disposed on the dielectric layer (86) and the second metal via; and
a second metal line (94) of the second metallization layer disposed on the second liner layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 21-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leobandung (Patent No.: US 10446490) in view of Clevenger (Patent No.: US 9837309) and further in view of Volant.
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Re claim 1, Leobandung, FIG. 4G teaches an interconnect structure, comprising:
a first metal via [FMV] disposed on a first metal line (402) of a first metallization layer disposed in a dielectric layer (200), wherein a portion of the first metal via extends above the dielectric layer;
a first liner layer (208+404) disposed on the dielectric layer (200) and on the sidewalls of the first metal via [SP] extending above the dielectric layer; and
a second metallization layer (406) comprising a first metal line (404) disposed on the first liner layer (208+404) disposed on the dielectric layer (200) and the top surface of the first metal via [FMV] extending above the dielectric layer;
wherein the first metal via [FMV] includes a first portion [FP] disposed in the dielectric layer (200) and a second portion [SP] extending above the dielectric layer
Leobandung fails to teach a first liner layer disposed on a top surface of the first metal via; and a second metallization layer disposed on the sidewalls of the first metal via.
Clevenger teaches a first liner layer (30/26, FIG. 4, col. 4, lines 40-50) disposed on a top surface of the first metal via (22); and a second metallization layer (18) disposed on the sidewalls of the first metal via (22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing electromigration of the via material as taught by Clevenger, BACKGROUND.
Moreover, Leobandung/Clevenger fails to teach a first metal via having a bottom surface disposed on a uniform horizontal top surface of a first metal line of a first metallization layer disposed in a dielectric layer, wherein the uniform horizontal top surface of the first metal line is below a top surface of the dielectric layer.
Volant teaches a first metal via (92-2/94) having a bottom surface disposed on a uniform horizontal top surface of a first metal line of a first metallization layer (122) disposed in a dielectric layer (124 of 120), wherein the uniform horizontal top surface of the first metal line (92-2/94) is below a top surface of the dielectric layer (124 of 120)
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the interconnect structure from shorting or leakage as taught by Volant, Background.
Re claim 2, Leobandung, FIG. 4G teaches the interconnect structure according to claim 1, wherein the first metal via comprises a first portion [FP] extending from the first metal line (402) of the first metallization layer to a top surface of the dielectric layer (200) and a second portion [SP] extending above the top surface of the dielectric layer and within the first metal line (404) of the second metallization layer.
Re claim 3, Leobandung, FIG. 4G teaches the interconnect structure according to claim 1, wherein the first metal via comprises a first conductive metal (material of 406) and the first metal line (404) of the second metallization layer comprises a second conductive metal.
Re claim 4, Leobandung, FIG. 4G teaches the interconnect structure according to claim 3, wherein the first conductive metal is the same as the second conductive metal (said tungsten material of 406 and 404, col. 6, lines 13-27).
Re claim 5 Leobandung, FIG. 4G teaches the interconnect structure according to claim 3, wherein the first conductive metal is different than the second conductive metal (said tungsten material of 406 and ruthenium material of 404, col. 6, lines 13-27).
Re claim 6, Leobandung, FIG. 4G teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a single layer (208).
Re claim 7, Leobandung, FIG. 4G teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a plurality of layers (208/404).
Re claim 8, Leobandung, FIG. 4G teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a plurality of layers each of a different conductive liner material (400/404).
Re claim 21, Leobandung, FIG. 4G teaches an integrated circuit comprising one or more interconnect structures, wherein at least one of the one or more interconnect structures comprises:
a first metal via [FMV] disposed on a first metal line (402) of a first metallization layer disposed in a dielectric layer (200), wherein a portion of the first metal via extends above the dielectric layer (200);
a first liner layer (208) disposed on the dielectric layer and on the sidewalls of the first metal via extending above the dielectric layer; and
a second metallization layer comprising a first metal line (404) disposed on the first liner layer disposed on the dielectric layer (200) and the top surface of the first metal via [FMV] extending above the dielectric layer.
Leobandung fails to teach a first liner layer disposed on a top surface of the first metal via; and a second metallization layer disposed on the sidewalls of the first metal via.
Clevenger teaches a first liner layer (30/26, FIG. 4, col. 4, lines 40-50) disposed on a top surface of the first metal via (22); and a second metallization layer (18) disposed on the sidewalls of the first metal via (22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing electromigration of the via material as taught by Clevenger, BACKGROUND.
Re claim 22, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first metal via [FMV] comprises a first portion [FP] extending from the first metal line of the first metallization layer to a top surface of the dielectric layer (200) and a second portion [SP] extending above the top surface of the dielectric layer and within the first metal line (404) of the second metallization layer.
Re claim 23, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first metal via comprises a first conductive metal (material of 406) and the first metal line (404) of the second metallization layer comprises a second conductive metal.
Re claim 24, Leobandung, FIG. 4G teaches the integrated circuit according to claim 23, wherein the first conductive metal is the same as the second conductive metal (said tungsten material of 406 and 404, col. 6, lines 13-27).
Re claim 25, Leobandung, FIG. 4G teaches the integrated circuit according to claim 23, wherein the first conductive metal is different than the second conductive metal (said tungsten material of 406 and ruthenium material of 404, col. 6, lines 13-27).
Re claim 26, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a single layer (208).
Re claim 27, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a plurality of layers (208/404).
Re claim 28, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a plurality of layers each of a different conductive liner material (400/404).
Re claim 29, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the first liner layer (208/404) is disposed on sidewalls of the first metal via [FMV].
Re claim 30, Leobandung, FIG. 4G teaches the integrated circuit according to claim 21, wherein the at least one of the one or more interconnect structures further comprises:
a second metal via (406) disposed on a second metal line (400/404) of the first metallization layer;
a second liner layer (208) disposed on the dielectric layer (200) and the second metal via; and
a second metal line (404) of the second metallization layer disposed on the second liner layer (400/404).
Claim(s) 1-10 and 21-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murray (Patent No.: US 10714379) filed in the IDS on 01/05/2023 in view of Clevenger and Volant.
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Re claim 1, Murray, FIG. 6 [as shown above] teaches an interconnect structure, comprising:
a first metal via ([FMV]/40) disposed on a first metal line (20) of a first metallization layer disposed in a dielectric layer (25); wherein a portion of the first metal via [FMV] extends above the dielectric layer (25);
a first liner layer (15b+30 or (15b/30/35) for claims 7-8) disposed on the dielectric layer and on the sidewalls of the first metal via [FMV] extending above the dielectric layer (25);
a second metallization layer (45/30/35) comprising a first metal line (20/30) disposed on the first liner layer (15b) disposed on the dielectric layer (25) and the top surface of the first metal via [FMV] extending above the dielectric layer;
wherein the first metal via [FMV] includes a first portion [FP] disposed in the dielectric layer (25) and a second portion [SP] extending above the dielectric layer
Murray fails to teach a first liner layer disposed on a top surface of the first metal via; and a second metallization layer disposed on the sidewalls of the first metal via.
Clevenger teaches a first liner layer (30/26, FIG. 4, col. 4, lines 40-50) disposed on a top surface of the first metal via (22); and a second metallization layer (18) disposed on the sidewalls of the first metal via (22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing electromigration of the via material as taught by Clevenger, BACKGROUND.
Moreover, Murray/Clevenger fails to teach a first metal via having a bottom surface disposed on a uniform horizontal top surface of a first metal line of a first metallization layer disposed in a dielectric layer, wherein the uniform horizontal top surface of the first metal line is below a top surface of the dielectric layer.
Volant teaches a first metal via (92-2/94) having a bottom surface disposed on a uniform horizontal top surface of a first metal line of a first metallization layer (122) disposed in a dielectric layer (124 of 120), wherein the uniform horizontal top surface of the first metal line (92-2/94) is below a top surface of the dielectric layer (124 of 120)
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing the interconnect structure from shorting or leakage as taught by Volant, Background.
Re claim 2, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first metal via comprises a first portion [FP] extending from the first metal line (20) of the first metallization layer to a top surface of the dielectric layer (25) and a second portion [SP] extending above the top surface of the dielectric layer (25) and within the first metal line of the second metallization layer (45).
Re claim 3, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first metal via [FMV] comprises a first conductive metal (20) and the first metal line (20/30) of the second metallization layer comprises a second conductive metal (30).
Re claim 4, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 3, wherein the first conductive metal (said Cu or Al material of 20, col. 4, lines 10-17) is the same as the second conductive metal (said copper or silver material of 45, col. 9, lines 1-17).
Re claim 5, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 3, wherein the first conductive metal [FMV] is different than the second conductive metal (30).
Re claim 6, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a single layer (15b).
Re claim 7, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first liner layer (15b/30/35) comprises a plurality of layers.
Re claim 8, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first liner layer comprises a plurality of layers each of a different conductive liner material (15b/30/35).
Re claim 9, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, wherein the first liner layer (15b) is disposed on sidewalls of the first metal via [FMV].
Re claim 10, Murray, FIG. 6 [as shown above] teaches the interconnect structure according to claim 1, further comprising:
a second metal via (45) disposed on a second metal line (30) of the first metallization layer;
a second liner layer (15a) disposed on the dielectric layer (25) and the second metal via (45); and
a second metal line (35) of the second metallization layer (45/30/35) disposed on the second liner layer (30).
Re claim 21, Murray, FIG. 6 [as shown above] teaches an integrated circuit comprising one or more interconnect structures, wherein at least one of the one or more interconnect structures comprises:
a first metal via [FMV] disposed on a first metal line (20/30) of a first metallization layer disposed in a dielectric layer (25), wherein a portion of the first metal via extends above the dielectric layer;
a first liner layer (15b+30 or (15b/30/35) for claims 27-28) disposed on the dielectric layer (25) and on the sidewalls the first metal via [FMV] extending above the dielectric layer (25); and
a second metallization layer (45/30/35) comprising a first metal line (30) disposed on the first liner layer (15b) disposed on the dielectric layer (25) and the top surface of the first metal via [FMV] extending above the dielectric layer.
Murray fails to teach a first liner layer disposed on a top surface of the first metal via; and a second metallization layer disposed on the sidewalls of the first metal via.
Clevenger teaches a first liner layer (30/26, FIG. 4, col. 4, lines 40-50) disposed on a top surface of the first metal via (22); and a second metallization layer (18) disposed on the sidewalls of the first metal via (22).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of preventing electromigration of the via material as taught by Clevenger, BACKGROUND.
Re claim 22, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first metal via [FMV] comprises a first portion [FP] extending from the first metal line of the first metallization layer to a top surface of the dielectric layer (25) and a second portion [SP] extending above the top surface of the dielectric layer and within the first metal line of the second metallization layer (45/30/35).
Re claim 23, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first metal via comprises a first conductive metal [FMV] and the first metal line (20/30) of the second metallization layer comprises a second conductive metal.
Re claim 24, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 23, wherein the first conductive metal (said copper or silver material of 45, col. 9, lines 1-17) is the same as the second conductive metal (said Cu or Al material of 20, col. 4, lines 10-17).
Re claim 25, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 23, wherein the first conductive metal [FMV] is different than the second conductive metal (30).
Re claim 26, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a single layer (15b).
Re claim 27, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a plurality of layers.
Re claim 28, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first liner layer comprises a plurality of layers each of a different conductive liner material (15b/30/35).
Re claim 29, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the first liner layer is disposed on sidewalls of the first metal via [FMV].
Re claim 30, Murray, FIG. 6 [as shown above] teaches the integrated circuit according to claim 21, wherein the at least one of the one or more interconnect structures further comprises:
a second metal via (45) disposed on a second metal line (20/30) of the first metallization layer;
a second liner layer (15b) disposed on the dielectric layer (25) and the second metal via [FMV]; and
a second metal line (20/30) of the second metallization layer disposed on the second liner layer.
Response to Arguments
Applicant's arguments with respect to claims 1-10 and 21-30 on the remarks filed on 05/13/2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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