DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application and IDS filed on 1/6/2023. Claims 1-18 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1-18 are objected to because of the following informalities:
As per claim 1, “the circuit based on the performance check file corresponding to each of the sequential logic elements,” (lines 6-7) should be moved from lines 6-7 to be inserted after “simulating” (line 7) for greater clarification.
As per claim 7, “the circuit based on the performance check file corresponding to each of the sequential logic elements,” (lines 8-9) should be moved from lines 8-9 to be inserted after “simulating” (line 7) for greater clarification.
As per claim 13, “the circuit based on the performance check file corresponding to each of the sequential logic elements” (line 6-7) should be moved from lines 8-9 to be inserted after “simulating” (line 5) for greater clarification.
As per claims 2-6,8-12,14-18, the claims are objected to for incorporating the above errors into the respective claims by claim dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nobutaka et al. (Japanese Patent Document No. JPH08221456A, published 8/30/1995).
As per claims 1,5, 7,11, 13, 17, Fig. 1 illustrates the event driven logic simulation, comprising:
In first timing verification process means 11:
a performance check file (5, i.e., file holding initial timing check reference values) is obtained corresponding to each of the sequential logic elements (i.e., each flip-flop FF which is considered sequential logic elements)
the circuit (i.e., which includes multiple flipflops) are simulated, based on the performance check file (5) corresponding to each flip-flop, the circuit is simulated using various simulation waveforms (i.e., test patterns 4 or waveform of the event—see paragraph [0020]) given to the clock input terminal and the data input terminal of each flip-flop, wherein the performance check file 5 is used to check whether the hold time and setup time (i.e., target characteristic parameters) of each trigger flipflop meets the preset conditions in the simulation process, and output the identification information of the hold time and setup time of the target trigger flipflop that does not meet the preset conditions in the simulation result (see paragraphs [0015]-[0016]);
wherein the electronic device comprising at least one processor and memory, non-transitory computer readable medium, storing instructions, to perform the operations are part of the computer-implemented method/system as described in paragraphs [0001], [0015], Fig. 1.
As per claims 2,8,14, before obtaining the performance check file (5), the netlist 2 which was previously generated corresponding to the circuit based on a design database of the circuit; from which each of the sequential logic elements were necessarily searched or identified to arrive at based target flipflops using some form of preset keyword as is known in the art; and configuring the performance check file corresponding to each of the sequential logic elements (i.e., delay time are input from the model library 3 to simulate the logic circuit to be simulated; characteristic extraction system obtained in advance the characteristic or performance data for these flipflops which are sequential logic elements) (see paragraphs [0015]-[0016]).
As per claims 3,9,15, after the simulation result is obtained (i.e., after the first timing verification processing means 11, in the second timing verification processing means 12—paragraph [0016]) the method further comprises: determining a smallest target characteristic parameter (i.e., obtaining exact setup time and hold time required, input file 6 which contains typical delay time, maximum/minimum value of the device delay variation time, tester skew time, etc.) corresponding to target sequential logic elements on a same path in the simulation result (i.e., from the first and a target simulation waveform corresponding to the smallest target characteristic parameter; and determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path (see paragraphs [0016], [0018]-[0020])
As per claims 4,6,10,12,16,18, the adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path (see paragraphs [0010]-[0011], i.e.., the tester skew time is [adjusted] taken into consideration at the stage of timing verification, wherein the stage could be the first, second or subsequent timing verification stages).
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 January 10, 2026