DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 14, 2025 has been entered.
Response to Arguments
Applicant's arguments filed December 14, 2025 have been fully considered but they are not persuasive. Applicant recites “…points out that, in Botka, the calibration board 116 needs to pass through the load board 112 to calibrate the connector plane 130. Therefore, it is absolutely impossible for the Botka to have a flat surface in the center of the load board 112, where the pull down/eject ring 150 is installed. On the contrary, the purpose of the present invention is to quickly replace the standard chip or the tested chip, and it must be able to be placed firmly on the load board. Therefore, it can be seen from paragraphs [0025], [0027], and [0028] of the specification, the word "place" is used to describe the relationship between the load board and the body, such as "place the load board 12 on the body 10" without any special locking fixture. Therefore, it is impossible for the present invention to place the load board in the hole.”
The examiner respectfully disagrees as can be seen on fig. 2 and fig. 5 of Botka that the circumference of the calibration board 116 is larger than the circumference of the load board 112 therefore the calibration broad 116 is placed on the load board 112. The load board 112 is placed between the test head 100 and fixture board 114. The test head 100 comprises a pull down/eject ring 150 having a plurality of slots 150A and not load board 112. The hole in the center of the load board 112 is not part of the board since the is nothing there, the rest of the surface is flat on which the fixture board 114 is placed.
The instant application paragraph [0024] discloses “…that the test area can have an irregular shape. In practice, as long person having ordinary skill in the art can distinguish an area from the upper surface l0a of the body that can accommodate or fit the load board 12, such area should belong to the scope of the test area 100 in this embodiment.”.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Botka US 5,539,305 A.
Regarding claim 1, Botka discloses a chip carrier (fig. 2, elm. 100, col. 4, ln. 4-6), for selectively carrying a chip under test (fig. 2, integrated circuit 128, col. 4, ln. 25-26) or a standard chip (fig. 3, verification standard 147, col. 4, ln. 25-26), comprising: a body (fig. 2, load board 112, col. 4, ln. 4-5) defining a test area (fig. 2, top surface of load board 112, col. 4, ln. 4-5); and a load board (fig. 3, calibration board 116, col. 4, ln. 15-18) detachably placed on the test area (see. fig. 2 and fig. 5); wherein the test area is located on an upper surface of the body (see fig. 2, elm. 100) and a first chip position (fig. 2, elm. 150, col. 4, ln. 60-62) is defined in the test area; wherein a second chip position (fig. 2, quadrant 148 of the substrate 132, col. 4, ln. 25-28) is defined in the load board, and the standard chip (verification standard 147) is disposed within the second chip position (quadrant of 148); wherein when the load board (116) is located in the test area (surface of load board 112), the load board covers (132) the first chip position (150), and the chip under test (128) is not disposed within the first chip position; wherein when the chip under test (128) is disposed within the first chip position (150), the load board (132) is not located in the test area, wherein the test area is a flat portion of the upper surface (see fig. 2, top surface of load board 112, col. 4, ln. 4-5).
Regarding claim 2, Botka discloses chip carrier according to claim 1, wherein the load board (fig. 3, calibration board 116, col. 4, ln. 15-18) defines a first surface (fig. 3, calibration standards 134 are mounted in respective regions of the substrate 132, col. 4, ln. 25-28) and a second surface (fig. 3, surface with pins 152, col. 4, ln. 61-63) opposite to the first surface the second chip position (fig. 3, respective regions of the substrate 132, for ex. three respective quadrants 142, 144, and 146 of the substrate 132, col. 4, ln. 25-28) is located on the first surface, and the second surface contacts the first chip position (150) when the load board (116) is located in the test area (surface of load board 112).
Regarding claim 6, Botka and XIAO discloses the chip carrier according to claim 3, Botka discloses wherein the first surface (fig. 3, calibration standards 134 are mounted in respective regions of the substrate 132, col. 4, ln. 25-28) is provided with a second electrode pad (fig. 3, quadrant 144 of the substrate 132, col. 4, ln. 25-28), the second electrode pad is located in the second chip position (fig. 3, quadrant 148 of the substrate 132, col. 4, ln. 25-28) and connected to a conductive block (fig. 3, elm. 149 pass through the substrate beyond the other surface of the substrate for interconnection with the connectors 126, col. 4, ln. 40-46), the conductive block is disposed within the load board (fig. 3, calibration board 116, col. 4, ln. 15-18) and exposed on the second surface (fig. 3, surface with pins 152, col. 4, ln. 61-63).
Regarding claim 8, Botka discloses the chip carrier according to claim 1, wherein the test area (fig. 2, top surface of load board 112, col. 4, ln. 4-5) is recessed into the upper surface, the load board (fig. 3, calibration board 116, col. 4, ln. 15-18) is placed in the test area, and the body (fig. 2, load board 112, col. 4, ln. 4-5) is made of conductive material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Botka as applied to claim 2 above, and further in view of XIAO CN 207990239 U.
Regarding claim 3, Botka discloses the chip carrier according to claim 2, wherein the first surface (fig. 3, calibration standards 134 are mounted in respective regions of the substrate 132, col. 4, ln. 25-28) is further provided with a first electrode pad (see fig. 3, fourth quadrant 148, col. 4, ln. 40-46).
Botka does not disclose the first electrode pad is connected to a protective conductor, the protective conductor shields the standard chip in a vertical direction, and the standard chip is a light emitting chip in side- emission configuration.
XIAO discloses the first electrode pad is connected to a protective conductor (fig. 1, aluminum substrate 4, Specific implementation methods) the protective conductor shields the standard chip (fig. 1, LED lamp bead 3, Specific implementation methods) in a vertical direction (see fig. 1), and the standard chip is a light emitting chip in side- emission configuration (the side light emitting LED light emitting module).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a low-power-consumption radiating side light emitting LED light emitting module, comprising a heat conducting layer guard plate, an outer protective plate, as taught in XIAO in modifying the apparatus of Botka. The motivation would be improved the heat dissipation area of the heat dissipation structure of the side emitting LED light emitting module so as to effectively control temperature of space with increased luminous efficiency.
Regarding claim 4, Botka and XIAO discloses the chip carrier according to claim 3, Botka discloses wherein a conductive block (fig. 3, blind mate connectors 149, col. 4, ln. 43-48) is disposed within the load board (fig. 3, calibration board 116, col. 4, ln. 15-18), the conductive block is exposed at the second chip position (quadrants of 132) on the first surface and the conductive block is exposed on the second surface (fig. 3, blind mate connectors 149 connect to the calibration standards 134 and at least one verification standard 147 mounted to one surface of the substrate 132 and pass through the substrate beyond the other surface of the substrate for interconnection, col. 4, ln. 43-48).
The references are combined for the same reason already applied in the rejection of claim 3.
Regarding claim 5, Botka and XIAO discloses the chip carrier according to claim 4, Botka discloses wherein the protective conductor (fig. 1, aluminum substrate 4, Specific implementation methods) is composed of a protective cantilever (fig. 1, aluminum substrate 4, Specific implementation methods) and an elastic block (fig. 1, heat conductive sheet, Specific implementation methods), the protective cantilever shields the standard chip (fig. 1, LED lamp bead 3, Specific implementation methods) in the vertical direction, the elastic block is located between the protective cantilever and the first surface (fig. 1, second outer plate 5-2, Specific implementation methods), and the elastic block absorbs stress (heat) applied to the protective cantilever.
The references are combined for the same reason already applied in the rejection of claim 3.
Regarding claim 7, Botka and XIAO discloses the chip carrier according to claim 3, Botka discloses wherein the first surface (fig. 3, calibration standards 134 are mounted in respective regions of the substrate 132, col. 4, ln. 25-28) is further provided with an extended electrode pad (fig. 3, quadrant 140 of the substrate 132, col. 4, ln. 25-28), and the protective conductor is electrically connected to the first electrode pad (see fig. 3, fourth quadrant 148, col. 4, ln. 40-46) and the extended electrode pad.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Botka as applied to claim 1 above, and further in view of Needham US 6,617,868 B1.
Regarding claim 9, Botka discloses the chip carrier according to claim 1, Botka does not disclose wherein the load board has a temperature control unit, and the temperature control unit is used to control an ambient temperature around the second chip position.
Needham disclose wherein the load board has a temperature control unit (fig. 1B, testing system 100, cooling system 114, description: par. [09]), and the temperature control unit is used to control an ambient temperature around the second chip position (fig. 1B, DUT 120, description: par. [10]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature control to the DUT, as taught in Needham in modifying the apparatus of Botka. The motivation would be to closely control the temperature of DUT near the specified minimum and maximum operating temperatures.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Botka as applied to claim 1 above, and further in view of Pierce US 2002/0075023 A1.
Regarding claim 10, Botka discloses the chip carrier according to claim 1, Botka does not disclose wherein the body is provided with an identification pattern, and the identification pattern is used to identify the chip carrier.
Pierce discloses wherein the body is provided with an identification pattern, and the identification pattern is used to identify the chip carrier (fig.1, elm. 23, par. [0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an identification of the load board as taught in Pierce in modifying the apparatus of Botka. The motivation would be to correlate test results of each device with a particular wafer-interposer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 1/28/2026