Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket number: 3748-0146PUS1
Filling Date: 1/10/23
Inventor: Lin et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (US 2018/0082994 A1) in view of Chuang et al (US 2012/0012973 A1).
Regarding claim 1, Han discloses an electrostatic discharge (ESD) protection device (Fig. 2, see annotated figure) comprising: an N-type semiconductor substrate 115; a P-type semiconductor layer 110 formed on the N-type semiconductor substrate 115; a first N-type well 150 (where emitter connected, middle), a P-type well 135 (where collector connected, left), and a second N-type well 150, 160 (where base connected, right) formed in the P-type semiconductor layer 110, wherein the second N-type well 150, 160 (right) directly touches the N-type semiconductor substrate 115; a first P-type heavily-doped area 130 formed in the first N-type well 150.
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Han does not explicitly disclose N-type substrate; a first N-type heavily-doped area and a second P-type heavily-doped area formed in the P-type well, wherein the second P-type heavily-doped area is coupled to the second N-type well through an external conductive wire; wherein the second P-type heavily-doped area is directly coupled to the external conductive wire.
However, Chuang discloses a first N-type heavily-doped area 36 (Fig. 3, see annotated figure) and a second P-type heavily-doped area 32 formed in the P-type well 38, wherein the second P-type heavily-doped area 32 is coupled (coupled through element 20, 24) to the second N-type well 30 through an external conductive wire (element GND); wherein the second P-type heavily-doped area 32 is directly coupled to the external conductive wire (element GND).
Chuang teaches the above modification is used to connect GND to two wells of the device (Fig. 3). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Han structure with Chuang wire as suggested above to connect GND to two wells of the device (Fig. 3).
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Regarding claim 2, Han further discloses the ESD protection device according to claim 1, wherein the second N-type well 150, 160 is an N-type heavily-doped well (claim does not specify the number of doping level).
Regarding claim 3, Chuang further discloses the ESD protection device according to claim 1, further comprising an N-type heavily-doped area 28 (Fig. 3) formed in the second N-type well 30.
Regarding claim 4, Chuang further discloses the ESD protection device according to claim 1, further comprising a second N-type heavily-doped area 62 (Fig. 6, paras. 20-32, see annotated figure below) formed in the first N-type well (left most one, see annotated figure).
Regarding claim 5, Chuang further discloses the ESD protection device according to claim 4, wherein the first N-type heavily-doped area 68 (Fig. 6), the first P-type heavily-doped area 66, and the second N-type heavily-doped area 62 are coupled (coupled through layers 46, 70) to a first pin (see annotated figure 6) and the N-type semiconductor substrate (see annotated figure 6) is coupled to a second pin (see annotated figure).
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Allowable Subject Matter
Claims 6-7 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 1/12/26 have been fully considered but they are not persuasive.
Applicants argue:
The amended part of claim 1 does not disclose the cited two references.
Examiner responds:
However, examiner respectfully disagrees about the above arguments. The cited two references disclose the amended part and other limitations of claim 1. See above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817