DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on December 17, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 11-13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over by Yoo et al. (US 2020/0212060, hereinafter Yoo) in view of Ichinose (US 2020/0357808).
Regarding claim 1, Yoo discloses for a semiconductor device comprising that
a source structure (base conduction layer 105, Fig. 2), because “the base conduction layer 105 may be electrically connected to a source line (not illustrated). In another embodiment, the base conduction layer 105 may be a source line” ([0034]), therefore, the base conduction layer 105 by Yoo can correspond to the source structure in the claimed invention;
gate electrodes (gate electrode layers 210a-210g, Fig. 2) spaced apart from each other, because the gate electrode layers from 210a to 210g by Yoo are spaced apart from each other by the interlayer insulating layers 110a-110g (Fig. 2) and stacked in a first direction (vertical direction), perpendicular to an upper surface of the source structure (upper surface of 105, Fig. 2); and
a channel structure (channel structure 320/charge storage structure 310, Fig. 3) extending through the gate electrodes (210a-210g, Fig. 2) in the first direction (vertical direction), and including a dielectric layer (charge barrier layer 311, Fig. 3), a charge storage layer (charge trap layer 312, Fig. 3), a tunneling layer (charge tunneling layer 313, Fig. 3), a channel layer (hole conduction layer 321 and/or electron conduction layer 322 of the channel structure 320, Fig. 3), and a buried semiconductor layer (channel core 140, Fig. 3),
wherein the dielectric layer (311, Fig. 3) is between the gate electrodes (210a-210g, Fig. 3) and the charge storage layer (312, Fig. 3),
wherein the tunneling layer (313, Fig. 3) is between charge storage layer (312, Fig. 3) and the channel layer (320, Fig. 3),
wherein the channel layer (321/322, Fig. 3) is between the tunneling layer (313, Fig. 3) and the buried semiconductor layer (140, Fig. 3),
wherein an outer surface of a lower portion of the channel layer (bottom surface of channel structure 320, Fig. 2) is in contact with the source structure (105, Fig. 2), because Applicants do not specifically claim where the lower portion of the channel layer is positioned, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, an arbitrary portion – i.e., a bottom portion – of the lower part of channel layers 321/322 by Yoo can be selected as the claimed lower portion of the channel layer, and
wherein the dielectric layer (311, Fig. 3) is continuous between the gate electrodes, because the charge barrier layer 311 by Yoo is vertically continuous between the gate electrodes 210a and 210g (see Fig. 2), and
the channel layer (321/322, Fig. 3) includes an oxide semiconductor material, because “the electron conduction layer 322 may include an oxide semiconductor material. As an example, the electron conduction layer 322 may include indium-gallium-zinc (In-Ga-Zn) oxide” (emphasis added, [0052]).
Yoo does not explicitly disclose that the dielectric layer includes a ferroelectric material and the buried semiconductor layer includes silicon (Si).
However, Ichinose discloses for the vertical memory device that the memory device (Fig. 4A) includes the oxide-film core 101, the semiconductor columnar portion 102, tunnel insulating film 103, the charge storage layer 104 and the block insulating layer 105 (Fig. 4A), which correspond to the buried semiconductor layer, channel layer, tunneling layer, charge storage layer and dielectric layer in the claimed invention, respectively; and Ichinose further discloses that the blocking insulating layer 105 is vertically continuous between the conducting layers 22 (Fig. 2, control gate or word line WL, [0029]), which correspond to the gate electrode in the claimed invention, and “the blocking insulating layer 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx)” (emphasis added, [0038]); since Applicants originally disclosed that “The ferroelectric material and the antiferroelectric material may include at least one of, for example, hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), titanium (Ti), and oxides thereof. For example, the ferroelectric material and the antiferroelectric material may include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium zirconium oxide (HZO), but are not limited thereto” ([0040] of present application), the blocking insulating layer 105 by Ichinose can be made of the same ferroelectric material of the claimed dielectric layer 142, for example, hafnium oxide (HfO2) or zirconium oxide (ZrO2) ([0038]); and the oxide-film core 101 by Ichinose, which corresponds to the buried semiconductor layer in the claimed invention, “is formed of, for example, a silicon oxide film (SiO2)” ([0036]), therefore, the oxide-film core includes silicon (Si).
Since both Yoo and Ichinose teach a vertical memory device structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a dielectric layer of charge storage structure can be selected from a ferroelectric material and a core semiconductor can include silicon (Si), as disclosed by Ichinose, in order to improve and optimize the semiconductor memory device performance.
Regarding claim 2, Yoo further discloses that the channel structure (320/310, Fig. 3) further includes a channel pad (bit line 150, Fig. 3) in an upper portion of the channel structure (upper portion of 320, Fig. 3) and in contact with the channel layer (Fig. 3).
Regarding claim 4, Ichinose further discloses that the channel layer (102, Fig. 4A) includes a material different from a material of the buried semiconductor layer (101, Fig. 4A), because “the semiconductor columnar portion 102 is formed of, for example, silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), germanium (Ge), or carbon (C)” ([0036]) and “the oxide-film core 101 is formed of, for example, a silicon oxide film (SiO2)” ([0036]), therefore, the semiconductor columnar portion 102 includes a material different from a material of the oxide-film core 101, and
wherein the buried semiconductor layer (101, Fig. 4A) is disposed in a channel hole to fill an inner space of the channel layer (102, Fig. 4A), because the semiconductor columnar portion 102 has a cylindrical shape (Fig. 4A) and the oxide-film core is formed inside of the semiconductor columnar portion 102 (Fig. 4A).
Regarding claim 5, Yoo further discloses that the channel layer includes zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), Zinc Oxynitride (ZnON), Magnesium Zinc Oxide (MgZnO), Zirconium Indium Zinc Oxide (ZrInZnO), Hafnium Indium Zinc Oxide (HffnZnO), Tin Indium Zinc Oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), or zirconium zinc tin oxide (ZrZnSnO), because “the electron conduction layer 322 may include an oxide semiconductor material. As an example, the electron conduction layer 322 may include indium-gallium-zinc (In-Ga-Zn) oxide” (emphasis added, [0052]).
Regarding claim 6, Ichinose further discloses that the dielectric layer (blocking insulating layer 105, Fig. 4A of Ichinose) includes hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), or titanium (Ti), or an oxide thereof, because “the blocking insulating layer 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx)” ([0038]), therefore, the blocking insulating layer 105 by Ichinose includes an element listed in claim 6.
Regarding claim 11, Yoo in view of Ichinose further discloses that the channel structure (channel structure 320/charge storage structure 310, Fig. 3 of Yoo) is configured to have an erase voltage applied thereto through the source structure (base conduction layer 105, Fig. 2), and wherein, after the erase voltage reaches a target voltage level during an erase operation, the channel structure is configured to have a step voltage applied thereto through the source structure such that the erase voltage has a voltage higher than the target voltage level, because the claimed limitation is directed to an intended use or field of use of a semiconductor memory device, as it describes an operational sequence, i.e., how the device is operated, rather than a structural property.
Regarding claim 12, Yoo in view of Ichinose further discloses that the step voltage corresponds to a voltage caused by ferroelectric polarization by the dielectric layer, because it is obvious to one of ordinary skill in the art that the blocking insulating film 153 by Kim (Fig. 1), which corresponds to the dielectric layer in the claimed invention, includes a ferroelectric material, and in this case, it would naturally cause such polarization.
Regarding claim 13, Yoo in view of Ichinose further discloses that an erase verify operation is performed after the erase voltage reaches the target voltage level and is not performed after the step voltage is applied, because the claimed limitation is directed to an intended use or field of use of a semiconductor memory device, as it describes an operational sequence, i.e., how the device is operated, rather than a structural property.
Regarding claim 15, Yoo further discloses for a semiconductor device comprising that
a source structure (base conduction layer 105, Fig. 2) including a conductive plate layer (source line, [0034]) and a source layer (105, Fig. 2) including a semiconductor material on the conductive plate layer, because “the base conduction layer 105 may, for example, include doped semiconductor, metal, conductive metal nitride or conductive metal silicide. In an example, the base conduction layer 105 may include n-type doped silicon” ([0034]) and “the base conduction layer 105 may be electrically connected to a source line (not illustrated)” ([0034]), therefore, the source line can correspond to the conductive plate layer in the claimed invention;
gate electrodes (gate electrode layers 210a-210g, Fig. 2) spaced apart from each other and stacked in a first direction, because the gate electrode layers from 210a to 210g by Yoo are spaced apart from each other by the interlayer insulating layers 110a-110g (Fig. 2) and stacked in a first direction (vertical direction), perpendicular to an upper surface of the source structure (upper surface of 105, Fig. 2); and
a channel structure (channel structure 320/charge storage structure 310, Fig. 3) extending through the gate electrodes (210a-210g, Fig. 2) in the first direction (vertical direction), and including a dielectric layer (charge barrier layer 311, Fig. 3), a charge storage layer (charge trap layer 312, Fig. 3), a tunneling layer (charge tunneling layer 313, Fig. 3), a channel layer (hole conduction layer 321 and/or electron conduction layer 322 of the channel structure 320, Fig. 3), and a buried semiconductor layer (channel core 140, Fig. 3),
wherein the dielectric layer (311, Fig. 3) is between the gate electrodes (210a-210g, Fig. 3) and the charge storage layer (312, Fig. 3),
wherein the tunneling layer (313, Fig. 3) is between charge storage layer (312, Fig. 3) and the channel layer (321/322, Fig. 3),
wherein the channel layer (321/322, Fig. 3) is between the tunneling layer (313, Fig. 3) and the buried semiconductor layer (140, Fig. 3),
wherein the channel structure (321/322, Fig. 3) has a contact region (region of bottom surface of 320, Fig. 2) in which the dielectric layer, the charge storage layer, and the tunneling layer are absent in a lower portion of the channel structure (bottom portion of the channel structure 320, Fig. 2), because Applicants do not specifically claim where the lower portion of the channel structure is positioned, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, therefore, an arbitrary portion – i.e., bottom portion – of the lower part of channel structure 320 by Yoo can be selected as the claimed lower portion of the channel structure, and in this case, a bottom surface of the channel structure 320 does not include the charge barrier layer 311, charge trap layer 312 and charge tunneling layer 313 (Fig. 2), and
an outer surface of the channel layer (bottom surface of 321/322, Fig. 3) is in contact with the source layer (105, Fig. 2) in the contact region (region of bottom surface of 321/322, Fig. 2),
wherein the channel layer (321/322, Fig. 3) includes an oxide semiconductor material, because “the electron conduction layer 322 may include an oxide semiconductor material. As an example, the electron conduction layer 322 may include indium-gallium-zinc (In-Ga-Zn) oxide” (emphasis added, [0052]), and
wherein the dielectric layer is continuous between the gate electrodes, because the charge barrier layer 311 by Yoo is vertically continuous between the gate electrodes 210a and 210g (see Fig. 2).
Yoo does not explicitly disclose that the dielectric layer includes a ferroelectric material.
However, Ichinose discloses that the memory device (Fig. 4A) includes the oxide-film core 101, the semiconductor columnar portion 102, tunnel insulating film 103, the charge storage layer 104 and the block insulating layer 105 (Fig. 4A), which correspond to the buried semiconductor layer, channel layer, tunneling layer, charge storage layer and dielectric layer in the claimed invention, respectively; and Ichinose further discloses that the blocking insulating layer 105 is vertically continuous between the conducting layers 22 (Fig. 2, control gate or word line WL, [0029]), which correspond to the gate electrode in the claimed invention, and “the blocking insulating layer 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx)” (emphasis added, [0038]); since Applicants originally disclosed that “The ferroelectric material and the antiferroelectric material may include at least one of, for example, hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), titanium (Ti), and oxides thereof. For example, the ferroelectric material and the antiferroelectric material may include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium zirconium oxide (HZO), but are not limited thereto” ([0040] of present application), the blocking insulating layer 105 by Ichinose can be made of the same ferroelectric material of the claimed dielectric layer 142, for example, hafnium oxide (HfO2) or zirconium oxide (ZrO2) ([0038]), therefore, it includes ferroelectric material, as claimed, and one of ordinary skill in the art would readily recognize that the charge barrier layer 311 in Yoo can be modified to the ferroelectric material taught by Ichinose.
Since both Yoo and Ichinose teach a vertical memory device structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a dielectric layer of charge storage structure can be selected from a ferroelectric material, as disclosed by Ichinose, in order to improve and optimize the semiconductor memory device performance.
Regarding claim 16, claim 16 is rejected for the same reasons discussed in claim 11 above.
Regarding claim 17, Ichinose further discloses that the dielectric layer (105, Fig. 4A) includes a ferroelectric material or an anti-ferroelectric material, because “the blocking insulating layer 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx)” (emphasis added, [0038]); since Applicants originally disclosed that “The ferroelectric material and the antiferroelectric material may include at least one of, for example, hafnium (Hf), zirconium (Zr), silicon (Si), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), titanium (Ti), and oxides thereof. For example, the ferroelectric material and the antiferroelectric material may include at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and hafnium zirconium oxide (HZO), but are not limited thereto” ([0040] of present application), the blocking insulating layer 105 by Ichinose can be made of the same ferroelectric material of the claimed dielectric layer 142, for example, hafnium oxide (HfO2) or zirconium oxide (ZrO2) ([0038]), therefore, it includes ferroelectric material, as claimed.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2020/0212060, hereinafter Yoo) in view of Ichinose (US 2020/0357808) as applied to claim 1 above, and further in view of Hwang (US 2018/0006052). The teachings of Yoo in view of Ichinose are discussed above.
Regarding claim 3, Yoo further discloses that in the channel structure (320/310, Fig. 3), the dielectric layer (311, Fig. 3), the charge storage layer (312, Fig. 3), the tunneling layer (313, Fig. 3), and the channel layer (321/322, Fig. 3) extend to an upper end of the channel structure (Fig. 3).
Yoo in view of Ichinose differs from the claimed invention by not showing that the channel layer is between the channel pad and the tunneling layer in the upper portion of the channel structure.
However, Hwang discloses for a three-dimensional semiconductor memory device that the memory device includes the channel layers CH (Fig. 1) and the multi-layered pattern ML1 including tunnel insulating pattern TI, data storage pattern DS and blocking insulating pattern BI (Fig. 1); the highly-doped capping layer CAP (Fig. 1) is formed in an upper portion of the channel layer CH and multi-layered pattern ML1, therefore, the capping layer CAP by Hwang can correspond to the channel pad in the claimed invention, and the channel layer CH is formed between the capping layer CAP and the tunnel insulating pattern TI (Fig. 1) in the upper postion of the channel layer CH.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a conductive feature can be formed in an upper portion of the channel structure of a vertical memory device and it can be positioned directly above a core layer of the channel structure, as disclosed by Hwang, in order to improve and optimize the performance of a vertical 3D memory device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2020/0212060, hereinafter Yoo) in view of Ichinose (US 2020/0357808) as applied to claim 1 above, and further in view of Kim et al. (US 2020/0328229, hereinafter Kim). The teachings of Yoo in view of Ichinose are discussed above.
Regarding claim 7, Yoo in view of Ichinose differs from the claimed invention by not showing that the buried semiconductor layer includes polycrystalline silicon.
However, Kim discloses for a vertical memory device that the memory device includes the channel layers 130 and the charge storage elements 150 (Fig. 1) formed through the vertically stacked gates 160 (Fig. 1), and the blocking insulating film 153 (dielectric layer in the claimed invention) is formed between the gate 160 and the charge trap film 152 (charge storage layer in the claimed invention); the tunnel oxide film 151 (tunneling layer in the claimed invention) is formed between the charge trap film 152 and the channel layer 132/133 (Charge layer in the claimed invention); the channel layer 132/133 is formed between the tunnel oxide film 151 and the undoped channel area 131 (buried semiconductor layer in the claimed invention) (Fig. 1); Kim further discloses that the undoped channel area 131 includes polysilicon ([0150]), and one of ordinary skill in the art would acknowledge that the channel core 140 of Yoo may be formed with polysilicon used by Kim.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a core layer of vertical memory device can be made of polycrystalline silicon, as disclosed by Kim, in order to improve and optimize the performance of a vertical 3D memory device.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2020/0212060, hereinafter Yoo) in view of Ichinose (US 2020/0357808) as applied to claim 1 and 15 above, and further in view of Ozawa (US 2010/0140684). The teachings of Yoo in view of Ichinose are discussed above.
Regarding claim 18, Yoo in view of Ichinose does not explicitly disclose that an entire outer surface of the buried semiconductor layer is surrounded by the channel layer.
However, Ozawa discloses for a nonvolatile semiconductor memory device that the vertical memory device (Fig. 16A) includes the channel silicon crystal film 30 (channel layer in the claimed invention), alumina film 16 to serve as a charge block film (dielectric layer in the claimed invention), silicon nitride film 17 to serve as a charge storage film (charge storage layer in the claimed invention), silicon oxide film 18 to serve as a tunnel insulating film (tunneling layer in the claimed invention), and the polycrystalline silicon 32 at a core (Fig. 16A), which corresponds to the buried semiconductor layer in the claimed invention; and the channel silicon crystal film 30 by Ozawa surrounds an entire outer surface of the polycrystalline silicon 32 (Fig. 16A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a core layer can be made of polycrystalline silicon and an entire outer surface can be surrounded by a channel layer, as disclosed by Ozawa, in order to improve and optimize the performance of a vertical 3D memory device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815