DETAILED ACTION
This Office Action is in response to the applicant's amendment filed December 5th, 2025. In virtue of this communication, claims 1-15 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, and 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “a first end portion” at line 2. Is unclear whether this is meant to refer back to the “a first end portion” at line 14 of claim 1 or to set forth another and different first end portion. For the purposes of examination this limitation is understood to be --the first end portion--. Claim 7 is also rejected as it depends from claim 6 and does not clear up the uncertainty of claim 6.
Claim 15 recites the limitations "the first distance” and “the second distance." There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, claim 15 is understood to depend from claim 11.
Claim Objections
Claim 4 is objected to because of the following informalities: change “the sider recess portion” to --the side recess portion--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5-7, 9, 10, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (US 2004/0113248 A1; hereinafter Ito).
With respect to claim 1, Ito teaches a semiconductor device in at least Figs. 1-4, comprising:
a semiconductor element 2 (see Figs. 1 and 2 and paragraphs 68, 70);
a base 5 having a first surface 5a on which the semiconductor element 2 is mounted and a second surface 5b opposite to the first surface 5a (see Figs. 1 and 2 and paragraphs 60, 68, 69, 74, 93-95);
a first edge portion (right edge of 5 in Fig. 2) that includes a stepped recess 5c recessed from the first surface 5a toward the second surface 5b in a first region of a peripheral edge of the base 5 and a non-recessed region (5a at right edge) (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115);
a first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) that is arranged at a position facing the first edge portion (right edge of 5 in Fig. 2) when viewed from a thickness direction of the base 5 (see Figs. 1 and 2 and paragraphs 60-63, 88, 93);
a conductive member 4 for electrically connecting the semiconductor element 2 and the first terminal (comprising 1a, 1b, 1d on right side in Fig. 2) to each other (see Figs. 1 and 2 and paragraphs 60, 70); and
a resin material 3 for sealing a part of the base 5, the semiconductor element 2, and a part 1a of the first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) (see Figs. 1 and 2 and paragraphs 60, 69, 70, 75, 88);
wherein a first end portion (where 4 contacts 1a on right in Fig. 2) of the first terminal (comprising 1a, 1b, 1d on right side in Fig. 2) that is connected to the semiconductor element 2 is positioned to overlap the stepped recess 5c in an overlap region when viewed from the thickness direction, and, in the overlap region, a distance L1 along the thickness direction between the first end portion (where 4 contacts 1a on right in Fig. 2) and a surface of the stepped recess 5c is greater than a distance L2 between the first end portion (where 4 contacts 1a on right in Fig. 2) and the first surface 5a in the non-recessed region (5a at right edge) of the first edge portion (right edge of 5 in Fig. 2) (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115; also see Fig. 2 annotated below showing distance L1 is greater than distance L2).
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With respect to claim 2, Ito teaches the semiconductor device according to claim 1, further comprising: a second edge portion (left edge of 5 in Fig. 2) having a stepped recess 5c that is recessed from the first surface 5a toward the second surface 5b in a second region facing the first region of the peripheral edge of the base 5 (see Figs. 1, 2, 7-9, and paragraphs 93, 94, 96, 114, 115); and a second terminal (comprising 1a, 1b, 1d at left side in Fig. 2) that is arranged at a position facing the second edge portion (left edge of 5 in Fig. 2) when viewed from the thickness direction of the base 5 (see Figs. 1 and 2 and paragraphs 60-63, 88, 93), and is electrically connected to the semiconductor element 2 by the conductive member 4 (see Figs. 1 and 2 and paragraphs 60, 70).
With respect to claim 5, Ito teaches the semiconductor device according to claim 1, further comprising: a matching circuit 7 mounted on the first surface 5a of the base 5 and electrically connected to the semiconductor element 2 and the first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) (see Figs. 1, 2, 18, and paragraphs 68, 70, 71, 86, 87).
With respect to claim 6, Ito teaches the semiconductor device according to claim 1, wherein the first terminal (comprising 1a, 1b, 1d on right in Fig. 2) has the first end portion (where 4 contacts 1a on right in Fig. 2) connected to the semiconductor element 2 and a second end portion 1b facing the first end portion (where 4 contacts 1a on right in Fig. 2), the first end portion (where 4 contacts 1a on right in Fig. 2) is arranged at a position facing the first edge portion (right edge of 5 in Fig. 2) when viewed from the thickness direction of the base 5, and the second end portion 1b is arranged at a position not facing the first edge portion (right edge of 5 in Fig. 2) when viewed from the thickness direction of the base 5 (see Figs. 1 and 2 and paragraphs 60-63, 70, 88, 93; 1b faces 1a in at least as much as 23b faces 23a in Fig. 2 of instant application).
With respect to claim 7, Ito teaches the semiconductor device according to claim 6, wherein the second surface 5b is exposed on a front surface (bottom surface of 6) of a package 6 covered with the resin material 3, the first end portion 1a is arranged inside the resin material 3, the second end portion 1b is exposed on a front surface (bottom surface of 6) of the package 6, and the first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) is arranged so as to be bent 1d in a region between the first end portion 1a and the second end portion 1b (see Figs. 1, 2, 4, and paragraphs 60, 63, 65, 69, 70, 75, 81, 88; bottom of 5b and 1b face same direction).
With respect to claim 9, Ito teaches the semiconductor device according to claim 1, wherein the first terminal (comprising 1a, 1b, 1d on right in Fig. 2) has the first end portion (where 4 contacts 1a on right in Fig. 2) and a second end portion 1b that is exposed at a front surface (bottom surface of 6) of a package 6 covered with the resin material 3, the first end portion (where 4 contacts 1a on right in Fig. 2) being disposed inside the resin material 3 and the first terminal (comprising 1a, 1b, 1d on right in Fig. 2) being bent 1d between the first end portion (where 4 contacts 1a on right in Fig. 2) and the second end portion 1b (see Figs. 1, 2, 4, and paragraphs 60-63, 65, 69, 70, 75, 81, 88, 93; bottom of 5b and 1b face same direction).
With respect to claim 10, Ito teaches the semiconductor device according to claim 9, wherein the second surface 5b of the base 5 is exposed at the front surface (bottom surface of 6) of the package 6 (see Figs. 1, 2, 4, and paragraphs 60, 69, 75, 88).
With respect to claim 14, Ito teaches the device according to claim 2, wherein, in a region where the second terminal (comprising 1a, 1d, 1b at left in Fig. 2) overlaps the second edge portion (left edge of 5 in Fig. 2) when viewed from the thickness direction, a distance along the thickness direction between the second terminal (comprising 1a, 1d, 1b at left in Fig. 2) and a surface of a stepped recess 5c at the second edge portion (left edge of 5 in Fig. 2) is greater than a distance between the second terminal (comprising 1a, 1d, 1b at left in Fig. 2) and the first surface 5a at a non-recessed region (5a at left edge) of the second edge portion (left edge of 4 in Fig. 2) (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115; also see Fig. 2 annotated above showing distance L1 is larger than distance L2; the structural configuration and spacing on the right side in the annotated figure applies equally to the left side).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (US 2004/0113248 A1; hereinafter Ito) in view of Danno et al. (US 2006/0237830 A1; hereinafter Danno).
With respect to claim 3, Ito discloses the semiconductor device according to claim 2, wherein the first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) is one of a plurality of the first terminals (see Figs. 1 and 2 and paragraphs 60-63).
Ito does not disclose wherein a ground terminal extending from the first edge portion is provided between the plurality of first terminals.
Danno discloses a similar semiconductor device in Figs. 1-13 including a ground terminal (ground lines) extending from a first edge portion is provided between a plurality of first terminals (signal lines) (see Figs. 1, 2, 5, and paragraphs 147-149, 152-154).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the semiconductor device of Ito a ground terminal extending from the first edge portion would be provided between the plurality of first terminals as taught by Danno thus magnetically shielding the signal line and hence, the signal line hardly receives the cross talk (see Danno: paragraph 154).
Claims 4, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (US 2004/0113248 A1; hereinafter Ito) in view of Uno et al. (US 2014/0077345 A1; hereinafter Uno).
With respect to claim 4, Ito discloses the semiconductor device according to claim 2, wherein the peripheral edge of the base 5 includes a third edge portion (left or right side of 5 in Fig. 7) that connects the first edge portion (right edge of 5 in Fig. 2) and the second edge portion (left edge of 5 in Fig. 2) to each other (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115).
Ito does not explicitly disclose wherein the third edge portion provides a side recess portion; and a third terminal is arranged in the side recess portion.
Uno discloses a similar semiconductor device in Figs. 1-3 and 7 wherein a third edge portion provides a side recess portion 11d; and a third terminal (screw) is arranged in the side recess portion 11d (see Figs. 1-3 and paragraphs 110, 113, 114; screws provide physical and thermal connection terminal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the third edge portion of Ito would provide a side recess portion; and a third terminal would be arranged in the side recess portion as taught by Uno the undersurface of the die pad exposed from the resin is directly screwed or soldered to a module case or a heat sink, thereby allowing heat generated by the semiconductor element to be effectively dissipated (see Uno: paragraph 31).
With respect to claim 11, Ito discloses the semiconductor device according to claim 1, wherein, in the overlap region, a first distance L1 along the thickness direction between the first terminal (comprising 1a, 1b, 1d on right side in Fig. 2) and the base 5, and in a non-recessed region (5a at right edge) of the first edge portion (right edge of 5 in Fig. 2) a second distance L2 between the first terminal (comprising 1a, 1b, 1d on right side in Fig. 2) and the first surface 5a, with the first distance L1 being greater than the second distance L2 (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115; also see Fig. 2 annotated above showing distance L1 is larger than distance L2).
Ito does not explicitly disclose wherein the first distance is 0.2 mm to 0.5 mm or wherein the second distance is 0.1 mm to 0.25 mm.
Uno discloses a similar semiconductor device in Figs. 1-4 and 7 where the thickness of components range from 0.2 to 1.2 mm (see Figs. 1-4 and 7 and paragraphs 119, 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the semiconductor device of Ito the first distance would be 0.2 mm to 0.5 mm and second distance would be 0.1 mm to 0.25 mm because the combined teachings of Ito and Uno disclose the general conditions of the claim and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I). Additionally, the shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious (see MPEP 2144.04 IV B).
With respect to claim 15, the combination of Ito and Uno discloses the device of claim 11, wherein the first distance is at least 1.3 times the second distance (see Ito: Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115; also see Fig. 2 annotated above showing distance L1 is larger than distance L2. Also see Uno: Figs. 1-4 and 7 and paragraphs 119, 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the semiconductor device of Ito the first distance would be at least 1.3 times the second distance because the combined teachings of Ito and Uno disclose the general conditions of the claim and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I). Additionally, the shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious (see MPEP 2144.04 IV B).
Allowable Subject Matter
Claims 8, 12, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest:
wherein the stepped recess extends only between a pair of ground terminals provided along the first edge portion and is centered with respect to the first terminal, as called for in claim 8;
wherein, when viewed from the thickness direction, the stepped recess has a rectangular plan shape with its long sides extending along a Y-direction and a length in the Y-direction larger than a length of the first end portion of the first terminal, the stepped recess extends over an entire region in the Y-direction between a pair of ground terminals provided along the first edge portion, and a center of the stepped recess coincides with a center of the first terminal, as called for in claim 12; and
wherein, on a back surface of the first edge portion, regions that do not overlap the first region when viewed from the thickness direction include respective second stepped portions formed stepwise toward the first surface and located at both end portions in the Y-direction between the pair of ground terminals, as called for in claim 13.
Response to Arguments
Applicant's arguments filed December 5th, 2025 have been fully considered but they are not persuasive.
The applicant argues that “Ito does not teach a stepped recess at the peripheral edge that is expressly overlapped by the terminal end connected to the chip and, critically, does not disclose the comparative distance requirement between an overlap region and a non-recessed region of the same edge.” The examiner respectfully disagrees.
As outlined in the rejection above, Ito teaches a first edge portion (right edge of 5 in Fig. 2) that includes a stepped recess 5c recessed from the first surface 5a toward the second surface 5b in a first region of a peripheral edge of the base 5 and a non-recessed region (5a at right edge) (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115); a first terminal (comprising 1a, 1b, 1d at right side in Fig. 2) that is arranged at a position facing the first edge portion (right edge of 5 in Fig. 2) when viewed from a thickness direction of the base 5 (see Figs. 1 and 2 and paragraphs 60-63, 88, 93); and wherein a first end portion (where 4 contacts 1a on right in Fig. 2) of the first terminal (comprising 1a, 1b, 1d on right side in Fig. 2) that is connected to the semiconductor element 2 is positioned to overlap the stepped recess 5c in an overlap region when viewed from the thickness direction, and, in the overlap region, a distance L1 along the thickness direction between the first end portion (where 4 contacts 1a on right in Fig. 2) and a surface of the stepped recess 5c is greater than a distance L2 between the first end portion (where 4 contacts 1a on right in Fig. 2) and the first surface 5a in the non-recessed region (5a at right edge) of the first edge portion (right edge of 5 in Fig. 2) (see Figs. 1, 2, 7-9 and paragraphs 93, 94, 96, 114, 115; also see Fig. 2 annotated above showing distance L1 is greater than distance L2). Ito teaches a stepped recess at the peripheral edge that is expressly overlapped by the terminal end connected to the chip and, discloses the comparative distance requirement between an overlap region and a non-recessed region of the same edge.
The applicant argues that “Uno does not suggest coordinating a third-edge recess with the first-edge stepped recess whose center is aligned to a signal terminal and that is bounded only by a pair of ground terminals, nor does Uno teach the overlap-and-distance constraints of claim 1.” The examiner respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., coordinating a third-edge recess with the first-edge stepped recess whose center is aligned to a signal terminal and that is bounded only by a pair of ground terminals) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The claims remain rejected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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