DETAILED ACTION
This Office action responds to the Amendment file on October 20, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on October 20, 2025, responding to the Office action mailed on June 20, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Response to Arguments
Applicant’s arguments with respect to the claims filed on October 20, 2025, have been considered. Applicant argues “FIGs. 1A, 1B, and 1B clearly illustrates an isolation ring that isolates the pixel transistor region from the first and second of photodiodes”. FIG. 1A is a top view only shows the isolation region 103 as horizontal bars on two sides of photodiodes 104 and the pixel transistor region 102. FIGs. 1B and 1C are cross-sectional view of lines AA' and BB' only shows the isolation region 103 between the photodiodes 104 and the pixel transistor region 102. None of the drawings shows “an isolation structure that encloses and isolates the pixel transistor region from the first photodiode and the second photodiode”. The word, “enclose” means surrounding on all sides, not just two sides. Providing isolation method(s) among different electrical components on the same substrate is a well-known technique in the semiconductor art to avoid interference among each other.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the isolation structure that encloses and isolates the pixel transistor region from the first photodiode and the second photodiode” and “an isolation structure that encloses the first pixel region and isolates the pixel transistor region from the first pixel region” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394), and further in view of McKee et al. (McKee hereinafter) (US 2007/0045679).
Regarding Claims 1, 3, 4, and 9:
Wang (see, paras. [0016], [0022]-[0027], and [0031] and FIGs. 10A and10B) teaches a SPAD image sensor 100 includes a plurality of SPADS arranged in an array within a substrate, “a plurality of isolation structure 108 to electrically isolate the second heavily doped region 120 and the third heavily doped region 120”, “the first deep well 112 and the first heavily doped region 114 are doped with p-type dopants”, “a buried doped layer 116 … a second conductivity type … n-type conductivity”, “a second deep well 118 of the second conductivity type and a second heavily doped region 120 of the second conductivity type”, ““the isolation structures 108 also electrically isolate SPADs 110 from other circuits of the image sensor 100 at the periphery of the semiconductor substrate 102”, and “source/drain regions for CMOS transistors in peripheral circuits (not shown)”.
a semiconductor substrate (102) having a first side (104) and a second side that is opposite the first side;
a first pixel region that includes at least one first photodiode (110), the first photodiode comprising
a first region (114) formed from a first type semiconductor on the first side of the semiconductor substrate and
a second region (120, 118) formed from a second type semiconductor on the first side of the semiconductor substrate;
a pixel transistor region including at least one transistor; and
an isolation structure (108) that isolates the pixel transistor region from the first photodiode,
the isolation structure on the first side of the semiconductor substrate comprising
a first shallow trench isolation (STI) structure (108) that is proximate to the second region (120, 118) of the first photodiode,
a third region (122) formed from the first type semiconductor that is proximate to the first STI structure,
a second STI structure (108) that is proximate to the third region
However, Wang does not explicitly teach the CMOS transistor being adjacent to the SPAD nor an implant region (bold text below).
a second STI structure (108) that is proximate to the third region (122) and that is proximate to the pixel transistor region, and
an implant region formed from the first type semiconductor that is in contact with the third region and extends toward the second side of the semiconductor substrate.
Nagaraja (see, para. [0004] and FIGs 1A, 1C, , 3, and 5A-5E) teaches a CMOS image sensor 100 having a pixel circuitry region 130, 315 adjacent to a photo-sensor or photodiode (PD) region 115, 310.
McKee (see, paras. [0006], [0024], [0025], and [0037] and FIGs 2-3 and 6) teaches “shallow trench isolation (STI) in one technique that can be used to isolate pixels from one another in a pixel array, or other integrated structures from one another … in a typical STI isolation structure 102 … to provide a physical and electrical barrier between adjacent active areas within a substrate … to enhance the isolation further, ions may be implanted into the silicon substrate 101 in the area 140 directly beneath the trench 117”, “two adjacent pixel cells 301, 302 having photosensors 303, 304 separated by an isolation region 222 … consists of at least one p-well ion implant 250”, “the ion-implant isolation region 222 has a p+ enhancement layer 251”, and “Isolation regions 222 … are located between each two adjacent photosensors … other types of isolation regions 320 may also be used … may be STI or LOCOS regions”
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Wang to include the teaching of Nagaraja to allow the CMOS transistor near and isolated from the SPAD to provide a variety of functionality for the regular operation of the CMOS image sensors and to further include the teaching of McKee by adding more ion-implant regions beneath the heavily doped region 122 to create additional ion-implant isolation structure between the isolation structure 108 to further enhance the isolation between the SPADs and other structures.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394) and further in view of McKee et al. (McKee hereinafter) (US 2007/0045679) as applied to claim 1 above, and further in view of Gu (US 2021/0343765).
Regarding Claim 2:
The combination of Wang in the device of Nagaraja in view of McKee does not explicitly teach a trench isolation structure extending from the second side toward the first side of the semiconductor substrate to contact the implant region.
However, Gu (see, paras. [0055], [0070], and [0064] and FIG. 3) teaches a CMOS image sensor comprising a first isolation region 250 and a second isolation region, “the first isolation region 250 may be doped with specific conductivity-type impurities” and “may be arranged to be in contact with a first surface (i.e., a top surface or a front surface) of the substrate 310”, “the second isolation region 260 may be formed … in a vertical direction from a second surface (i.e., a bottom surface or a back surface) opposite to the first surface including the first isolation region 250 to the first surface”,
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Wang in the device of Nagaraja in view of McKee to further include the teaching of Gu to form a backside isolation structure connecting to the ion-implant region and the heavily doped region 122 to completely isolate the SPADs in order to prevent the movement of overflown photo-charges from SPADs.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394) and further in view of McKee et al. (McKee hereinafter) (US 2007/0045679) as applied to claim 1 above, and further in view of Finkelstein (US 11,296,137).
Regarding Claims 5-8:
The combination of Wang in the device of Nagaraja in view of McKee does not explicitly teach the cathode are shared between two adjacent SPADs nor the deep well 118 being a guard ring.
However, Finkelstein (see, col.10/ll.10-47 and col.14/ll.28-47 and FIGs. 1C-2B) teaches a CMOS image sensor comprising of “the photodetector devices 200a, 200b may include first and second electrodes 107n, 107p … may define respective anodes and cathodes of each of the photodiodes 105a, 105b in a pixel and comprising of the photodetector device 100c and a photodiode 105 with “a guard ring structure 105g for more uniform avalanche breakdown”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Wang in the device of Nagaraja in view of McKee to further include the teaching of Finkelstein to form the second deep well 118 as a guard ring contacting the buried doped deep layer 116 to generate more uniformed avalanche breakdown and to share the cathode of two adjacent SPADs instead of placing pixel transistor adjacent to each SPAD to meet the design rules.
Claims 10, 12, 13, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394), further in view of McKee et al. (McKee hereinafter) (US 2007/0045679), and further in view of Bahl, et al. (Bahl hereinafter) (EP 1 750 308).
Regarding Claims 10, 12, 13, 17, 19, and 20:
Wang (see, paras. [0016], [0022]-[0027], [0031], FIGs. 10A, 10B) teaches a SPAD image sensor 100 includes a plurality of SPADS arranged in an array within a substrate, “a plurality of isolation structure 108 to electrically isolate the second heavily doped region 120 and the third heavily doped region 120”, “the first deep well 112 and the first heavily doped region 114 are doped with p-type dopants”, “a buried doped layer 116 … a second conductivity type … n-type conductivity”, “a second deep well 118 of the second conductivity type and a second heavily doped region 120 of the second conductivity type”, ““the isolation structures 108 also electrically isolate SPADs 110 from other circuits of the image sensor 100 at the periphery of the semiconductor substrate 102”, and “source/drain regions for CMOS transistors in peripheral circuits (not shown)”.
However, Wang does not explicitly teach the CMOS transistor being adjacent to the SPAD nor an implant region (bold text below) nor an isolation structure encloses the pixel transistor region from the photodiodes and encloses the first pixel region.
Nagaraja (see, para. [0004] and FIGs 1A, 1C, , 3, and 5A-5E) teaches a CMOS image sensor 100 having a pixel circuitry region 130, 315 adjacent to a photo-sensor or photodiode (PD) region 115, 310.
McKee (see, paras. [0006], [0024], [0025], and [0037] and FIGs 2 and 3) teaches “shallow trench isolation (STI) in one technique that can be used to isolate pixels from one another in a pixel array, or other integrated structures from one another … … in a typical STI isolation structure 102 … to provide a physical and electrical barrier between adjacent active areas within a substrate …an STI structure 102 can be formed by etching a trench 117 and then filling it with a dielectric 124 … to enhance the isolation further, ions may be implanted into the silicon substrate 101 in the area 140 directly beneath the trench 117”, “two adjacent pixel cells 301, 302 having photosensors 303, 304 separated by an isolation region 222 … consists of at least one p-well ion implant 250”, and “the ion-implant isolation region222 has a p+ enhancement layer 251”, and “Isolation regions 222 … are located between each two adjacent photosensors … other types of isolation regions 320 may also be used … may be STI or LOCOS regions”
.
Bahl (see, paras. [0017]-[0024] and FIGs 3-4) teaches a CMOS image sensor 300 comprising of a horizontal barrier layer 324 on a substrate 302 and a deep trench 326, “deep p-well 322 together with trench 326 function as a lateral barrier layer between adjacent pixels to prevent lateral diffusion between the pixels”, and “masks 400 provided between each of the plurality of pixels 402 … to define trenches 326 … form the lateral barrier layers that prevent lateral diffusion between adjacent pixels”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Wang to include the teaching of Nagaraja to allow the CMOS transistor near and isolated from the SPAD to provide a variety of functionality for the regular operation of the CMOS image sensors, to further include the teaching of McKee by adding more ion-implant regions beneath the heavily doped region 122 to create additional ion-implant isolation structure between the isolation structure 108 in order to support high voltage/power applications, and to further include the teaching of Bahl to surround individual SPAD or to surround the combination of one or more of SPADs and one CMOS transistor with one or more isolation structures having different depths to prevent the lateral diffusion between the adjacent SPADs by design rules.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394), further in view of McKee et al. (McKee hereinafter) (US 2007/0045679), and further in view of Bahl et al. (Bahl hereinafter) (EP 1 750 308) as applied to claim 10 or 17 above, and further in view of Gu (US 2021/0343765).
Regarding Claims 11 and 18:
The combination of Wang in the device of Nagaraja in view of McKee further in view of Bahl does not explicitly teach a trench isolation structure extending from the second side toward the first side of the semiconductor substrate to contact the implant region.
However, Gu (see, paras. [0055], [0070], and [0064] and FIG. 3) teaches a CMOS image sensor comprising a first isolation region 250 and a second isolation region, “the first isolation region 250 may be doped with specific conductivity-type impurities” and “may be arranged to be in contact with a first surface (i.e., a top surface or a front surface) of the substrate 310”, “the second isolation region 260 may be formed … in a vertical direction from a second surface (i.e., a bottom surface or a back surface) opposite to the first surface including the first isolation region 250 to the first surface”,
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Wang in the device of Nagaraja in view of McKee and further in view of Bahl to further include the teaching of Gu to form a backside isolation structure connecting to the ion-implant region and the heavily doped region 122 to completely isolate the SPADs in order to prevent the movement of overflown photo-charges from other SPADs.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang hereinafter) (US 2020/0020734) in view of Nagaraja et al. (Nagaraja hereinafter) (US 2009/0230394), further in view of McKee et al. (McKee hereinafter) (US 2007/0045679), and further in view of Bahl et al. (Bahl hereinafter) (EP 1 750 308) as applied to claim 10 above, and further in view of Finkelstein (US 11,296,137).
Regarding Claims 14-16:
The combination of Wang in the device of Nagaraja in view of McKee and further in view of Bahl does not explicitly teach the cathode shared between two adjacent SPADs and the deep well 118 and the buried doped layer 116 being a guard ring.
However, Finkelstein (see, col.10/ll.10-47 and col.14/ll.28-47 and FIGs. 1C, 2A and 2B) teaches a CMOS image sensor comprising of “the photodetector devices 200a, 200b may include first and second electrodes 107n, 107p … may define respective anodes and cathodes of each of the photodiodes 105a, 105b in a pixel and comprising of the photodetector device 100c and a photodiode 105 with “a guard ring structure 105g for more uniform avalanche breakdown”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Wang in the device of Nagaraja in view of McKee and further in view of Bahl to further include the teaching of Finkelstein to form the second deep well 118 as a guard ring contacting the buried doped deep layer 116 with more uniformed avalanche breakdown and to share the cathode of two adjacent SPADs instead of placing pixel transistor adjacent to each SPAD in order to meet the design rules.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814