DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note, the restriction has been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al.(US 2021/0090902) in view of Hsich et al.(US 2011/0042794).
Regarding claim 1, Cho et al. discloses a multi-layer substrate(fig 5, 110, 120a, 120b)), a dielectric layer(fig 2, 111); at least one pad layer formed in the dielectric layer(fig 2, 120); and at least one protective metal layer formed on the at least one pad layer and bonded to the at least one pad layer(fig , 130), wherein the at least one protective metal layer only covers an upper surface of the at least one pad layer(fig 2), the at least one protective metal layer is configured to contact an external element (fig 2, 195, as well as the protective layer shown in figure 2, top surface, yet not labeled or discussed in the specification), there is no height difference between an upper surface of the at least one protective metal layer and an upper surface of the dielectric layer(fig 2). Cho et al. shows in fig 2 a surface finish structure of the multi-layer substrate is completely bonded to a surface of the external element( the structure surrounding element 190 and mating with layer 160) without any gap without discussing this aspect of the invention in the specification). Additionally, Hsich et al. discloses a surface finish structure of the substrate(fig 10, the surface of 40) is completely bonded to a surface of the external element(fig 10, 30). It would have been obvious to one skilled in the art at the time of the invention to use a surface finish structure of the multi-layer substrate that is completely bonded to a surface of the external element so as to protect the surface components of the circuit board.
Regarding claim 2, Cho et al. discloses wherein a material of the dielectric layer is polyimide(para0071).
Regarding claim 3, Cho et al. discloses wherein a material of the at least one pad layer is copper.(para 0025).
Regarding claim 4, Cho et al. discloses wherein a material of the at least one protective metal layer is selected from the group consisting of chromium, nickel, palladium, and gold(para 0088).
Regarding claim 5, Cho et al. discloses a dielectric layer(fig 2, 111); at least one pad layer(fig 2, 120), wherein a part of the at least one pad layer is formed in the dielectric layer(fig 2); and at least one protective metal layer formed on the at least one pad layer and bonded to the at least one pad layer(fig 2, 130), wherein the at least one protective metal layer only covers an upper surface of the at least one pad layer(fig 2), the at least one protective metal layer is configured to contact an external element fig 2, 195, as well as the protective layer shown in the figure, top surface, yet not labeled or discussed in the specification), there is no height difference between an upper surface of the at least one protective metal layer(fig 2, 130) adjacent to the dielectric layer(fig 2, 160). an upper surface of the dielectric layer, and the surface finish structure of the multi-layer substrate is completely bonded toa surface of the external element without any gap.
Cho et al. shows in fig 2 an upper surface of the dielectric layer, and the surface finish structure of the multi-layer substrate is completely bonded toa surface of the external element without any gap(the structure surrounding element 190 and mating with layer 160) without any gap without discussing this aspect of the invention in the specification). Additionally, Nakunura et al. discloses an upper surface of the dielectric layer, and the surface finish structure of the multi-layer substrate (fig 4, the surface of 10) is completely bonded to a surface of the external element without any gap (fig 4, 44; para 53, 0054). It would have been obvious to one skilled in the art at the time of the invention to use a surface finish structure of the multi-layer substrate that is completely bonded to a surface of the external element without any gap so as to protect the surface components of the circuit board.
Regarding claim 6, Cho et al. discloses wherein a material of the dielectric layer is polyimide(para0071).
Regarding claim 7, Cho et al. discloses wherein a material of the at least one pad layer is copper.(para 0025).
Regarding claim 8, Cho et al. discloses wherein a material of the at least one protective metal layer is selected from the group consisting of chromium, nickel, palladium, and gold(para 0088).
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al.(US 2021/0090902) In view of Hsich et al.(US 2011/0042794) and further in view of Cho et al.(US 2016/0225706) herein in after “Cho2”.
Regarding claim 9, Cho et al. does not disclose wherein an upper surface of a remaining part of the at least one protective metal layer excluding the upper surface of the at least one protective metal layer adjacent to the dielectric layer is a protrusion shape or a recessed shape. However Cho2 discloses a pad (fig 2, 105) with in the insulating layer with a recessed shape(fig 2, 110). It would have been obvious to one skilled in the art at the time of the invention to place a recess in the middle of the pad as shown by Cho2, with a modified Cho since this is a way to better control the solder from straying form the pad.
Regarding claim 10, Cho et al. discloses wherein a material of the dielectric layer is polyimide(para0071).
Regarding claim 11, Cho et al. discloses wherein a material of the at least one pad layer is copper.(para 0025).
Regarding claim 12, Cho et al. discloses wherein a material of the at least one protective metal layer is selected from the group consisting of chromium, nickel, palladium, and gold(para 0088).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy Thompson whose telephone number is (571)272-2342. The examiner can normally be reached Monday-Friday 8:00 AM-4:30 PM EST.
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/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847