DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (“Chang” US 2021/0202336).
Regarding claim 1, Chang discloses a packaging structure (Figure 6), comprising:
a substrate (1), comprising a bonding surface (upper surface),
a chipset (376/268), bonded to the bonding surface (upper surface of substrate 1, see Figure 6) and comprising a plurality of first chips (376 and memory dice 268) stacked along a longitudinal direction (see Figure 6), wherein a first chip (376) of the plurality of first chips (376/268) that is adjacent to the substrate (1) is used as a bottom chip (376), each of the rest of the first chips (268) of the plurality of first chips (376/268) is used as a top chip (268), the bottom chip (376) is electrically connected to the substrate (1, through interconnect structures on the upper surface and through the upper chips 268 and 24) and an adjacent first chip (lowermost die 268) of the plurality of first chips (376/268), and a first portion of the bottom chip (left side of 376) is exposed from a first side of the top chip (268, left side in Figure 6) and a second portion of the bottom chip (right side of 376) is exposed from a second side of the top chip (268, right side in Figure 6, the left and right side portions of bottom chip 376 do not vertically overlap with the top chip 268);
a second chip (24), bonded to the first portion of the bottom chip (left side of bottom chip 376) exposed from the top chip (268) and to the bonding surface (upper surface of substrate 1) on a side of the chipset (376/268), wherein the second chip (24), the bottom chip (376), the top chip (268), and the substrate (1) are electrically connected (see para. [0054]), and a projection of the second chip (24) and a projection of the bottom chip (376) on a projection plane parallel to the bonding surface (upper surface of substrate 1) partially overlap (see Figure 6); and
a molding layer (molding layer includes the encapsulant 269 and portions of insulating materials 32 and 374 directly between the vertical projections of the top chip 268 and the bottom chip 376) covering and being in contact with a sidewall of the top chip (268, portion of encapsulant 269 is in direct physical contact and covering sidewalls of the top chip 268, see highlighted in annotated Figure 6 below), and covering and being in direct contact with a top surface of the second portion of the bottom chip (top surface of the right side portion of bottom chip 376 is in direct contact with the portion 374 of the molding layer and is covered by portions 32/269 of the molding layer 32/269/374) without being in contact with a sidewall of the bottom chip (376, the lower, bottom surface sidewall of the bottom chip 376 is not in contact with the molding layer 32/269/374, here the bottom surface is considered as a sidewall because the bottom side is a side of the bottom chip).
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Regarding claim 3, Chang discloses wherein a first interconnecting structure is formed in the bottom chip (376, see para. [0054], which discloses that the bottom chip “bridge die” 376 electrically connects the second chip 24 and the top chip 268, of device 26, and thus would contain and interconnecting structure) exposed from the top chip (268), the first interconnecting structure (structure connecting the second chip 24 and the top chip 268) is electrically connected to the top chip (268), and the second chip (24) bonded to the bottom chip (376) is electrically connected to the first interconnecting structure (see para. [0054]).
Regarding claim 7, Chang further discloses a plurality of chipsets (see Figure 1), wherein the second chip (24) partially overlaps and is electrically connected to each of the bottom chips (376) of a plurality of adjacent chipsets (see interconnect structure of Figure 1 indicating the bottom chip, or the high density area of the substrate which corresponds to the bottom chip, which is vertically aligned with the bottom chip in Figure 9, showing overlap of bottom chip and second chip).
Regarding claim 8, Chang discloses wherein the substrate (1) comprises a base (145) and an interconnecting structure layer (circuit layers 151-154) on the base (145, see Figure 6),
a surface exposed from the interconnecting structure layer (151-154) is the bonding surface (bonding surface is the surface of conductive bumps/circuit layer 17, to which the components are bonded, upper surfaces of bumps 17 are exposed from the interconnecting structure layer because the two surfaces are not in direct physical contact), and the bottom chip (376) is electrically connected to the interconnecting structure layer (through other interconnection structures and the chips), and the second chip (24) is electrically connected to the interconnecting structure layer (151-154, see Figure 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above, and further in view of Jeng et al. (“Jeng” US 2023/0352463).
Regarding claim 2, Chang does not disclose a groove in the substrate.
However, Jeng discloses in Figure 7 a groove (recess 106) in the substrate (102) on a side of the bonding surface (upper surface of the substrate 102, see Figure 7), and the bottom chip (bridge die 78) is arranged in the groove (106, see Figure 7).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Jeng into the teachings of Chang to include a groove in the substrate for the purpose of increasing high-density interconnections (see Jeng, para. [0012])
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment (Figure 6) of Chang applied to claim 1 above and further in view of another embodiment of Chang.
Regarding claim 4, Chang discloses in the embodiment of Figure 9:
wherein a second interconnecting structure (64) extending through the bottom chip (6) is formed in the bottom chip (6, see Figure 9), and the substrate (1) is electrically connected to the top chip (26) longitudinally adjacent to the bottom chip (6) by the second interconnecting structure (64, see para. [0057]).
It would have been obvious to incorporate the teachings of Chang’s Figure 9 into Chang’s Figure 6 to include the second interconnecting structure 64 in Figure 9 into the bottom chip 376 of Figure 6 for the purpose of connecting the chips 24, 268 to the substrate 1 through the bottom chip, which would increase interconnection density (Chang, para. [0057]).
Regarding claim 5, Chang further discloses second conductive bumps (245), arranged between the second chip (24) and the bottom chip (376, see Figure 9), and between the second chip (24) and the substrate (1), wherein the second conductive bumps (245) electrically connect the second chip (24) to the bottom chip (376) and electrically connect the second chip (24) to the substrate (1, see Figure 6).
Chang discloses that the bottom chip of Figure 6 (376) is electrically connected to the substrate via the interconnection structures and the chips, but Chang’s embodiment of Figure 6 does not disclose first conductive bumps, arranged between the bottom chip and the substrate.
Chang discloses in the embodiment of Figure 9:
first conductive bumps (17), arranged between the bottom chip (6) and the substrate (1), and electrically connecting the bottom chip (6) to the substrate (1, para. [0057]).
It would have been obvious to incorporate the teachings of Chang’s Figure 9 into Chang’s Figure 6 in the manner above to further increase interconnection density (Yang, see Figure 9, para. [0057]).
Regarding claim 6, Chang discloses in the embodiment of Figure 6:
a sealing layer (sealing layer includes portions of insulating materials 32 and 374 directly between the vertical projections of the second chip 24 and the bottom chip 376, as well as portions of insulating material 32 laterally between the top chip 268 and the second chip 24, see highlighted in annotated Figure 6) arranged between the bottom chip (376) and the substrate (see annotated Figure 6) and between the second chip (24) and the substrate (1), and filling a gap between the top chip (268) and the second chip (24, see annotated Figure 6), a gap between adjacent first conductive bumps (17, incorporated by Figure 9 between the bottom chip and the substrate, where the portion 374 fills the gap between adjacent conductive bumps 17 in Figure 9), and a gap between adjacent second conductive bumps (245, see annotated Figure 6).
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Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above and further in view of Chiang et al. (“Chiang” US 2020/0243449).
Regarding claim 9, Chang discloses wherein … the top chip (268) is a memory chip (para. [0047]), and the second chip (24) is a second logic chip (para. [0046] discloses 24 as an ASIC die which is a known logic/processing die).
Chang does not explicitly disclose the bottom chip is a first logic chip, Chang discloses that the bottom chip 376 is a bridge die (para. [0054]).
Chiang discloses wherein the bottom chip (131) is a first logic chip (para. [0022]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chiang into the teachings of Chang to include the bottom chip (bridge die 376 of Chang) is a first logic chip because Chiang discloses that a bridge die may be any suitable die, such as a logic die (Chiang, para. [0022]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment (Figure 6) of Chang applied to claim 1 above and further in view of another embodiment of Chang.
Regarding claim 11, Chang further discloses in the embodiment of Figure 10:
a thermally conductive layer (48) arranged on the chipset (26/268 and 6) and a top of the second chip (24, see Figure 9).
It would have been obvious to a person having ordinary skill in the art to incorporate the features of Chang’s Figure 10 into the features of Chang’s Figure 6 to include a thermally conductive layer arranged on the chipset and a top surface of the second chip for the purpose of attaching a heat sink to the device for heat dissipation (Chang, para. [0059]).
Regarding claim 12, Chang further discloses in the embodiment of Figure 10:
a packaging housing (46) arranged on the substrate (1) and packaging the packaging structure (packaging structure 3).
It would have been obvious to a person having ordinary skill in the art to incorporate the features of Chang’s Figure 10 into Chang’s Figure 6 to include a packaging housing arranged on the substrate and packaging the packaging structure for the purpose of heat dissipation (Chang, para. [0059]).
Response to Arguments
Applicant’s arguments, see Remarks, filed April 23 2026, with respect to the 112(a) rejection of claim 10 have been fully considered and are persuasive. The 112(a) rejection of claim 10 has been withdrawn. The Examiner notes that Applicant has cancelled claim 10 but has amended claim 1 to include similar features that were recited in claim 10. Claim 1 is not currently being rejected under 112(a).
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any interpretation of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/GENEVIEVE G BULLARD CONNOR/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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