DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 21 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 requires the limitation “a molding layer…covering and being in contact with a top surface of the second portion of the bottom chip without being in contact with a sidewall of the bottom chip”. The underlined portion of the claim has introduced new matter. The Figures of the instant application only show some cross-sectional views, see for example Figures 1-2 and 4-8. It is the Examiner’s position that the molding layer could be covering the sidewalls of the bottom chip 310 in other cross-sectional views not explicitly shown, since it is not explicitly disclosed that the molding layer 370 is only contacting a top surface of the bottom chip 310, and not contacting the sidewall of the bottom chip 310. Further, it could be argued that the molding layer 370 is in fact contacting the sidewall of the bottom chip 310 because the upper left corner of the sidewall of the bottom chip (see Figure 2) is in contact with the lower left corner of the molding layer 370. Finally, the instant specification describes that the molding layer 370 “covers a sidewall of the first chip 330 and the bottom chip 310 exposed from the top chip 320, to protect the structure of the chipset 300” (see para. [0108]). It is the Examiner’s position that the above quotation from the specification is potentially disclosing that the molding layer covers the sidewall of the first chip 330 and the sidewall of the bottom chip. Thus, the amendments to claim 10 have introduced new matter to the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (“Chang” US 2021/0202336) and Jeng et al. (“Jeng” US 2023/0352463).
Regarding claim 1, Chang discloses a packaging structure (Figure 6), comprising:
a substrate (1), comprising a bonding surface (upper surface),
a chipset (376/268), bonded to the bonding surface (upper surface of substrate 1, see Figure 6) and comprising a plurality of first chips (376 and memory dice 268) stacked along a longitudinal direction (see Figure 6), wherein a first chip (376) of the plurality of first chips (376/268) that is adjacent to the substrate (1) is used as a bottom chip (376), each of the rest of the first chips (268) of the plurality of first chips (376/268) is used as a top chip (268), the bottom chip (376) is electrically connected to the substrate (1, through interconnect structures on the upper surface and through the upper chips 268 and 24) and an adjacent first chip (lowermost die 268) of the plurality of first chips (376/268), and a first portion of the bottom chip (left side of 376) is exposed from a first side of the top chip (268, left side in Figure 6) and a second portion of the bottom chip (right side of 376) is exposed from a second side of the top chip (268, right side in Figure 6, the left and right side portions of bottom chip 376 do not vertically overlap with the top chip 268); and
a second chip (24), bonded to the first portion of the bottom chip (left side of bottom chip 376) exposed from the top chip (268) and to the bonding surface (upper surface of substrate 1) on a side of the chipset (376/268), wherein the second chip (24), the bottom chip (376), the top chip (268), and the substrate (1) are electrically connected (see para. [0054]), and a projection of the second chip (24) and a projection of the bottom chip (376) on a projection plane parallel to the bonding surface (upper surface of substrate 1) partially overlap (see Figure 6).
Chang does not disclose that a bottom surface of the bottom chip is lower than the bonding surface and a top surface of the bottom chip is higher than the bonding surface.
However, Jeng discloses a bottom chip (bridge die 78) with a bottom surface lower than a bonding surface of a substrate (upper surface of the substrate on which the package components 20, and 50 are mounted) and a top surface of the bottom chip (78) is higher than the bonding surface (top surface of substrate 102, see Figure 7 and para. [0040]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Jeng above into the teachings of Chang. All of the claimed elements were known in the prior art, namely the structure including a bottom die with a lower surface lower than the top bonding surface of the substrate and an upper surface above the top bonding surface of the substrate as taught by Jeng, and the remaining claim limitations taught by Chang above. The combination would have no change in the respective functions of the teachings of Chang and Jeng and would have resulted in the predictable result of increasing device and interconnect density due to an embedded bridge die as disclosed by Jeng (see para. [0012]). See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 2, Jeng discloses in Figure 7 a groove (recess 106) in the substrate (102) on a side of the bonding surface (upper surface of the substrate 102, see Figure 7), and the bottom chip (bridge die 78) is arranged in the groove (106, see Figure 7).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Jeng into the teachings of Chang to include a groove in the substrate for the purpose of increasing high-density interconnections (see Jeng, para. [0012])
Regarding claim 3, Chang discloses wherein a first interconnecting structure is formed in the bottom chip (376, see para. [0054], which discloses that the bottom chip “bridge die” 376 electrically connects the second chip 24 and the top chip 268, of device 26, and thus would contain and interconnecting structure) exposed from the top chip (268), the first interconnecting structure (structure connecting the second chip 24 and the top chip 268) is electrically connected to the top chip (268), and the second chip (24) bonded to the bottom chip (376) is electrically connected to the first interconnecting structure (see para. [0054]).
Regarding claim 7, Chang further discloses a plurality of chipsets (see Figure 1), wherein the second chip (24) partially overlaps and is electrically connected to each of the bottom chips (376) of a plurality of adjacent chipsets (see interconnect structure of Figure 1 indicating the bottom chip, or the high density area of the substrate which corresponds to the bottom chip, which is vertically aligned with the bottom chip in Figure 9, showing overlap of bottom chip and second chip).
Regarding claim 8, Chang discloses wherein the substrate (1) comprises a base (145) and an interconnecting structure layer (circuit layers 151-154) on the base (145, see Figure 6),
a surface exposed from the interconnecting structure layer (151-154) is the bonding surface (bonding surface is the surface of conductive bumps/circuit layer 17, to which the components are bonded, upper surfaces of bumps 17 are exposed from the interconnecting structure layer because the two surfaces are not in direct physical contact), and the bottom chip (11) is electrically connected to the interconnecting structure layer (through other interconnection structures and the chips), and the second chip (24) is electrically connected to the interconnecting structure layer (151-154, see Figure 6).
Regarding claim 10, Chang further discloses a molding layer (32/269) covering and being in contact with a sidewall of the top chip (268, portion of encapsulant 269 is in direct physical contact and covering sidewalls of the top chip 268), and covering and being in contact with a top surface of the second portion of the bottom chip (right side of bottom chip 376) without being in contact with a sidewall of the bottom chip (376, the portion 32 of the molding layer is covering the right portion of the bottom chip 376, and is in contact with a top surface of the right portion of the bottom chip through the thin upper layer of material 374 that is overlaying the top surface of the bottom chip, see Figure 6, note that the term “in contact” does not require direct physical contact and can be achieved through intervening layers).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment of Chang applied to claim 1 above and further in view of another embodiment of Chang.
Regarding claim 4, Chang discloses in the embodiment of Figure 9:
wherein a second interconnecting structure (64) extending through the bottom chip (6) is formed in the bottom chip (6, see Figure 9), and the substrate (1) is electrically connected to the top chip (26) longitudinally adjacent to the bottom chip (6) by the second interconnecting structure (64, see para. [0057]).
It would have been obvious to incorporate the teachings of Chang’s Figure 9 into Chang’s Figure 6 to include the second interconnecting structure 64 in Figure 9 into the bottom chip 376 of Figure 6 for the purpose of connecting the chips 24, 268 to the substrate 1 through the bottom chip, which would increase interconnection density (Chang, para. [0057]).
Regarding claim 5, Chang further discloses second conductive bumps (245), arranged between the second chip (24) and the bottom chip (376, see Figure 9), and between the second chip (24) and the substrate (1), wherein the second conductive bumps (245) electrically connect the second chip (24) to the bottom chip (376) and electrically connect the second chip (24) to the substrate (1, see Figure 6).
Chang discloses that the bottom chip of Figure 6 (376) is electrically connected to the substrate via the interconnection structures and the chips, but Chang’s embodiment of Figure 6 does not disclose first conductive bumps, arranged between the bottom chip and the substrate.
Chang discloses in the embodiment of Figure 9:
first conductive bumps (17), arranged between the bottom chip (6) and the substrate (1), and electrically connecting the bottom chip (6) to the substrate (1, para. [0057]).
It would have been obvious to incorporate the teachings of Chang’s Figure 9 into Chang’s Figure 6 in the manner above to further increase interconnection density (Yang, see Figure 9, para. [0057]).
Regarding claim 6, Chang discloses in the embodiment of Figure 6:
a sealing layer (374) arranged between the bottom chip (376) and the substrate (1, a line drawn between the substrate 1 and the bottom chip 376 intersects the sealing layer 374, thus 374 is considered as being between the bottom chip 376 and the substrate 1) and between the second chip (24) and the substrate (1), and filling a gap between the top chip (268) and the second chip (24, the gap between the second chip and top chip extends vertically through the entire device, a portion of which is filled with the sealing layer 374), a gap between adjacent first conductive bumps (17), and a gap between adjacent second conductive bumps (245, the gap between adjacent bumps 245 extends vertically through the entire device, a portion of which is filled with sealing material 374, see Figure 9).
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Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over the embodiment of Chang applied to claim 1 above and further in view of another embodiment of Chang.
Regarding claim 11, Chang further discloses in the embodiment of Figure 10:
a thermally conductive layer (48) arranged on the chipset (26/268 and 6) and a top of the second chip (24, see Figure 9).
It would have been obvious to a person having ordinary skill in the art to incorporate the features of Chang’s Figure 10 into the features of Chang’s Figure 6 to include a thermally conductive layer arranged on the chipset and a top surface of the second chip for the purpose of attaching a heat sink to the device for heat dissipation (Chang, para. [0059]).
Regarding claim 12, Chang further discloses in the embodiment of Figure 10:
a packaging housing (46) arranged on the substrate (1) and packaging the packaging structure (packaging structure 3).
It would have been obvious to a person having ordinary skill in the art to incorporate the features of Chang’s Figure 10 into Chang’s Figure 6 to include a packaging housing arranged on the substrate and packaging the packaging structure for the purpose of heat dissipation (Chang, para. [0059]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above and further in view of Chiang et al. (“Chiang” US 2020/0243449).
Regarding claim 9, Chang discloses:
wherein … the top chip (268) is a memory chip (para. [0047]), and the second chip (24) is a second logic chip (para. [0046] discloses 24 as an ASIC die which is a known logic/processing die).
Chang does not explicitly disclose the bottom chip is a first logic chip, Chang discloses that the bottom chip 376 is a bridge die (para. [0054]).
Chiang discloses:
The packaging structure according to claim 1, wherein the bottom chip (131) is a first logic chip (para. [0022]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chiang into the teachings of Chang to include the bottom chip (bridge die 376 of Chang) is a first logic chip because Chiang discloses that a bridge die may be any suitable die, such as a logic die (Chiang, para. [0022]).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any interpretation of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/GENEVIEVE G BULLARD CONNOR/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899