DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28 August 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the rest of the first chips” in claim 1. There is insufficient antecedent basis for this element in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beyne (US 2020/0203309).
Regarding claim 1, Beyne discloses a packaging structure (Figure 3I), comprising:
a substrate (3), comprising a bonding surface (upper surface),
a chipset (13/25), bonded to the bonding surface (upper surface of substrate 3) and comprising a plurality of first chips stacked along a longitudinal direction (see Figure 3I), wherein a first chip of the plurality of first chips that is adjacent to the substrate (3) is used as a bottom chip (25), each of the rest of the first chips of the plurality of first chips is used as a top chip (13), the bottom chip (25) is electrically connected to the substrate (3) and an adjacent first chip of the plurality of first chips (lowermost chip of stack 13, see Figure 3I and para. [0052]), and a first portion of the bottom chip (right end portion of 25 bonded to chip 4) is exposed from a first side (right side) of the top chip (13, exposed is interpreted to mean non-overlap of the portion of the bottom chip with the side of the top chip) and a second portion of the bottom chip (left side portion of 25) is exposed from a second side (left side surface of 13) of the top chip (13, see Figure 3I, nonoverlap is shown);
a second chip (4), bonded to the first portion (right end portion) of the bottom chip (25) exposed from the top chip (13, see Figure 3I) and to the bonding surface (upper surface of substrate 3) on a side of the chipset (13/25, right side), wherein the second chip (4), the bottom chip (25), the top chip (13), and the substrate (3) are electrically connected (see interconnects), and a projection of the second chip (4) and a projection of the bottom chip (25) on a projection plane parallel to the bonding surface (upper surface of substrate 3) partially overlap (see Figure 3I); and
a molding layer (16) covering and being in contact with a sidewall of the top chip (13, see Figure 3I), and covering and being in direct contact with a top surface of the second portion of the bottom chip (left side portion of 25, see upper surface in direct physical contact with the top surface of the second/left portion of the bottom chip 25) without being in contact with a lateral sidewall of the bottom chip (25, see at least the right lateral sidewall of 25 not being in direct contact with the molding layer 16).
Regarding claim 3, Beyne discloses wherein a first interconnecting structure (I/O contacts formed in opening 32 in Figure 3F, see para. [0054]) is formed in the bottom chip (25) exposed from the top chip (13), the first interconnecting structure (I/O contacts) is electrically connected to the top chip (13), and the second chip (4) bonded to the bottom chip (25) is electrically connected to the first interconnecting structure (I/O contacts, see para. [0052]).
Regarding claim 4, Beyne discloses wherein a second interconnecting structure (interconnects in bridge die connecting the I/O contacts to 7a electrodes, plus left side group of bumps 7b) extending through the bottom chip (the interconnects would extend through the chip laterally to access the other I/O contacts) is formed in the bottom chip (25, see para. [0051]-[0052], the interconnects in the bottom chip 25 are formed in the bottom chip), and the substrate (3) is electrically connected to the top chip (4) longitudinally adjacent to the bottom chip (25) by the second interconnecting structure (connected by the left side group of bumps 7b, which is part of the second interconnecting structure).
Regarding claim 8, Beyne discloses wherein:
the substrate (3) comprises a base and an interconnecting structure layer on the base (see para. [0053]),
a surface exposed from the interconnecting structure layer (exposed circuitry) is the bonding surface (upper surface of the substrate 3 that comprises the surfaces where circuitry is exposed), and the bottom chip (25) is electrically connected to the interconnecting structure layer (at least through bumps 7a/7b and the chip 4), and the second chip (4) is electrically connected to the interconnecting structure layer (through bumps 7b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Beyne as applied to claim 1 above, and further in view of Jeng et al. (“Jeng” US 2023/0352463).
Regarding claim 2, Beyne does not disclose a groove in the substrate.
However, Jeng discloses in Figure 7 a groove (recess 106) in the substrate (102) on a side of the bonding surface (upper surface of the substrate 102, see Figure 7), and the bottom chip (bridge die 78) is arranged in the groove (106, see Figure 7).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Jeng into the teachings of Beyne to include a groove in the substrate for the purpose of increasing high-density interconnections (see Jeng, para. [0012]).
Claims 5-7, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Beyne as applied to claim 1 above, and further in view of Chang et al. (“Chang” US 2021/0202336).
Regarding claim 5, Beyne teaches second conductive bumps (bumps 7a and right side group of bumps 7b), arranged between the second chip (4) and the bottom chip (25, see Figure 3I), and between the second chip (4) and the substrate (3), wherein the second conductive bumps (bumps 7a and right side group of bumps 7b) electrically connect the second chip (4) to the bottom chip (25, 7a portion) and electrically connect the second chip (4) to the substrate (3, 7b right side portion, see Figure 3I).
Beyne does not teach first conductive bumps as claimed.
Chang teaches in the embodiment of Figure 9:
first conductive bumps (17), arranged between the bottom chip (6) and the substrate (1), and electrically connecting the bottom chip (6) to the substrate (1, para. [0057]).
It would have been obvious to incorporate the teachings of Chang’s Figure 9 into Beyne to include the first conductive bumps between the bottom chip and the substrate, electrically connecting the two, to further increase interconnection density (Yang, see Figure 9, para. [0057]).
Regarding claim 6, the combination of Beyne and Chang teaches a sealing layer (11) arranged between the bottom chip (25) and the substrate (3, straight line drawn between an edge of the bottom chip 25 and the substrate intersects the sealing layer 11, thus the sealing layer 11 is therebetween) and between the second chip (4) and the substrate (3, see Figure 3I), and filling a gap between the top chip (13) and the second chip (4), a gap between adjacent first conductive bumps (as incorporated by Chang above), and a gap between adjacent second conductive bumps (see Figure 3I).
Regarding claim 7, Chang teaches a plurality of chipsets (see Figure 1), wherein the second chip (24) partially overlaps and is electrically connected to each of the bottom chips (376) of a plurality of adjacent chipsets (see interconnect structure of Figure 1 indicating the bottom chip, or the high density area of the substrate which corresponds to the bottom chip, which is vertically aligned with the bottom chip in Figure 9, showing overlap of bottom chip and second chip).
It would have been obvious to a person having ordinary skill in the art to incorporate the plurality of chipsets as taught by Chang into the teachings of Beyne for the purpose of increasing packaging density.
Regarding claim 11, Chang teaches in the embodiment of Figure 10:
a thermally conductive layer (48) arranged on the chipset (26/268 and 6) and a top of the second chip (24, see Figure 9).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Beyne to include a thermally conductive layer arranged on the chipset and a top surface of the second chip for the purpose of attaching a heat sink to the device for heat dissipation (Chang, para. [0059]).
Regarding claim 12, Chang further discloses in the embodiment of Figure 10:
a packaging housing (46) arranged on the substrate (1) and packaging the packaging structure (packaging structure 3).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Beyne to include a packaging housing arranged on the substrate and packaging the packaging structure for the purpose of heat dissipation (Chang, para. [0059]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Beyne as applied to claim 1 above and further in view of Chiang et al. (“Chiang” US 2020/0243449).
Regarding claim 9, Beyne teaches wherein… the top chip is a memory chip (13, memory stack), and the second chip (4) is a second logic chip (4, para. [0053]).
Beyne does not teach the bottom chip is a first logic chip, Beyne teaches that the bottom chip is an interconnection die.
Chiang teaches wherein the bottom chip (131) is a first logic chip (para. [0022]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chiang into the teachings of Beyne to include the bottom chip is a first logic chip because Chiang discloses that a bridge die may be any suitable die, such as a logic die (Chiang, para. [0022]).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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