DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 23, 2026, has been entered.
Claims 1-2, 7-8, 10-12, 17-18, and 20 are pending in this office action and presented for examination. Claims 1-2, 7, 11-12, and 17 are newly amended, and claims 9 and 19 are newly cancelled, by the response received March 23, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 7-8, 10-12, 17-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “sorting by the master processor” in line 16. However, it is indefinite as to whether this sorting is the same as, or different from, the “sort[ing]” recited in claim 1, line 14. If the same, antecedent basis language should be used for clarity.
Claim 1 recites the limitation “a last inserted item in the time-sequenced list” in lines 20-21. However, it is indefinite as to whether this limitation is intended to reflect a) an inserted item that is in a last position of the time-sequenced list, or b) an item that was most recently inserted into the time-sequenced list. With respect to possibility “a)”, note, for example, that claim 1, lines 24-26, may reflect a path through steps 94, 96, and 98 in Figure 7. Note that the limitation “the last inserted item in the time-sequenced list” is recited in claim 1, lines 23-24, and claim 1, lines 25-26.
Claims 2, 7-8, and 10 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 8 recites the limitation “The system of claim 1, wherein the master processor is configured to arrange subsequent input data entries, of the input data entries received from the plural slave processors, to be time-ordered” in lines 1-3. Claim 1, upon which claim 8 is dependent, recites, amongst other relevant limitations, “sort the input data entries in the first complete event log to form a second complete event log, wherein, after sorting by the master processor, all the respective timestamps in the second complete event log are chronologically consistent” in lines 14-17. As such, it is unclear as to whether claim 8 further limits the metes and bounds of claim 1 as would be necessary to be a proper dependent claim; if so, it is unclear as to how claim 8 further limits the metes and bounds of claim 1.
Claim 8 recites the limitation “the input data entries received from the plural slave processors” in lines 2-3. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 10 recites the limitation “The system of claim 1, wherein the master processor is configured to insert an individual input data entry from the input data entries received from the plural slave processors into the second complete event log” in lines 1-3. Claim 1, upon which claim 10 is dependent, recites, amongst other relevant limitations, “a master processor configured to: … sort the input data entries in the first complete event log to form a second complete event log … the master processor inserts the data item currently being processed by the master processor” in lines 5-23. As such, it is unclear as to whether claim 10 further limits the metes and bounds of claim 1 as would be necessary to be a proper dependent claim; if so, it is unclear as to how claim 10 further limits the metes and bounds of claim 1.
Claim 10 recites the limitation “The system of claim 1, wherein the master processor is configured to insert an individual input data entry from the input data entries received from the plural slave processors into the second complete event log” in lines 1-3. However, it is indefinite as to how an individual input data entry from the input data entries received from the plural slave processors can be “insert[ed]” “into” the second “complete” event log, as it is unclear as to how the second complete event log could be complete before the individual input data entry is inserted.
Claim 11 recites the limitation “sorting by the master processor” in line 14. However, it is indefinite as to whether this sorting is the same as, or different from, the sort[ing] recited in claim 11, line 12. If the same, antecedent basis language should be used for clarity.
Claim 11 recites the limitation “the sets together stored by the master processor” in lines 10-11. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 11 recites the limitation “a last inserted item in the time-sequenced list” in lines 18-19. However, it is indefinite as to whether this limitation is intended to reflect a) an inserted item that is in a last position of the time-sequenced list, or b) an item that was most recently inserted into the time-sequenced list. With respect to possibility “a)”, note, for example, that claim 11, lines 22-24, may reflect a path through steps 94, 96, and 98 in Figure 7. Note that the limitation “the last inserted item in the time-sequenced list” is recited in claim 11, lines 21-22, and claim 11, lines 23-24.
Claims 12, 17-18, and 20 are rejected for failing to alleviate the rejections of claim 11 above.
Claim 12 recites the limitation “the sorting” in line 1. However, it is indefinite as to whether the antecedent basis for this limitation is “sorting” in claim 11, line 12, or “sorting” in claim 11, line 14.
Claim 18 recites the limitation “The method of claim 11, wherein the master processor arranges subsequent input data entries, of the input data entries received from the plural slave processors, to be time-ordered” in lines 1-3. Claim 11, upon which claim 18 is dependent, recites, amongst other relevant limitations, “sorting at the master processor the input data entries in the first complete event log to form a second complete event log, wherein, after sorting by the master processor, all the respective timestamps in the second complete event log are chronologically consistent” in lines 12-15. As such, it is unclear as to whether claim 18 further limits the metes and bounds of claim 11 as would be necessary to be a proper dependent claim; if so, it is unclear as to how claim 18 further limits the metes and bounds of claim 11.
Claim 20 recites the limitation “The method of claim 11, further comprising inserting an individual input data entry from the input data entries received from the plural slave processors into the second complete event log” in lines 1-3. Claim 11, upon which claim 20 is dependent, recites, amongst other relevant limitations, “sorting at the master processor the input data entries in the first complete event log to form a second complete event log … the master processor inserts the data item currently being processed by the master processor” in lines 12-21. As such, it is unclear as to whether claim 20 further limits the metes and bounds of claim 11 as would be necessary to be a proper dependent claim; if so, it is unclear as to how claim 20 further limits the metes and bounds of claim 11.
Claim 20 recites the limitation “The method of claim 11, further comprising inserting an individual input data entry from the input data entries received from the plural slave processors into the second complete event log” in lines 1-3. However, it is indefinite as to how an individual input data entry from the input data entries received from the plural slave processors can be “insert[ed]” “into” the second “complete” event log, as it is unclear as to how the second complete event log could be complete before the individual input data entry is inserted.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 7-8, 10-12, 17-18, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See MPEP 2106.
Regarding Eligibility Step 1, each of the claims is directed to a process, machine, manufacture, or composition of matter.
Regarding Eligibility Step 2A, Prong One, each of the claims recites abstract ideas. Specifically, each of the claims recites mathematical concepts such as mathematical calculations and/or mental processes that can be performed in the human mind, or by a human using a pen and paper. For example, independent claim 11 recites separate event logs recording events and respective timestamps for when the events occurred; receiving the input data entries, the input data entries received including the respective timestamps of the events recorded; storing the received input data entries in a first complete event log, wherein the first complete event log comprises a plurality of sets of time-ordered data entries, the sets together comprising a partially time-ordered list of the input data entries; and sorting the input data entries in the first complete event log to form a second complete event log, wherein, after sorting, all the respective timestamps in the second complete event log are chronologically consistent, through iterations generating a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed and a last inserted item in the time-sequenced list, and based on the comparison, inserting the data item currently being processed into a first location immediately preceding the last inserted item in the time-sequenced list or inserting the data item currently being processed into a second location immediately following the last inserted item in the time-sequenced list.
Regarding the “plural slave processors” and “master processor”, Examiner notes that performing a mental process on a generic computer, performing a mental process in a computer environment, and using a computer as a tool to perform a mental process is still an abstract idea.
Regarding Eligibility Step 2A, Prong Two, the claim as a whole does not integrate the judicial exception into a practical application. In other words, the claim does not recite additional elements that integrate the judicial exception into a practical application. Regarding the “plural slave processors” and the “master processor”, Examiner notes that merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, or generally linking the use of a judicial exception to a particular technological environment or field of use, does not integrate a judicial exception into a practical application. Therefore, the claim is directed to the judicial exception.
Regarding Eligibility Step 2B, the claim does not recite additional elements that amount to an inventive concept. In other words, the claim does not recite additional elements that, individually or in combination, amount to significantly more than the judicial exception itself. Regarding the “plural slave processors” and the “master processor”, Examiner notes that merely adding the words "apply it" (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, or generally linking the use of a judicial exception to a particular technological environment or field of use, are not enough to qualify as "significantly more" when recited in a claim with a judicial exception. Examiner also notes that the courts have recognized receiving or transmitting data over a network, performing repetitive calculations, and storing and retrieving information in memory, as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. To any extent to which “plural slave” processors and a “master processor” are not encompassed by the previous mentions of, for example, a computer or computing environment, Examiner takes official notice of the well-understood, routine, conventional nature of “plural slave” processors. For example, USPC 712/31 and G06F9/3877 are directed to master/slave processors. (Also see FIG. 5 of Lieber-Dembo et al. (US 20210141602 A1), for example.) Examiner notes that the dependent claims do not add limitations that integrate the judicial exception into a practical application or amount to significantly more than the judicial exception recited in the independent claim. For example, the dependent claims merely further limit the abstract idea of sorting.
Therefore, the claims are not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 10-12, 17-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farrell et al. (Farrell) (US 20030163275 A1) in view of Uppala et al. (Uppala) (US 20090077078 A1) and Bentley (Programming Pearls Second Edition).
Consider claim 1, Farrell discloses a system for event logging (FIG. 2; [0019], line 14, event logging) and sorting (see FIG. 2, where error log 52 is sorted by time) of input data entries (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information), comprising: plural slave processors ([0020], lines 13-14, a microprocessor contained in each module) each having separate event logs recording events and respective timestamps for when the events occurred (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information); and a master processor ([0015], lines 26-29, controller 12 may periodically poll the modules and sub-modules for error or operational data. Alternatively, controller 12 may receive and record data transmitted from the various modules or sub-modules in real time) configured to: receive the input data entries from each of the plural slave processors (FIG. 2; [0015], lines 26-29, controller 12 may periodically poll the modules and sub-modules for error or operational data. Alternatively, controller 12 may receive and record data transmitted from the various modules or sub-modules in real time); the input data entries received from each of the plural slave processors including the respective timestamps of the events recorded by each of the plural slave processors (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information); the input data entries received from each of the plural slave processors including the respective time stamps comprise a plurality of sets of time-ordered data entries, the sets together comprising a partially time-ordered list of the input data entries (see FIG. 2), and sort the input data entries to form a second complete event log, wherein, after sorting by the master processor, all the respective timestamps in the second complete event log are chronologically consistent (see FIG. 2, where error log 52 is sorted by time).
Farrell does not explicitly disclose the master processor is configured to: store the input data entries in a first complete event log, wherein the first complete event log comprises the aforementioned plurality of sets of time-ordered data entries. Farrell also does not explicitly disclose that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list.
On the other hand, Uppala discloses storing input data entries, wherein the stored input data entries comprises a plurality of sets of ordered data entries, the sets together comprising a partially ordered list of the input data entries, prior to sorting the input data entries ([0022], lines 8-11, sorting a working table 108 results in merging sorted key records into a sorted results table 120. In another embodiment, a working table 108 may itself be reordered in-place so as not to create a new table within memory; FIG. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Uppala with the invention of Farrell in order to facilitate the sorting of data. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Farrell as cited above, including the master processor, input data entries, plurality of time-ordered data entries, and sorting, and Uppala’s teaching of storing input data prior to sorting that input data) according to known methods (Examiner submits that the concept of a processor storing data before operating on that data is well known) to yield predictable results (the invention of Farrell, wherein the master processor is configured to: store the input data entries received from each of the plural slave processors including the respective timestamps in a first complete event log, wherein the first complete event log stored by the master processor comprises a plurality of sets of time-ordered data entries, the sets together comprising a partially time-ordered list of the input data entries, and sort the input data entries in the first complete event log to form the second complete event log), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not explicitly entail that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list.
On the other hand, Bentley explicitly discloses the well-known concept of sorting via iterations of insertion into a proper relative position (page 115, section 11.1, Insertion Sort, lines 1-3, Insertion Sort is the method most card players use to sort their cards. They keep the cards dealt so far in sorted order, and as each new card arrives they insert it into its proper relative position). Examiner further submits that sorting via iterations of insertion into a proper relative position entails, for example, a comparison and an insertion of a data item currently being processed into a location immediately preceding or immediately following a last inserted item.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bentley with the combination of Farrell and Uppala in order to implement the sorting of the combination of Farrell and Uppala in a simple and straightforward manner. Note that Bentley’s teaching cited above, when applied to the combination of Farrell and Uppala (which entails, for example, the master processor, first complete event log, second complete event log, and input data entries including respective timestamps), results in the overall claimed limitation that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Farrell and Uppala as cited above, including the master processor, first complete event log, second complete event log, and input data entries including respective timestamps, and Bentley's teaching of sorting via iterations of insertion into a proper relative position) according to known methods (Examiner submits that sorting via iterations of insertion into a proper relative position is known, as reflected by Bentley) to yield predictable results (the combination of Farrell and Uppala, implementing the cited sorting of Bentley, such that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, the overall combination entails the system of claim 1 (see above), wherein the master processor is configured to place a subsequent input data entry ahead of prior input data entries received from the plural slave processors when the subsequent input data entry has a timestamp earlier than timestamps of the prior input data entries (Farrell, FIG. 2; also see Uppala, FIG. 1; also see Bentley, page 115, section 11.1, Insertion Sort, lines 1-3).
Consider claim 7, the overall combination entails the system of claim 1 (see above), wherein the master processor merges all of the respective timestamps received from each of the plural slave processors from storage event logs recorded by the plural slave processors (Farrell, FIG. 2; also see Uppala, FIG. 1).
Consider claim 8, the overall combination entails the system of claim 1 (see above), wherein the master processor is configured to arrange subsequent input data entries, of the input data entries received from the plural slave processors, to be time-ordered (Farrell, FIG. 2; also see Uppala, FIG. 1).
Consider claim 10, the overall combination entails the system of claim 1 (see above), wherein the master processor is configured to insert an individual input data entry from the input data entries received from the plural slave processors into the second complete event log (Farrell, FIG. 2; also see Uppala, FIG. 1; also see Bentley, page 115, section 11.1, Insertion Sort, lines 1-3).
Consider claim 11, Farrell discloses a method for event logging (FIG. 2; [0019], line 14, event logging) and sorting (see FIG. 2, where error log 52 is sorted by time) input data entries (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information), comprising: at a master processor ([0015], lines 26-29, controller 12 may periodically poll the modules and sub-modules for error or operational data. Alternatively, controller 12 may receive and record data transmitted from the various modules or sub-modules in real time), receiving the input data entries (FIG. 2; [0015], lines 26-29, controller 12 may periodically poll the modules and sub-modules for error or operational data. Alternatively, controller 12 may receive and record data transmitted from the various modules or sub-modules in real time) from plural slave processors ([0020], lines 13-14, a microprocessor contained in each module) each having separate event logs recording events and respective timestamps for when the events occurred (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information), the input data entries received from each of the plural slave processors including the respective timestamps of the events recorded by the plural slave processors (FIG. 2; [0019], line 6, error codes and associated run time stamps; [0019], line 8, similar information); the input data entries received from each of the plural slave processors including the respective timestamps comprise a plurality of sets of time-ordered data entries, the sets together stored by the master processor comprising a partially time-ordered list of the input data entries (see FIG. 2), and sorting at the master processor the input data entries to form a second complete event log, wherein, after sorting by the master processor, all the respective timestamps in the second complete event log are chronologically consistent (see FIG. 2, where error log 52 is sorted by time).
Farrell does not explicitly disclose storing at the master processor the input data entries in a first complete event log, wherein the first complete event log comprises the aforementioned plurality of sets of time-ordered data entries. Farrell also does not explicitly disclose that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list.
On the other hand, Uppala discloses storing input data entries, wherein the stored input data entries comprises a plurality of sets of ordered data entries, the sets together comprising a partially ordered list of the input data entries, prior to sorting the input data entries ([0022], lines 8-11, sorting a working table 108 results in merging sorted key records into a sorted results table 120. In another embodiment, a working table 108 may itself be reordered in-place so as not to create a new table within memory; FIG. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Uppala with the invention of Farrell in order to facilitate the sorting of data. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Farrell as cited above, including the master processor, input data entries, plurality of time-ordered data entries, and sorting, and Uppala’s teaching of storing input data prior to sorting that input data) according to known methods (Examiner submits that the concept of a processor storing data before operating on that data is well known) to yield predictable results (the invention of Farrell, further entailing storing at the master processor the input data entries in a first complete event log, wherein the first complete event log comprises a plurality of sets of time-ordered data entries, each set of the time-ordered data entries received from one of the plural slave processors, the sets together comprising a partially time-ordered list of the input data entries, and sorting at the master processor the input data entries in the first complete event log), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the prior art combination thus far does not explicitly entail that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list.
On the other hand, Bentley explicitly discloses the well-known concept of sorting via iterations of insertion into a proper relative position (page 115, section 11.1, Insertion Sort, lines 1-3, Insertion Sort is the method most card players use to sort their cards. They keep the cards dealt so far in sorted order, and as each new card arrives they insert it into its proper relative position). Examiner further submits that sorting via iterations of insertion into a proper relative position entails, for example, a comparison and an insertion of a data item currently being processed into a location immediately preceding or immediately following a last inserted item.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bentley with the combination of Farrell and Uppala in order to implement the sorting of the combination of Farrell and Uppala in a simple and straightforward manner. Note that Bentley’s teaching cited above, when applied to the combination of Farrell and Uppala (which entails, for example, the master processor, first complete event log, second complete event log, and input data entries including respective timestamps), results in the overall claimed limitation that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Farrell and Uppala as cited above, including the master processor, first complete event log, second complete event log, and input data entries including respective timestamps, and Bentley's teaching of sorting via iterations of insertion into a proper relative position) according to known methods (Examiner submits that sorting via iterations of insertion into a proper relative position is known, as reflected by Bentley) to yield predictable results (the combination of Farrell and Uppala, implementing the cited sorting of Bentley, such that the master processor through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list, and based on the comparison, the master processor inserts the data item currently being processed by the master processor into a first location immediately preceding the last inserted item in the time-sequenced list or inserts the data item currently being processed by the master processor into a second location immediately following the last inserted item in the time-sequenced list), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 12, the overall combination entails the method of claim 11 (see above), wherein the sorting places a subsequent input data entry ahead of prior input data entries received from the plural slave processors when the subsequent input data entry has a timestamp earlier than timestamps of the prior input data entries (Farrell, FIG. 2; also see Uppala, FIG. 1; also see Bentley, page 115, section 11.1, Insertion Sort, lines 1-3).
Consider claim 17, the overall combination entails the method of claim 11 (see above), further comprising merging all of the respective timestamps received from each of the plural slave processors from storage event logs recorded by the plural slave processors (Farrell, FIG. 2; also see Uppala, FIG. 1).
Consider claim 18, the overall combination entails the method of claim 11 (see above), wherein the master processor arranges subsequent input data entries, of the input data entries received from the plural slave processors, to be time-ordered (Farrell, FIG. 2; also see Uppala, FIG. 1).
Consider claim 20, the overall combination entails the method of claim 11 (see above), further comprising inserting an individual input data entry from the input data entries received from the plural slave processors into the second complete event log (Farrell, FIG. 2; also see Uppala, FIG. 1; also see Bentley, page 115, section 11.1, Insertion Sort, lines 1-3).
Response to Arguments
Applicant on page 13 argues: “Hence, the foregoing 35 U.S.C. § 112(b) rejections should be removed.”
In view of the aforementioned amendments, the previously presented indefinite rejections are withdrawn.
Applicant on page 15 argues: “Here, the amended claims set forth positive steps for the master processor that are more than intended use and are more than that which the human mind is equipped to perform and cannot, as a practical matter, be performed entirely in a human's mind. The human mind can not entirely have a first complete event log or a plurality of sets of time-ordered data entries stored by the master processor. Nor can the human mind entirely have a master processor sort the input data entries in the first complete event log to form a second complete event log. Nor can the human mind entirely through iterations generates a time-sequenced list for the second complete event log based on a comparison between the respective timestamps of a data item from the first complete event log currently being processed by the master processor and a last inserted item in the time-sequenced list.”
However, Examiner submits that sorting can be performed in the human mind, or by a human using a pen and paper. Moreover, regarding Applicant’s mention of a master processor, Examiner notes that performing a mental process on a generic computer, performing a mental process in a computer environment, and using a computer as a tool to perform a mental process is still an abstract idea.
Applicant on page 16 argues: “Furthermore, the claims now clarify that the second complete event log sorted by the master processor is formed inserting at least once a data entry currently being processed by the master processor into either a first location immediately preceding a first input data entry in the first complete event log or a second location immediately following the first input data entry, based on a comparison between the respective timestamps of the data entry currently being processed by the master processor to the first input data entry in the first complete event log. It is this attribute from Applicant's description of the inventive algorithm of FIG. 7 which contributes to the improvement evidenced by the Experimental Results shown in Applicant's FIGs. 8A and 8B.”
However, MPEP 2106.05(a) conveys that an improvement in the abstract idea itself is not an improvement in technology, and the recited master processor (which is recited to perform the abstract idea of sorting) merely appears to be a generic computer component. Instant paragraph [0013] discloses “FIG. 7 is a flow chart of the inventive sorting algorithm”, and Applicant cites further paragraphs [0034], [0036], and [0037] referring to “the inventive algorithm of FIG. 7”; Examiner submits this disclosure reflects the improvement being to the abstract idea of sorting.
Applicant on page 17 argues: “Here, Applicant has demonstrated an improvement in the functioning of a computer when the inventive algorithm of FIG. 7 used.”
However, MPEP 2106.05(a) conveys that an improvement in the abstract idea itself is not an improvement in technology, and the recited master processor (which is recited to perform the abstract idea of sorting) merely appears to be a generic computer component. Instant paragraph [0013] discloses “FIG. 7 is a flow chart of the inventive sorting algorithm”, and Applicant cites further paragraphs [0034], [0036], and [0037] referring to “the inventive algorithm of FIG. 7”; Examiner submits this disclosure reflects the improvement being to the abstract idea of sorting.
Applicant on page 21 argues: ‘Here, Applicant submits that the claimed elements noted above would have to be shown by the Office to be "widely prevalent and its combination with any other additional elements is well understood, routine, conventional activity" or else the 35 U.S.C. §101 rejection should be withdrawn. Yet, from the art of record (requiring a combination of references to meet that previously claimed) and from the lack of the evidentiary requirements set forth in MPEP 2106.07(a) III being advanced for that previously claimed, it does not appear to be the case that the evidentiary requirements could be met for the elements now presently claimed defining subject matter further from the applied art and at the inventive concept.’
However, Examiner submits that the entirety of the claimed elements (e.g., the abstract idea) does not have to be shown by the Office to be "widely prevalent and its combination with any other additional elements is well understood, routine, conventional activity" for the rejection under 35 U.S.C. §101 to be proper.
Applicant on page 21 argues: “Here, the specific steps recite in the claims are more than data gathering and define a non-conventional and non-generic arrangement of subject matter not present in the applied art, thereby representing an inventive concept.”
However, the rejection under 35 U.S.C. §101 is not based on an assertion that all of the steps recited in the claims are data gathering steps.
Applicant on page 25 argues: ‘Yet, the teachings in the art which the Office relied on for teaching "sorting" do not describe that presently claimed.’
In view of the newly amended claims, Examiner is newly relying upon Bentley in the rejections of the independent claims — see the Claim Rejections - 35 USC § 103 section above.
Applicant on page 29 argues “Accordingly, the sorting in Uppala is a re-ordering of column records, and does not imply or suggest a re-ordering based on respective time stamps, as presently defined in claims 1 and 11. Nor does Uppala provide any detail on the particulars of how "Qsort" sorts the column records to form the far-right table in FIG. 1.”
Examiner generally notes that Farrell was relied upon to teach timestamp subject matter.
Applicant on page 29 argues: “Hence, a combination of Farrel and Uppala would not disclose or suggest: … Thus, the rejection of claims 1-2, 7-8, 10-12, 17-18, and 20 under 35 U.S.C. §103 as allegedly being unpatentable over Farrell in view of Uppala should be removed, and these claims should be passed to allowance.”
In view of the newly amended claims, Examiner is newly relying upon Bentley in the rejections of the independent claims — see the Claim Rejections - 35 USC § 103 section above.
Applicant on page 30 argues: “Thus, claims 9 and 19 (for their dependence from independent claim 1 or independent claim 11) should be passed to allowance.”
However, claims 9 and 19 are currently cancelled.
Conclusion
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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