DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on December 5th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on December 5th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 7-8, with respect to the rejections of claims under 35 U.S.C 102 (a)(2) have been fully considered but they are not persuasive in view of the following reasons.
Applicant argues that Na fails to teach that the top interconnect layer and the conductive plug are integrally formed, as recited in amended claim 1 (see Applicant’s argument and pg. 7-8). The examiner respectfully disagrees because the term “integrally formed” only means elements/features are joined together as single complete unit. Na discloses the conductive plug (via 150) and the top interconnect layer (layer 162) integrally and continuously attached together as a whole structure of the same material (see Fig. 1 and [0040], [0047], [0049]). Therefore, the conductive plug (via 150 and the top interconnect layer (layer 162) are integrally formed.
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since 1 is directed to a device, the method of forming the top interconnect layer and the conductive plug is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…integrally formed” stated in claim 1 has not been given any patentable weight. MPEP 2113 [R-1].
In view of the foregoing reasons, the examiner believes that all Applicant's arguments and remarks are addressed. The examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NA et al. (Pub. No.: US 2022/0399229 A1), hereinafter as Na.
Regarding claim 1, Na discloses a semiconductor structure in Fig. 1, comprising: a substrate (substrate 100) (see [0028]); a bottom dielectric layer (layer 110), located on the substrate (see [0030]); a bottom interconnect layer (layer 122), located in the bottom dielectric layer (see [0032]); a top dielectric layer (layer 140), located on the bottom dielectric layer and the bottom interconnect layer (see [0038]); a conductive plug (via 150), located in the top dielectric layer on a top of the bottom interconnect layer and having a bottom in direct contact with the bottom interconnect layer and a sidewall in direct contact with the top dielectric layer (see Fig. 1 and [0039]); a top interconnect layer (layer 162), located in the top dielectric layer above the conductive plug and in contact with the conductive plug (see [0042]); wherein the top interconnect layer and the conductive plug are integrally formed (via 150 and layer 162 are continuously and integrally attached as a whole structure of the same material) (see Fig. 1 and [0040], [0047], [0049]); and a top adhesion layer (layer 161), located between the top interconnect layer and the top dielectric layer (see Fig. 1 and [0042-0043]).
Note: it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since 1 is directed to a device, the method of forming the top interconnect layer and the conductive plug is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…integrally formed” stated in claim 1 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 2, Na discloses the semiconductor structure according to claim 1, further comprising: a bottom adhesion layer (layer 121), located between the bottom interconnect layer and the bottom dielectric layer (see Fig. 1 and [0033]).
Regarding claim 3, Na discloses the semiconductor structure according to claim 2, wherein a material of the bottom adhesion layer comprises at least one of tantalum, tantalum nitride, titanium and titanium nitride (see [0033]).
Regarding claim 4, Na discloses the semiconductor structure according to claim 1, further comprising: an etch stop layer (etch stop layer 130), located between the bottom dielectric layer (layer 110) and the top dielectric layer (layer 140) and between the bottom interconnect layer (layer 122) and the top dielectric layer (layer 140) (see Fig. 1 and [0037]); wherein the conductive plug (via 150) further extends through the etch stop layer (see Fig. 1).
Regarding claim 5, Na discloses the semiconductor structure according to claim 4, wherein a material of the etch stop layer comprises at least one of silicon nitride, silicon carbide (see [0036]).
Regarding claim 7, Na discloses the semiconductor structure according to claim 1, wherein a material of the top adhesion layer (layer 161) comprises at least one of tantalum nitride, titanium, or titanium nitride (see [0046]).
Regarding claim 8, Na discloses the semiconductor structure according to claim 1, wherein: a material of the bottom interconnect layer (material of layer 122) comprises at least one of Co, W, Ru, Al, Ir, Rh, Cu, Pt, or Ti (see [0034]); a material of the top interconnect layer (material of layer 162) comprises at least one of Co, W, Ru, Al, Ir, Rh, Cu, Pt, Ta, or Ti (see [0049]); a material of the bottom dielectric layer (material of layer 110) comprises at least one of a low-k dielectric material, an ultra low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride (see [0030]); a material of the top dielectric layer (material of layer 140) comprises at least one of a low-k dielectric material, an ultra low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride (see [0037]); and a material of the conductive plug (material of via 150) comprises at least one of of Co, W, Ru, Al, Ir, Rh, Cu, Pt, Ta, or Ti (see [0040]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Prosecution Insights