Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's amendment/arguments filed on 1/15/26 as being acknowledged and entered. By this amendment claims 5-7 and 21-24 are canceled, claims 25-27 have been added and claims 1-4, 8-20, and 25-27 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US PGPub 2020/0343307.
Claim 15: Lee teaches (Fig. 4) an electronic system, comprising: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, wherein: the semiconductor device includes: a gate stack structure including alternately stacked insulating patterns (33) and conductive patterns (Wn); a memory channel structure (40) extending through the gate stack structure; and a bit line pad (63) on the memory channel structure, the memory channel structure includes a variable resistance layer (44A/B), a channel layer (43A/B) surrounding the variable resistance layer, and a channel insulating layer (42A/B) surrounding the channel layer, the insulating patterns include an uppermost insulating pattern at an uppermost portion of the gate stack structure, and a level of a top surface of the variable resistance layer, a level of a top surface of the channel layer, and a level of a top surface of the channel insulating layer are each higher than a level of a top surface of the uppermost insulating pattern. Lee does not teach the top surfaces of the variable resistance layer, channel layer, and the channel insulating layer are coplanar. As evidenced by the prior art listed in the PTO-892, teach the top surfaces of the variable resistance layer, channel layer, and the channel insulating layer being coplanar is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the tops to be coplanar as it is a common feature in the art.
Claim 16: Lee teaches (Fig. 4) the semiconductor device further includes a cover insulating layer (52, 53) covering the gate stack structure, the memory channel structure, and the bit line pad; and a level of a bottom surface of the cover insulating layer is lower than the level of the top surface of the variable resistance layer, is lower than the level of the top surface of the channel layer, and is lower than the level of the top surface of the channel insulating layer. The claims does not describe how the cover insulating layer covers the bit line pad. It currently covers the side surface.
Claim 17: Lee teaches (Fig. 4) the channel insulating layer has a surface contacting a side wall of the cover insulating layer.
Claim 18: Lee teaches (Fig. 4) the surface of the channel insulating layer is coplanar with a side wall of the bit line pad.
Claim 19: Lee teaches (Fig. 4) the surface of the channel insulating layer interconnects a side wall and the top surface of the channel insulating layer.
Claim 20: Lee teaches (Fig. 4) the memory channel structure is spaced apart from the cover insulating layer.
Claim 26: Lee teaches (Fig. 4) wherein the bit line pad contacts the variable resistance layer, channel layer and the channel insulating layer. The claim does not required direct physical contact. The references in the prior art listing also teach this claim limitation.
Allowable Subject Matter
Claims 1-4 and 8-14 are allowed. The prior art of record does not teach the claim amendments presented in claims 1 and 8.
Claims 25 and 27 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814