DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/12/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 12 and 19 are objected to because of the following informalities:
Claim 12 recites “different logic levels each other” in lines 7 and 8. The examiner suggests “different from each other”.
Claim 19 recites “different logic levels each other” in lines 7 and 8. The examiner suggests “different from each other”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0365593) in view of Ko (US 2014/0313845).
Regarding claim 1.
Chen teaches a stacked integrated circuit comprising: an upper chip (fig 4d:61; [para 0046]) that is rotated around a rotation axis and stacked on a lower chip (fig 4d:62; [para 0046]) in a mirror symmetric structure form (fig 4e:64; [para 0048]), wherein the lower chip (fig 4d:62; [para 0046]) and the upper chip (fig 4d:61; [para 0046]) are stacked in a front and front connection structure form (fig 4e:64; [para 0048]).
Chen does not teach the details of the internal circuitry configuration.
Ko teaches the upper chip (fig 4: 240; [para 0048]) configured to generate a first internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0050]) based on a distinguishment signal (fig 4:UP_slice<0:1>; [para 0050]), the upper chip (fig 4: 240; [para 0048]) configured to generate a first input and output (input/output) control signal (fig 4:dec_slice<0:3>; [para 0050]) for an input/output of a power signal based on the first internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0050]) and a chip selection signal (fig 4: CS#_SEL; [para 0050]), the lower chip (fig 4:230; [para 0048]) configured to generate a second internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0050]) based on a reset signal, and the lower chip (fig 4:230; [para 0048]) configured to generate a second input/output control signal (fig 4: DEC_Slice<0:3>; [para 0050]) for the input/output of the power signal based on the second internal distinguishment signal (fig 4:ID_SLICE<0:1>; [para 0050]) and the chip selection signal (fig 4: CS#_SEL; [para 0049,0050]).
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It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention for the input and output of the stacked chips to be controlled based on a distinguishment signal so that the data stored in each chip can be distinctly and specifically fetched, further by providing particular configuration to the die the die can be enabled to perform functions such as testing (Ko paragraph 8).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0365593) in view of Ko (US 2014/0313845)
Regarding claim 11,
Chen discloses a stacked integrated circuit comprising: an upper chip (fig 4d:61; [para 0046]) that is rotated around a rotation axis and stacked on a lower chip (fig 4d:62; [para 0046]) in a mirror symmetric structure (fig 4e:64; [para 0048]) form, wherein the lower chip (fig 4e:62; [para 0046]) and the upper chip (fig 4e:61; [para 0046]) are stacked in a front and front connection structure form (fig 4e:64; [para 0048]), and each of the lower chip (fig 4e:62) and the upper chip (fig 4e:61) is configured […] ([para 0029]).
Chen does not teach the details of configuration.
Ko teaches each of a lower chip (fig 4:230; [para 0048]) and the upper chip (fig 4:240; [para 0048]) is configured to control an input of a first power signal (fig 4:239; [para 0049]) and a second power signal (fig 4:249; [para 0049]) based on an internal distinguishment signal (fig 4:ID_slice<0:1>; [para 0050]) and an input and output (input/output) control signal (fig 4:DEC_slice<0:3> ; [para 0050], chip selection signal CS# combined with unique identifier to control the input and output of the chip).
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It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention for the input and output of the stacked chips to be controlled based on a distinguishment signal so that the data stored in each chip can be distinctly and specifically fetched, further by providing particular configuration to the die the die can be enabled to perform functions such as testing (Ko paragraph 8).
Regarding claim 12, Chen in view of Ko discloses the stacked integrated circuit of claim 11, further:
Ko teaches the internal distinguishment signal (fig4:ID_slice<0:1>; [para 0050]) comprises a first internal distinguishment signal (fig 4:id_slice; [para 0050]) that is generated (fig 4:241; [para 0050]) from the upper chip (fig 4:240; [para 0050]) and a second internal distinguishment signal (fig 4:ID_slice<0:1>; [para 0050]) that is generated (fig 4:231; [para 0050]) from the lower chip (fig 4:230; [para 0050]), and logic levels (fig 3,<0:1>; [para 0060]) of the first internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0060]) and the second internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0060]) are generated to have different logic levels each other (unique ID; [para 0050,0060]).
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0365593) in view of Ko (US 2014/0313845)
Regarding claim 18, Chen discloses a stacked integrated circuit (fig 4I; [para 0053]) comprising: an upper chip (fig 4e:61; [para 0048]) that is rotated around a rotation axis and stacked (fig 4e; [para 0048]) on a lower chip (fig 4e:62; [para 0048]) in a mirror symmetric structure form (fig 4d,e:64; [para 0043]), wherein the lower chip (fig 4e:62) and the upper chip (fig 4e:61) are stacked in a front and front connection structure form (fig 4d,4e; [para 0048]), and each of the lower chip (fig 4e:62) and the upper chip (fig 4e:61) is configured […]; ([para 0029]).
Chen does not teach the details of configuration,
Ko teaches each of a lower chip (fig 4:230; [para 0048]) and the upper chip (fig 4:240; [para 0048]) is configured to control an output of a first power signal (fig 4:239; [para 0049]) and a second power signal (fig 4:unit 249; [para 0049]) based on an internal distinguishment signal (fig 4:ID_slice<0,1>; [para 0050]) and an input and output (input/output) control signal (fig 4:DEC_SLICE<0:3>; [para 0050], chip selection signal CS# combined with unique identifier to control the input and output of the chip) (see also annotated fig 4).
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It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention for the input and output of the stacked chips to be controlled based on a distinguishment signal so that the data stored in each chip can be distinctly and specifically fetched, further by providing particular configuration to the die the die can be enabled to perform functions such as testing (Ko paragraph 8).
Regarding claim 19, Chen in view of Ko teaches the stacked integrated circuit of claim 18, further:
Ko teaches the internal distinguishment signal (fig 4:id_slice<0,1>; [para 0050]) comprises a first internal distinguishment signal (fig 4:id_slice<0,1> in chip 240; [para 0050]) that is generated from the upper chip (fig 4:240) and a second internal distinguishment signal (fig 4:id_slice<0,1> in chip 230; [para 0050]) that is generated from the lower chip (fig 4:230), and logic levels of the first internal distinguishment signal and the second internal distinguishment signal (fig 4:id_slice<0,1>; [para 0050]) are generated ([para 0064]) to have different logic levels from each other (unique ID; [para 0050,0060]) (see also annotated fig 4).
Allowable Subject Matter
Claims 2 through 10, 13 through 17 and 20 through 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art does not teach a stacked integrated circuit comprising: an upper chip that is rotated around a rotation axis and stacked on a lower chip in a mirror symmetric structure form, and the lower chip configured to generate a second input/output control signal for the input/output of the power signal based on the second internal distinguishment signal and the chip selection signal, the upper chip comprises: a first rear pad configured to receive the distinguishment signal; and a second rear pad configured to receive the chip selection signal in combination with other elements of the claim.
Regarding claim 13, the prior art does not teach a stacked integrated circuit comprising: an upper chip that is rotated around a rotation axis and stacked on a lower chip in a mirror symmetric structure form, and each of the lower chip and the upper chip is configured to control an input of a first power signal and a second power signal based on an internal distinguishment signal and an input and output (input/output) control signal, and the first input/output control signal and the second input/output control signal are selectively activated in response to a chip selection signal in combination with other elements of the claim.
Regarding claim 20, the prior art does not teach, a stacked integrated circuit comprising: an upper chip that is rotated around a rotation axis and stacked on a lower chip in a mirror symmetric structure form, and the upper chip is configured to control an output of a first power signal and a second power signal based on an internal distinguishment signal and an input and output (input/output) control signal, the input/output control signal comprises a first input/output control signal that is generated from the upper chip and a second input/output control signal that is generated from the lower chip, and the first input/output control signal and the second input/output control signal are selectively activated in response to a chip selection signal.
Prior Art
Listing of relevant prior art: Lee (US 2020/0303030), Lee (US 12438126)
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 26, 2026