DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 16/949,270 fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. With regards to independent claims 1 and 12, the disclosure of Application No. 16/949,270 does not teach a method comprising “converting each design in a first set of a plurality of designs from a first non-pixelized format to a second pixelized-format; converting description of DRC violations in each of the designs from the first non-pixelized format to the second pixelized-format; and using the second pixelized formats for the design and the DRC violations to train the machine-trained network to identify DRC violations in a subsequent second set of designs that are provided as input to the machine-trained network in the second pixelized format.” The dependent claims do not rectify this deficiency. Accordingly, claims 1-20 are not entitled to the benefit of the prior application. Therefore the priority date for the instant application is 19 January 2022.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-15, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tien et al., US PGPUB No. 2020/0134131.
Regarding Claim 1, Tien discloses a method for training a machine-trained network (test pattern machine learning circuitry 140 of test pattern generation tool 32 and/or test pattern generation circuitry 132) to perform design rule checks on designs comprising a plurality of shapes (Fig. 1 & 2; [0014], 'Embodiments provided herein include systems and methods for
generating test patterns which may be used for early assessments of lithographic or other semiconductor manufacturing processes, including, for example, for testing design rule check (DRC) features of an electronic device platform"; [0027], 'the verification tool 28 may perform a design rule check (DRC) to determine whether the electronic device design, including the geometric shapes, the locations of the geometric shapes, or the interconnections between the geometric shapes assigned by the placement tool 24 or the routing tool 26, satisfies the design rules, as may be defined by a semiconductor foundry or semiconductor technology node for fabricating the electronic device'; [0028], 'the test pattern generation platform 30 is configured to generate test patterns which may be used to validate the design rules (e.g., the DRC deck) that are implemented by the verification tool 28'; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations)'; [0039], 'The test pattern generation circuitry 132 analyzes the received noise image, and generates a test pattern based on the analyzed noise image. For example, the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations.'; [0053], 'FIG. 3 is a flow chart 300 illustrating a method of training the discriminator 144 of the test pattern machine learning circuitry 140, in accordance with one or more embodiments'), the method comprising:
converting each design in a first set of a plurality of designs (training data 150) from a first non-pixelized format to a second pixelized-format (Fig. 1-3; [0015], 'The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes.'; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations).' [0055], 'At 302, a plurality of layout clips is provided for training the discriminator 144. The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips at 302 may include valid layout clips 351 for electronic device designs which are known to be free of DRC violations, as well as invalid layout clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations. The layout clips 351, 352 may be pre-classified and labeled layout clips for training of the discriminator 144. For example, the valid layout clips 351 may be labeled as "valid" and the invalid layout clips 352 may be labeled as "invalid" so that the discriminator 144 may learn to classify received input as valid or invalid based on the training.'; [0056], 'At 304, the valid and invalid layout clips 351, 352 are rasterized to generate rasterized images 360. The rasterized images 360 may be generated, for example, by the rasterization circuitry 134 previously described herein. For example, the rasterization circuitry 134 may receive the layout clips 351, 352 as image data described in a vector graphics format (which may be provided, for example, as GDS files or the like), and may convert them into raster images, or a series of pixels, dots or lines, which, when displayed together, create the image which was represented via the shapes'; a vector image [non-pixelated] input can be converted into a raster image [pixelated], which may include the labels pertaining to the DRC violations as part of the rastered images);
converting description of DRC violations in each of the designs from the first non-pixelized format to the second pixelized-format (Fig. 1-3; [0015], 'The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes."; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations).'; [0055], 'At 302, a plurality of layout clips is provided for training the discriminator 144. The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips at 302 may include valid layout clips 351 for electronic device designs which are known to be free of DRC violations, as well as invalid layout clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations. The layout clips 351, 352 may be pre-classified and labeled layout clips for training of the discriminator 144. For example, the valid layout clips 351 may be labeled as "valid" and the invalid layout clips 352 may be labeled as "invalid" so that the discriminator 144 may learn to classify received input as valid or invalid based on the training."; [0056], 'At 304, the valid and invalid layout clips 351, 352 are rasterized to generate rasterized images 360. The rasterized images 360 may be generated, for example, by the rasterization circuitry 134 previously described herein. For example, the rasterization circuitry 134 may receive the layout clips 351, 352 as image data described in a vector graphics format (which may be provided, for example, as GDS files or the like), and may convert them into raster images, or a series of pixels, dots or lines, which, when displayed together, create the image which was represented via the shapes'; a vector image [non-pixelated] input can be converted into a raster image [pixelated], which may include the labels pertaining to the DRC violations as part of the rastered images); and
using the second pixelized formats for the design and the DRC violations to train the machine-trained network (140) to identify DRC violations in a subsequent second set of designs (noise input 120) that are provided as input to the machine-trained network (140) in the second pixelized format (Fig. 1-3; [0015], 'The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes."; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations).'; [0037], 'the noise input 120 may be provided from a noise input database, which may store a plurality of random noise vectors which may be sequentially or randomly accessed for generation of test patterns, for example, by the test pattern generation circuitry 132.'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; [0055], ‘At 302, a plurality of layout clips is provided for training the discriminator 144. The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips at 302 may include valid layout clips 351 for electronic device designs which are known to be free of DRC violations, as well as invalid layout clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations. The layout clips 351, 352 may be pre-classified and labeled layout clips for training of the discriminator 144. For example, the valid layout clips 351 may be labeled as "valid" and the invalid layout clips 352 may be labeled as "invalid" so that the discriminator 144 may learn to classify received input as valid or Invalid based on the training."; [0056], 'At 304, the valid and invalid layout clips 351, 352 are rasterized to generate rasterized images 360. The rasterized images 360 may be generated, for example, by the rasterization circuitry 134 previously described herein. For example, the rasterization circuitry 134 may receive the layout clips 351, 352 as image data described in a vector graphics format (which may be provided, for example, as GDS files or the like), and may convert them into raster images, or a series of pixels, dots or lines, which, when displayed together, create the image which was represented via the shapes'; a vector image [non-pixelated] input can be converted into a raster image [pixelated], which may include the labels pertaining to the DRC violations as part of the rastered images for use as training data 150; the neural network can be used to process test layouts [designs] for DRC violations).
Regarding Claim 2, Tien discloses the method of claim 1 further comprising identifying DRC violations in each design in the first set of designs (training data 150 having invalid layout clips 352; Fig. 2; [0055], 'The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips at 302 may include invalid layout
clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations'; in some instances, only invalid layout clips 352
may be used).
Regarding Claim 3, Tien discloses the method of claim 2, wherein identifying DRC violations comprises using a geometric-based DRC tool (verification tool 28) to identify the DRC violations (Fig. 1; [0026], 'The verification tool 28 may perform various verifications or checks on an electronic device layout, e.g., after placement and routing. The verification tool 28 verifies that the electronic device design, including the layout of the cells or geometric shapes provided by the placement tool 24, as well as the interconnections between the cells or geometric shapes provided by the routing tool 26, satisfies one or more specifications, rules, or the like associated with the electronic device design'; [0027], 'the verification tool 28 may perform a design rule check (DRC) to determine whether the electronic device design, including the geometric shapes, the locations of the geometric shapes, or the interconnections between the geometric shapes assigned by the placement tool 24 or the routing tool 26, satisfies the design rules, as may be defined by a semiconductor foundry or semiconductor technology node for fabricating the electronic device. The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design.').
Regarding Claim 7, Tien discloses the method of claim 1 further comprising generating at least a subset of designs in the first set of designs (Fig. 1-3; [0055], 'At 302, a plurality of layout clips is provided for training the discriminator 144.The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips
at 302 may include valid layout clips 351 for electronic device designs which are known to be free of DRC violations, as well as invalid layout clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations. The layout clips 351, 352 may be pre-classified and labeled layout clips for training of the discriminator 144'; layout clips may be a subset of the training data 150 and includes valid layout clips 351 and invalid layout clips 352).
Regarding Claim 8, Tien discloses the method of claim 8, wherein said generating comprises generating each design in the subset of designs to include portions with DRC violations and portions with no DRC violations (Fig. 1-3; [0055], 'At 302, a plurality of layout clips is provided for training the discriminator 144. The layout clips may be provided as training data 150, as previously described with respect to FIG. 2. For example, the layout clips at 302 may include valid layout clips 351 for electronic device designs which are known to be free of DRC violations, as well as invalid layout clips 352 for electronic device designs which are known to include one or more DRC violations. The invalid layout clips 352 may be layout clips including hotspots or other circuit defects which may be identified as DRC violations. The layout clips 351, 352 may be pre-classified and labeled layout clips for training of the discriminator 144'; layout clips may be a subset of the training data 150 and includes valid layout clips 351 and invalid layout clips 352).
Regarding Claim 9, Tien discloses the method of claim 1, wherein the first set of designs (150) comprise a subset of designs that are manufactured designs produced after a set of manufacturing operations are performed on an earlier third set of designs produced by a set of electronic design automation tools (one or more tools 22, 24, 26, 28 of electronic design platform 20; Fig. 2; [0014], "Embodiments provided herein include systems and methods for generating test patterns which may be used for early assessments of lithographic or other semiconductor manufacturing processes, including, for example, for testing design rule check (DRC) features of an electronic device platform'; [0019], 'The electronic design platform 20 includes electronic device design tools which can be used, for example, to design high-level programming descriptions of analog and/or digital circuitry for an electronic device the electronic design platform 20 may include various additional features and functionalities, including, for example, one or more tools suitable to simulate, analyze, and/or verify the high-level programming descriptions of circuitry for the electronic device.'; [0020], 'the electronic design platform 20 includes a synthesis tool 22, a placement tool 24, a routing tool 26, and a verification tool 28, each of which may be implemented at least in part as software tools accessible to and executable by one or more computing devices, processors or the like.'; [0026], 'The verification tool 28 may perform a physical verification, in which the verification tool 28 verifies whether an electronic device design is physically manufacturable, and that the resulting chips will meet the design specifications and will not have physical defects which prevent the chips from functioning as designed."; [0032], 'the test pattern generation platform 30 may receive training input in the form of layout clips from the electronic design platform 20 after DRC checking has been performed, for example, by the verification tool 28. The test pattern generation platform 30 may implement a machine-learning approach to learn to generate test patterns which conform to design rules for any particular electronic device design, device category, or lithographic or other semiconductor manufacturing process, based on the training of the test pattern generation platform 30. For example, the test pattern generation tool 32 may receive the training data in the form of layout clips from the electronic design platform 20, and the test pattern generation tool 32 may implement a machine-learning approach to generate, based on another input (which may be a random noise vector, in some embodiments), test patterns that represent layout clips that conform to the design rules'; simulation of manufacturing processes can be used to create training data input 150 based upon earlier designs [third set of designs] that have be produced using one or more tools 22, 24, 26, 28 that verify the manufacturability of said earlier designs).
Regarding Claim 10, Tien discloses the method of 9, wherein at least one design in the subset of designs is produced by a manufacturing process simulation software (part of electronic design platform 20; Fig. 2; [0014], 'Embodiments provided herein include systems and methods for generating test patterns which may be used for early assessments of lithographic or other semiconductor manufacturing processes, including, for example, for testing design rule check (DRC) features of an electronic device platform'; [0019], 'The electronic design platform 20 includes electronic device design tools which can be used, for example, to design high-level programming descriptions of analog and/or digital circuitry for an electronic device, the electronic design platform 20 may include various additional features and functionalities, including, for example, one or more tools suitable to simulate, analyze, and/or verify the high-level programming descriptions of circuitry for the electronic device.'; [0020], 'the electronic design platform 20 includes a synthesis tool 22, a placement tool 24, a routing tool 26, and a verification tool 28, each of which may be implemented at least in part as software tools accessible to and executable by one or more computing devices, processors or the like.'; [0026], 'The verification tool 28 may perform a physical verification, in which the verification tool 28 verifies whether an electronic device design is physically manufacturable, and that the resulting chips will meet the design specifications and will not have physical defects which prevent the chips from functioning as designed."; [0032], 'the test pattern generation platform 30 may receive training input in the form of layout clips from the electronic design platform 20 after DRC checking has been performed, for example, by the verification tool 28'; simulation of manufacturing processes can be used to create training data input for one or more designs).
Regarding Claim 11, Taiwan Semiconductor Manufacturing discloses the method of claim 9, wherein at least one design in the subset of designs is produced by another machine-trained network (Fig. 1 & 2; [0032], 'The test pattern generation platform 30 may implement
a machine-learning approach to learn to generate test patterns which conform to design rules for any particular electronic device design, device category, or lithographic or other semiconductor manufacturing process, based on the training of the test pattern generation platform 30. For example, the test pattern generation tool 32 may receive the training data in the form of layout clips from the electronic design platform 20, and the test pattern generation tool 32 may implement a machine-learning approach to generate, based on another input (which may be a random noise vector, in some embodiments), test patterns that represent layout clips that conform to the design rules'; [0034], 'FIG. 2 is a block diagram illustrating a test pattern generation system 100, in accordance with embodiments of the present disclosure. The test pattern generation system 100 may be used in conjunction with, and may include one or more of the features and functionality of, the test pattern generation platform 30 shown in FIG. 1'; [0039], 'the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations."; machine learning from one or more neural networks can be used to generate designs to be used as training data input 150).
Regarding Claim 12, Tien discloses the method of claim 22, wherein the machine-trained networks are neural networks (Fig. 1 & 2; [0032], 'The test pattern generation platform 30 may implement a machine-learning approach to learn to generate test patterns which conform to design rules for any particular electronic device design, device category, or lithographic or other semiconductor manufacturing process, based on the training of the test pattern generation platform 30. For example, the test pattern generation tool 32 may receive the training data in the form of layout clips from the electronic design platform 20, and the test pattern generation tool 32 may implement a machine-learning approach to generate, based on another input (which may be a random noise vector, in some embodiments), test patterns that represent layout clips that conform to the design rules'; [0034], 'FIG. 2 is a block diagram illustrating a test pattern generation system 100, in accordance with embodiments of the present disclosure. The test pattern generation system 100 may be used in conjunction with, and may include one or more of the features and functionality of, the test pattern generation platform 30 shown in FIG. 1'; [0039], 'the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations.'; machine learning from one or more neural networks can be used to generate designs to be used as training data input 150).
With regards to claims 13-15 and 19-20 drawn to a non-transitory machine-readable medium containing all of the same functional limitations as found in claims 1-3 and 7-8 as addressed above, the same rejections apply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 5, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al., US PGPUB No. 2020/0134131 in view of Yu et al., US PGPUB No. 2016/0125120.
Regarding Claim 4, Tien discloses the method of claim 3. They fail to explicitly disclose wherein the geometric-based DRC tool is a 1-D edge-based tool. Yu is in the field of design rule checking (Title and Abstract) and teaches wherein a geometric-based DRC tool is a 1-D edge-based tool (Fig. 1 shows the framework for DRC detection; Fig. 2 shows checking edges placement, making sure they are correctly positioned in the given dimension [1-D]; [0054], 'Referring to block 70, for a single layer, a width rule specifies the minimum width 71 of any polygon in the layout, while a spacing rule specifies the minimum distance 72 between two neighboring polygons. For two layers, an enclosure rule specifies a polygon should be covered with some additional margin 73 by some polygon on the other layer. These design rules can be expressed by equations and/or inequalities. For example, the minimum spacing rule can be described as the spacing between any two adjacent polygon edges is smaller than the spacing 72. These rules are applied during DRC, for example, by checking the widths and spacing of each block structure of user's layout pattern 90-1, and reporting the location of each block structure whose width is less than minimum width 71, and each pair of block structures whose edge-to-edge spacing is less than minimum distance 72. In addition to the three fundamental rules, modern DRC tools can perform general dimensional checks within a single polygon
(including length, width, area, overlap, ratio, and density calculations) or between polygon edges (including intersecting polygon spacings, enclosure spacings, and external polygon spacings). Given a runset file (i.e., the design rules provided to the DRC tool to be checked during a DRC session) and a layout, a DRC tool reports each location that a rule is violated.'). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the edge tool of Yu for because it would ensure the layout is dimensionally correct about the various edges, thereby reporting any determinations of violations (Yu; [0054]).
Regarding Claim 5, Tien discloses the method of claim 3. They fail to explicitly disclose wherein the geometric-based DRC tool is an equation-based tool. Yu is in the field of design rule checking (Title and Abstract) and teaches wherein the geometric-based DRC tool is an equation-based tool (Fig. 1 shows the framework for DRC detection; [0054], 'Referring to block 70, for a single layer, a width rule specifies the minimum width 71 of any polygon in the layout, while a spacing rule specifies the minimum distance 72 between two neighboring polygons. For two layers, an enclosure rule specifies a polygon should be covered with some additional margin 73 by some polygon on the other layer. These design rules can be expressed by equations and/or inequalities. For example, the minimum spacing rule can be described as the spacing between any two adjacent polygon edges is smaller than the spacing 72. These rules are applied during DRC, for example, by checking the widths and spacing of each block structure of user's layout pattern 90-1, and reporting the location of each block structure whose width is less than minimum width 71, and each pair of block structures whose edge-to-edge spacing is less than minimum distance 72. In addition to the three fundamental rules, modern DRC tools can perform general dimensional checks within a single polygon (including length, width, area, overlap, ratio, and density calculations) or between polygon edges (including intersecting polygon spacings, enclosure spacings, and external polygon spacings). Given a runset file (i.e., the design rules provided to the DRC tool to be checked during a DRC session) and a layout, a DRC tool reports each location that a rule is violated.'; the equation-based design rules are built into the tool). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the equation-based tool of Yu because it would ensure the layout is dimensionally correct according to the equations, thereby reporting any determinations of violations (Yu; [0054]).
With regards to claims 16 and 17 drawn to a non-transitory machine-readable medium containing all of the same functional limitations as found in claims 4 and 5 as addressed above, the same rejections apply.
Claim(s) 6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al., US PGPUB No. 2020/0134131 in view of Cecil, US PGPUB No. 2020/0387660.
Regarding Claim 6, Tien discloses the method of claim 14. They fail to explicitly disclose wherein the geometric-based DRC tool is based on a circle-tracing method. Cecil is in the field of design rule checking ([0052]) and teaches wherein a geometric-based DRC tool is based on a circle-tracing method ([0056], 'Therefore, the system according to various embodiments, checks the mask and fixes any MRC violations that are found.'; [0121], 'FIG. 11 illustrates the parameters for geometric shapes with circular corners according to an embodiment. The mask rule checking system 200 may scale these parameters by a factor to introduce some allowance so that shapes that are substantially circular will be permitted but shapes that are too different from circular shapes will be flagged as mask rule violations."; [0139], "Descriptions at each level of abstraction are enabled for use by the corresponding tools of that layer (e.g., a formal verification tool). A design process may use a sequence depicted in FIG. 16. The processes described by be enabled by EDA products (or tools).'). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the circle-tracing tool of Cecil for because it would perform checking the design based upon the rules, thereby identifying any violations that need to be corrected (Cecil; [0121], [0139]).
With regards to claims 18 drawn to a non-transitory machine-readable medium containing all of the same functional limitations as found in claims 6 as addressed above, the same rejections apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.B/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851