DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 16/949,270 fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. With regards to independent claims 1 and 12, the disclosure of Application No. 16/949,270 does not teach a method comprising “using the second description [of the design in a second pixelated format] to provide input to a machine-trained network to process in order to identify a DRC violation in the design; and based on output produced by the machine-trained network, identifying DRC violations in the design.” The dependent claims do not rectify this deficiency. Accordingly, claims 1-20 are not entitled to the benefit of the prior application. Therefore the priority date for the instant application is 19 January 2022.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 9, 12-15, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tien et al., US PGPUB No. 2020/0134131.
Regarding Claim 1, Tien teaches a method for performing design rule checking (DRC) on a design comprising a plurality of shapes (Fig. 1; [0014], Embodiments provided herein include systems and methods for generating test patterns which may be used for early assessments of lithographic or other semiconductor manufacturing processes, including, for example, for testing design rule check (DRC) features of an electronic device platform'; [0027], 'the verification tool 28 may perform a design rule check (DRC) to determine whether the electronic device design, including the geometric shapes, the locations of the geometric shapes, or the interconnections between the geometric shapes assigned by the placement tool 24 or the routing tool 26, satisfies the design rules, as may be defined by a semiconductor foundry or semiconductor technology node for fabricating the electronic device'), the method comprising:
receiving a first description of the design (noise input 120) in a first non-pixelized format (Fig. 1 & 2; [0015], 'The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes.'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; a vector image [non-pixelated] input can be converted into a raster image [pixelated] in order to be input into circuitry for processing the design with regards to DRC violations);
producing, from the first description, a second description of the design in a second pixelized format (Fig. 1 & 2; [0015], "The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes."; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; a vector image [non-pixelated] input can be converted into a raster image [pixelated] in order to be input into circuitry for processing the design with regards to DRC violations);
using the second description to provide input to a machine-trained network (test pattern machine learning circuitry 140 of test pattern generation tool 32 and/or test pattern generation circuitry 132) to process in order to identify a DRC violation in the design (Fig. 1 & 2; [0027], 'The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design."; [0028], 'the test pattern generation platform 30 is configured to generate test patterns which may be used to validate the design rules (e.g., the DRC deck) that are implemented by the verification tool 28'; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations)'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; [0039], "The test pattern generation circuitry 132 analyzes the received noise image, and generates a test pattern based on the analyzed noise image. For example, the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations.'); and
based on output produced by the machine-trained network (140), identifying DRC violations in the design (Fig. 1 & 2; [0027], 'The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design.'; [0028], 'the test pattern generation platform 30 is configured to generate test patterns which may be used to validate the design rules (e.g., the DRC deck) that are implemented by the verification tool 28'; [0048], 'On the other hand, the DRC check circuitry 136 may be operable to check for DRC violations in any layout clip, including layout clips generated by the electronic design platform 20 as previously described with respect to FIG. 1, as well as layout clips (e.g., test layouts or test patterns) that are generated by the test pattern generation circuitry 132 based on the generated pattern images. The DRC check circuitry 136 may be substantially the same as the DRC checking tool of the verification tool 28 as previously described. In some embodiments, the DRC check circuitry 136 may be the same as the DRC checking tool of the verification tool 28 of the electronic design platform 20 described with respect to FIG. 1.').
Regarding Claim 2, Tien teaches wherein the DRC violations are initially expressed in a pixel-based format ([0033], 'the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on inpút training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations). The DRC validation tool 34 may be communicatively coupled to a DRC checking tool, such as a DRC checking tool within the verification tool 28, and may be utilized to test the test patterns generated by the test pattern generation tool 32 in order to confirm that the DRC checking tool is properly functioning to implement the actual specified design rules, or to confirm whether the design rules should be modified'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes.'; determination of DRC violations can occur on rasterized images, which are pixel-based images),
the method further comprising generating, for the identified DRC violations that are specified in the pixel-based format, contoured shapes to display with the design, and displaying the design with the contoured shapes in order to identify locations in the design that have DRC violations ([0027], 'the verification tool 28 may perform a design rule check (DRC) to determine whether the electronic device design, including the geometric shapes, the locations of the geometric shapes, or the interconnections between the geometric shapes assigned by the placement tool 24 or the routing tool 26, satisfies the design rules, as may be defined by a semiconductor foundry or semiconductor technology node for fabricating the electronic device. The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design.'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes'; the contoured shapes represent the outlines of the shapes that provide and display the identified locations with DRC violations).
Regarding Claim 3, Tien teaches the method of claim 2, wherein the contoured shapes are displayed along with the design by a geometry-based design editing or visualization tool (verification tool 28; Fig. 1; [0026], The verification tool 28 may perform various verifications or checks on an electronic device layout, e.g., after placement and routing. The verification tool 28 verifies that the electronic device design, including the layout of the cells or geometric shapes provided by the placement tool 24, as well as the interconnections between the cells or geometric shapes provided by the routing tool 26, satisfies one or more specifications, rules, or the like associated with the electronic device design'; [0027], 'the verification tool 28 may perform a design rule check (DRC) to determine whether the electronic device design, including the geometric shapes, the locations of the geometric shapes, or the interconnections between the geometric shapes assigned by the placement tool 24 or the routing tool 26, satisfies the design rules, as may be defined by a semiconductor foundry or semiconductor technology node for fabricating the electronic device. The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design."; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes'; the contoured shapes represent the outlines of the shapes that provide and display the identified locations with DRC violations).
Regarding Claim 4, Tien teaches the method of claim 1, wherein the machine-trained network (140) is a neural network (Fig. 1 & 2; [0039], 'The test pattern generation circuitry 132 analyzes the received noise image, and generates a test pattern based on the analyzed noise image. For example, the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations."; [0046], Once the neural networks of the test pattern machine learning circuitry 140 (e.g., neural networks of the generator 142 and the discriminator 144) have been sufficiently trained, the neural network of the generator 142 may be provided with non-training data (e.g., the noise input 120 after rasterization by the rasterization circuitry 134) at the input layer'; [0047], 'The pattern images may be generated by the test pattern generation circuitry 132, for example, by accessing one or more neural networks of the test pattern machine learning circuitry 140 to generate the pattern images based on the rasterized noise input 120').
Regarding Claim 7, Tien teaches the method of claim 1; wherein said producing comprises using the first description to rasterize the design to obtain the second pixelized format in which pixel values are used to describe the design (Fig. 1 & 2; [0015], The electronic device design system 10 is operable to generate test patterns (which may be referred to herein as test layouts or test layout clips) for early assessments of lithographic or other semiconductor manufacturing processes."; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; a vector image [non-pixelated] input can be converted into a raster image [pixelated] in order to be input into circuitry for processing the design with regards to DRC violations).
Regarding Claim 9, Tien teaches the method of claim 1, wherein the machine-trained network (140) implements a DRC checking process (Fig. 1 & 2; [0027], 'The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design.'; [0028], 'the test pattern generation platform 30 is configured to generate test patterns which may be used to validate the design rules (e.g., the DRC deck) that are implemented by the verification tool 28'; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations)'; [0038], Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; [0039], The test pattern generation circuitry 132 analyzes the received noise image, and generates a test pattern based on the analyzed noise image. For example, the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning mode! (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations.').
In reference to claims 12-15, drawn to a non-transitory machine-readable medium containing all of the same functional limitations as found in claims 1-4, the same rejections apply.
With regards to claim 18, Tien teaches wherein the machine-trained network produces a single output representative of design violations for a single design rule ([0150] ‘the DRC check circuitry 136 may identify one or more DRC violations in the generated layout clips, and in some embodiments, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to fix such identified DRC violations in the generated layout clips. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to apply one or more design rules to adjust the arrangement of geometric shapes in the generated layout clip. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to adjust a spacing between one or more of the geometric shapes, to reduce or increase a width of one or more of the geometric shapes, or the like, so that the arrangement of the geometric shapes of the generated layout clip is made to conform to the specified design rules’ For the instant claim, one DRC violation is considered a single output representative of design violations for a single design rule).
With regards to claim 19, Tien teaches wherein the machine-trained network produces multiple outputs representative of design violations for multiple design rules ([0150] ‘the DRC check circuitry 136 may identify one or more DRC violations in the generated layout clips, and in some embodiments, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to fix such identified DRC violations in the generated layout clips. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to apply one or more design rules to adjust the arrangement of geometric shapes in the generated layout clip. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to adjust a spacing between one or more of the geometric shapes, to reduce or increase a width of one or more of the geometric shapes, or the like, so that the arrangement of the geometric shapes of the generated layout clip is made to conform to the specified design rules’ For the instant claim, “or more DRC violations” is considered multiple outputs representative of design violations for multiple design rules).
With regards to claim 20, Tien teaches wherein the multiple design rules comprise at least two of DRC rule constraints regarding widths of shapes, DRC rule constraints regarding spacing between two shapes, and DRC rule constraints regarding an amount by which one shape encloses another ([0150] ‘the DRC check circuitry 136 may identify one or more DRC violations in the generated layout clips, and in some embodiments, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to fix such identified DRC violations in the generated layout clips. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to apply one or more design rules to adjust the arrangement of geometric shapes in the generated layout clip. For example, the DRC check circuitry 136 or the test pattern generation circuitry 132 may be configured to adjust a spacing between one or more of the geometric shapes, to reduce or increase a width of one or more of the geometric shapes, or the like, so that the arrangement of the geometric shapes of the generated layout clip is made to conform to the specified design rules’).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5-6 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al., US PGPUB No. 2020/0134131 in view of Gheith et al., US PGPUB No. 2020/0380089.
Regarding Claim 5, Tien teaches the method of claim 1. They do not teach wherein the shapes comprise rectilinear shapes and curvilinear shapes. Gheith is in the field of semiconductor structure design (Title and Abstract) and teaches wherein shapes comprise rectilinear shapes and curvilinear shapes (Fig. 1; [0004], 'For example, under the Manhattanization technique, curved features are treated by breaking them down into vertical and horizontal edge fragments, e.g., a staircase shaped. These rigid shapes generated by the Manhattanization technique can cause design rule check (DRC) violations and OPC challenges for the masks used in silicon photonics manufacturing'; [0015], 'For example, Manhattanizing curvilinear designs creates rigid shapes, e.g., staircase shaped short edges, which can cause a lot of design rule checks (DRC) and OPC concerns in silicon photonics manufacturing'; [0020], 'curvilinear test patterns are any patterns which comprise curved shapes in addition to simple linear shapes. In this way, the test patterns are rectilinear shapes and curvilinear shapes.'). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the rectilinear shapes and curvilinear shapes of Gheith for the purpose of designing a semiconductor, because it would be using a structure that will pass the design rule checks for manufacturing (Gheith; [0004], [0015]).
Regarding Claim 6, Tien in view of Gheith teaches the method of claim 5. Tein alone further fails to teach wherein each rectilinear shape is formed by Manhattan edges, each curvilinear shape is formed by at least one curvilinear edge, and the shapes further comprise shapes with at least one non-Manhattan rectilinear edge that has a 45-degree angle or another angle other than 0, 45, or 90. Gheith is in the field of semiconductor structure design (Title and Abstract) and teaches wherein each rectilinear shape is formed by Manhattan edges, each curvilinear shape is formed by at least one curvilinear edge (Fig. 1; [0004], 'For example, under the Manhattanization technique, curved features are treated by breaking them down into vertical and horizontal edge fragments, e.g., a staircase shaped. These rigid shapes generated by the Manhattanization technique can cause design rule check (DRC) violations and, OPC challenges for the masks used in silicon photonics manufacturing'; [0015], 'For example, Manhattanizing curvilinear designs creates rigid shapes; e.g., staircase shaped short edges, which can cause a lot of design rule checks (DRC) and OPC concerns in silicon photonics manufacturing'; [0020], 'curvilinear test patterns are any patterns which comprise curved shapes in addition to simple linear shapes. In this way, the test patterns are rectilinear shapes and curvilinear shapes.'). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was made to use at least one non-Manhattan rectilinear edge that has a 45-degree angle or another angle other than 0, 45, or 90, since where the general conditions of the claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. The motivation for doing so would have been to avoid the problems of most Manhattan shapes that cause issues when placed through a design rule check (Gheith [0004], [0015]).
In reference to claims 16-17, drawn to a non-transitory machine-readable medium containing all of the same functional limitations as found in claims 1, 5, and 6, the same rejections apply.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al., US PGPUB No. 2020/0134131 in view of Poonawala et al., US PGPUB No. 2021/0181620.
Regarding Claim 8, Tien teaches the method of claim 7. They fail to explicitly disclose wherein the first description comprises a description of shapes as polygons. Poonawala is in the field of using machine learning for rule checking ([0077]) and teaches wherein the first description comprises a description of shapes as polygons ([0034], 'The polygon data is first converted to a rasterized pixel grid so that convolutional neural networks can be used in subsequent steps. This is merely an example, and methods for creating an encoded data set can be used, for example taking a lithographic simulation of the polygons and extracting geometric/pixel information from that.'; [0047], 'the ML training service can transform the polygon to a pixelized domain using rasterization (e.g., as discussed further below). Alternatively, or in addition, pixelized representations of polygons can be generated by first converting the polygons to a skeleton representation, and then converting the skeleton representation to pixelized data (e.g., focusing on the axis of the mask polygons). This is illustrated further below with regard to FIG. 9F.'; [0077], 'This post processing could be any combination of rule-based correction, model-based edge perturbations, application of additional ML models, etc'; the first data can be polygons that are converted to a second, pixel-based data). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the polygons of Poonawala because using polygons is a common design platform used for manufacturing (Poonawala [0006], [0008], [0027]).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al., US PGPUB No. 2020/0134131 in view of Baidya et al., US PGPUB No. 2019/0385300.
Regarding Claim 10, Tien teaches the method of claim 1, wherein the machine-trained network implements a DRC checking process (Fig. 1 & 2; [0027], 'The verification tool 28 may determine the presence of one or more DRC violations in the electronic device design, and in some embodiments, the verification tool 28 may generate information indicating locations of the one or more DRC violations in the electronic device design.'; [0028], 'the test pattern generation platform 30 is configured to generate test patterns which may be used to validate the design rules (e.g., the DRC deck) that are implemented by the verification tool 28'; [0033], 'As will be described in further detail below, in some embodiments, the test pattern generation tool 32 may include machine learning circuitry 140 which may be trained to generate the test patterns based on input training data 150 (e.g., labeled layout clips which have been previously checked by a DRC checking tool and which are known to be free of DRC violations or to include one or more DRC violations)'; [0038], 'Rasterization generally refers to a task of converting an image described in a vector graphics format (e.g., the noise input 120, which may be representative of shapes of a random image) and converting it into a raster image, which may be a series of pixels, dots or lines, which, when displayed together, create the image that was represented via shapes. The rasterized image (e.g., the noise image) may then be processed by the test pattern generation circuitry 132 and used to generate test patterns.'; [0039], 'The test pattern generation circuitry 132 analyzes the received noise image, and generates a test pattern based on the analyzed noise image. For example, the test pattern generation circuitry 132 may generate the test pattern by accessing a machine learning model (which may be one or more neural networks stored or implemented, for example, by the test pattern machine learning circuitry 140) that is trained with past data in the form of layout clips for electronic device designs which are known to be free of DRC violations, as well as layout clips for electronic device designs which are known to include one or more DRC violations.'). Tien fails to explicitly disclose wherein the machine-trained network partially implements a DRC checking process along with a pixel-based process. Baidya is in the field of design rule checking (Title and Abstract) and teaches wherein a machine-trained network partially implements a DRC checking process along with a pixel-based process ([0034], 'During the design process, patterns of a chip may be checked against design rule constraints, such as those described above, to determine whether the patterns are clean patterns (e.g., patterns that comply with all design rules) or dirty patterns (e.g., patterns that violate one or more design rules). Ensuring that all of the patterns of a design meet the design rules may requires weeks of manual work by circuit designers, as the designers modify the layout of the dirty patterns to conform with the design rules'; [0043], 'pattern information may comprise (or include data based on) an image constructed according to the design of the pattern as indicated by a portion of a layout database file. In particular embodiments, the image may include different colors for different materials of the chip so as to distinguish between the various layers of the chip'; [0057], 'The patterns corresponding to the morphed images may be checked to determine whether they are valid'; [0058], 'the morphing may include changing the shape or size of polygons within the dirty pattern'; [0059], 'the morphing techniques may be used in conjunction with the design rules or other parameters specifying allowable values for the geometric shapes that are morphed'; [0066], 'Since a human user may prefer certain types of changes to the input pattern (i.e., the dirty pattern) over other types of changes, various embodiments provide an interface for one or more users to select from a set of morphed patterns. Furthermore, the user preferences can be used to train a machine learning model (e.g., a neural net, support vector machine, or other suitable machine learning model) that influences the identification of similar patterns at 512 for future iterations of the flow (e.g., for other dirty patterns) and/or the selection of the closest morphed patterns at 516 by selecting patterns that are more likely to be preferred by users'; {pg. 11 of the PCT specification describes a morphological image processing process as being a pixel-based process}; therefore, the image morphing described may be a pixel-based process to be used with a machine learning process for DRC purposes). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tien with the pixel-based process of Baidya because it would improve the performing of a design rules check, thereby identifying any violations to be corrected (Baidya [0040]-[0041], [0059]).
Regarding Claim 11, Tien in view of Baidya discloses the method of claim 10. Tien fails to explicitly disclose wherein the pixel-based process comprises a morphological image processing process. Baidya is in the field of design rule checking (Title and Abstract) and teaches wherein the pixel-based process comprises a morphological image processing process ([0034], 'During the design process, patterns of a chip may be checked against design rule constraints, such as those described above, to determine whether the patterns are clean patterns (e.g., patterns that comply with all design rules) or dirty patterns (e.g., patterns that violate one or more design rules). Ensuring that all of the patterns of a design meet the design rules may requires weeks of manual work by circuit designers, as the designers modify the layout of the dirty patterns to conform with the design rules'; [0043], pattern information may comprise (or include data based on) an image constructed according to the design of the pattern as indicated by a portion of a layout database file. In particular embodiments, the image may include different colors for different materials of the chip so as to distinguish between the various layers of the chip'; [0057], 'The patterns corresponding to the morphed images may be checked to determine whether they are valid'; [0058], 'the morphing may include changing the shape or size of polygons within the dirty pattern'; [0059], 'the morphing techniques may be used in conjunction with the design rules or other parameters specifying allowable values for the geometric shapes that are morphed'; [0066], 'Since a human user may prefer certain types of changes to the input pattern (i.e., the dirty pattern) over other types of changes, various embodiments provide an interface for one or more users to select from a set of morphed patterns. Furthermore, the user preferences can be used to train a machine learning model (e.g., a neural net, support vector machine, or other suitable machine learning model) that influences the identification of similar patterns at 512 for future iterations of the flow (e.g., for other dirty patterns) and/or the selection of the closest morphed patterns at 516 by selecting patterns that are more likely to be preferred by users'; (pg. 11 of the PCT specification describes a morphological image processing process as being a pixel-based process); therefore, the image morphing described may be a pixel-based process to be used with a machine learning process for DRC purposes). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Tian with the morphological image processing process of Baidya because it would improve the performing of a design rules check, thereby identifying any violations to be corrected (Baidya [0040]-[0041], [0059]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.B/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851