DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7.2.2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the elements listed below must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Elements not shown:
- From claim 6, “the interface region is in contact with a doping region formed in the semiconductor substrate” is not shown.
- From claim 7, “metallization structures above the metal nitride layer” is not shown.
- From claim 8, “wherein the metal nitride layer and the metallization structures provide a backside metallization of the semiconductor device” is not shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 3-4 and 20, the claims appear to include silicon nitride as a “metal nitride layer” which is indefinite because silicon is not a metal and silicon nitride is not a metal nitride; the claims are treated as presented.
Regarding claim 4, “Si-3N4 and Al3N4” appear to be both dielectrics. First, it is unclear what metal nitride is “Al3N4” since the common formula for Aluminum Nitride is AlN. And second, it is unclear if dielectrics such as those claim would result in the claimed Nitrogen concentration difference.
Furthermore, the specification discloses “The present disclosure generally relates to semiconductor devices comprising a metal nitride layer as a metallization structure for Ohmic contacts to a semiconductor substrate” ([0002] of published application hereinafter) and “Further embodiments pertain to methods of producing semiconductor devices comprising a metal nitride layer for Ohmic contact formation” ([0002]) wherein it is clear the intent of the specification is to form ohmic contacts; it is unclear if the claimed dielectrics are capable of forming ohmic contacts.
No prior art is applied to the claim since it cannot be determined if the dielectrics claimed are capable of leading to the claimed Nitrogen concentration difference and if they can lead to ohmic contacts per the specification. Note that inconsistencies between claims and the specification can be the basis for an indefiniteness rejection per MPEP 2173.03.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hoshino et al. (JP 3439597 B2).
Regarding claim 1, Hoshino discloses a semiconductor device (Fig. 1), comprising:
a semiconductor substrate (1, “n-type SiC single crystal substrate 1”); and
a (MPEP 2111) metal nitride (comprising) (multi)layer (2-3, “TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers”) above the semiconductor substrate, wherein (MPEP 2111):
an interface region (IR) of the semiconductor device comprises:
a first portion of the semiconductor substrate (R1s);
a first portion (R1m which is ½ of the total thickness of 2 per MPEP 2111) of the metal nitride (comprising) (multi)layer (2-3); and
an interface (I) between the first portion of the semiconductor substrate (R1s) and the first portion of the metal nitride layer (R1m);
the interface region extends into the metal nitride layer (2/3) not more than 20 nanometers (nm) (per MPEP 2111, IR is selected to end a ½ the thickness of layer 2 which has “a thickness of 30 nm”; ½ of that being 15nm); and
a (one of many) concentration of nitrogen content at the first portion of the metal nitride layer (R1m) is higher than a concentration of nitrogen content at a second portion (3), of the metal nitride (comprising) (multi)layer(2-3), outside the interface region (IR, “TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers” implies that R1m has a higher N concentration than 3).
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Regarding claims 2-3 and 5-6, Hoshino discloses (claim 2) wherein the semiconductor substrate comprises at least one of silicon carbide (SiC), gallium nitride (GaN), or Si (silicon) (“n-type SiC single crystal substrate 1”), (claim 3) wherein the metal nitride layer (2-3) comprises at least one of Ti (titanium), Si (silicon), Al (aluminum), W (tungsten), Ta (tantalum), or Mo (molybdenum) (“TiN layer 2”), (claim 5) wherein the interface region (IR) extends into the metal nitride layer (2-3) not more than 15 nanometers (nm) (per MPEP 2111, IR is selected to end a ½ the thickness of layer 2 which has “a thickness of 30 nm”; ½ of that being 15nm and 15nm being not more than 15nm), and, (claim 6) wherein the interface region (IR) is in contact with a doping region (n) formed in the semiconductor substrate (“n-type SiC single crystal substrate 1”).
Regarding claim 18, Hoshito discloses a semiconductor device (Fig. 1 above), comprising:
a semiconductor substrate (1); and
a metal nitride layer (2-3) above the semiconductor substrate, wherein:
an interface region (IR) of the semiconductor device comprises:
a first portion (R1s) of the semiconductor substrate;
a first portion (R1m or ½ thickness of 2) of the metal nitride layer (2-3); and
an interface (I) between the first portion (R1s) of the semiconductor substrate and the first portion (R1m) of the metal nitride layer;
the interface region extends into the metal nitride layer (2/3) not more than 20 nanometers (nm) (per MPEP 2111, IR is selected to end a ½ the thickness of layer 2 which has “a thickness of 30 nm”; ½ of that being 15nm); and
a distribution of nitrogen content throughout the metal nitride (2-3) layer has a (one of many) maximum concentration at the first portion (R1m) of the metal nitride layer (“TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers” implies that R1m has a higher N concentration than 3 and R1m has a maximum as claimed).
Regarding claims 19 and 20, Hoshito discloses (claim 19) wherein the semiconductor substrate comprises at least one of silicon carbide (SiC), gallium nitride (GaN), or Si (silicon) (SiC disclosed), and (claim 20) wherein the metal nitride layer (2-3) comprises at least one of Ti (titanium), Si (silicon), Al (aluminum), W (tungsten), Ta (tantalum), or Mo (molybdenum) (TiN disclosed).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (JP 3439597 B2).
Regarding claims 7-8, Hoshino discloses (claim 7) comprising a metallization structure (4) above the metal nitride layer (2-3, Fig. 1), and, (claim 8) wherein the metal nitride layer (2-3) and the metallization structure (4) provide a metallization of the semiconductor device (Fig. 1).
Hoshino fails to disclose (a) metallization structures (plural) and (b) backside metallization.
However, it would have been obvious to one of ordinary skill in the art to include plural metallization structures and a backside metallization before the effective filing date in the device of Hoshino so as to ensure that “an ohmic electrode having low contact resistance and excellent stability in a high temperature environment is provided” (per Hoshino) is applied to back metallization of a power device and so as to provide means for allowing formation of backside metallization structures in multiple power devices since duplication of parts is prima-facie obvious (MPEP 2144.04-VI).
Claims 1-3, 5-8 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hoshino et al. (JP 3439597 B2).
Note: the instant rejection is based on an alternative interpretation of Hoshino. In order to avoid confusion, this rejection is added under a separate statement of rejection.
Regarding claim 1, Hoshino discloses a semiconductor device (Fig. 1), comprising:
a semiconductor substrate (1, “n-type SiC single crystal substrate 1”); and
a (MPEP 2111) metal nitride (comprising) (multi)layer (2-3, “TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers”) above the semiconductor substrate, wherein (MPEP 2111):
an interface region (IR) of the semiconductor device comprises:
a first portion of the semiconductor substrate (R1s);
a first portion (R1m or 2 per MPEP 2111) of the metal nitride (comprising) (multi)layer (2-3); and
an interface (I) between the first portion of the semiconductor substrate (R1s) and the first portion of the metal nitride layer (R1m);
the interface region extends into the metal nitride layer (2/3) not more than 30 nanometers (nm) (per MPEP 2111, IR is selected to include of layer 2 which has “a thickness of 30 nm”); and
a (one of many) concentration of nitrogen content at the first portion of the metal nitride layer (R1m) is higher than a concentration of nitrogen content at a second portion (3), of the metal nitride (comprising) (multi)layer(2-3), outside the interface region (IR, “TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers” implies that R1m has a higher N concentration than 3).
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Hoshino fails to disclose the interface region extends into the metal nitride layer not more than 20 nanometers (nm). Recall: under this rejection IR extends into 2/3 30nm.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to reduce the thickness of layer 2 to be 20nm (instead of 30nm) and arrive at the claimed invention in Hoshino so as to achieve “minimizing the contact resistance of SiC and the resistance of TiN itself” as disclosed by Hoshino as a matter of routine experimentation (MPEP 2144.05).
Regarding claims 2-3, Hoshino discloses (claim 2) wherein the semiconductor substrate comprises at least one of silicon carbide (SiC), gallium nitride (GaN), or Si (silicon) (“n-type SiC single crystal substrate 1”), and (claim 3) wherein the metal nitride layer (2-3) comprises at least one of Ti (titanium), Si (silicon), Al (aluminum), W (tungsten), Ta (tantalum), or Mo (molybdenum) (“TiN layer 2”).
Regarding claim 5, Hoshino fails to disclose wherein the interface region extends into the metal nitride layer not more than 15 nanometers (nm) Recall: under this rejection IR extends into 2/3 30nm.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to reduce the thickness of layer 2 to be 15nm (instead of 30nm) and arrive at the claimed invention in Hoshino so as to achieve “minimizing the contact resistance of SiC and the resistance of TiN itself” as disclosed by Hoshino as a matter of routine experimentation (MPEP 2144.05).
Regarding claim 6, Hoshino discloses wherein the interface region (IR) is in contact with a doping region (n) formed in the semiconductor substrate (“n-type SiC single crystal substrate 1”).
Regarding claims 7-8, Hoshino discloses (claim 7) comprising a metallization structure (4) above the metal nitride layer (2-3, Fig. 1), and, (claim 8) wherein the metal nitride layer (2-3) and the metallization structure (4) provide a metallization of the semiconductor device (Fig. 1).
Hoshino fails to disclose (a) metallization structures (plural) and (b) backside metallization.
However, it would have been obvious to one of ordinary skill in the art to include plural metallization structures and a backside metallization before the effective filing date in the device of Hoshino so as to ensure that “an ohmic electrode having low contact resistance and excellent stability in a high temperature environment is provided” (per Hoshino) is applied to back metallization of a power device and so as to provide means for allowing formation of backside metallization structures in multiple power devices since duplication of parts is prima-facie obvious (MPEP 2144.04-VI).
Regarding claim 18, Hoshino discloses a semiconductor device (Fig. 1 above), comprising:
a semiconductor substrate (1); and
a metal nitride layer (2-3) above the semiconductor substrate, wherein:
an interface region (IR) of the semiconductor device comprises:
a first portion (R1s) of the semiconductor substrate;
a first portion (R1m or 2) of the metal nitride layer (2-3); and
an interface (I) between the first portion (R1s) of the semiconductor substrate and the first portion (R1m) of the metal nitride layer;
the interface region extends into the metal nitride layer (2/3) not more than 30 nanometers (nm) (per MPEP 2111, IR is selected to include of layer 2 which has “a thickness of 30 nm”); and
a distribution of nitrogen content throughout the metal nitride (2-3) layer has a (one of many) maximum concentration at the first portion (R1m) of the metal nitride layer (“TiN layer 2 and the Ti layer 4, the transition layer 3 in which the N content gradually decreases from the TiN layer to the Ti layer is inserted between both layers” implies that R1m has a higher N concentration than 3 and R1m has a maximum as claimed).
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Hoshino fails to disclose the interface region extends into the metal nitride layer not more than 20 nanometers (nm). Recall: under this rejection IR extends into 2/3 30nm.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to reduce the thickness of layer 2 to be 20nm (instead of 30nm) and arrive at the claimed invention in Hoshino so as to achieve “minimizing the contact resistance of SiC and the resistance of TiN itself” as disclosed by Hoshino as a matter of routine experimentation (MPEP 2144.05).
Regarding claims 19 and 20, Hoshino discloses (claim 19) wherein the semiconductor substrate comprises at least one of silicon carbide (SiC), gallium nitride (GaN), or Si (silicon) (SiC disclosed), and (claim 20) wherein the metal nitride layer (2-3) comprises at least one of Ti (titanium), Si (silicon), Al (aluminum), W (tungsten), Ta (tantalum), or Mo (molybdenum) (TiN disclosed).
Response to Arguments
Note: the examiner notes that applicant’s reply did not address the drawing objections of claims 6-8 nor the 35 USC 112 rejections of claims 3-4 and 20. Said objections and rejections and included in the instant Office Action (OA) again.
Applicant’s arguments, see p. 6-8, filed 10.9.2025, with respect to [0049] (“It has been observed by transmission electron microscopy (TEM) micrographs and energy-dispersive X-ray (EDX) mapping of thermally annealed structures that the distribution of nitrogen content throughout the metal nitride layer shows a higher concentration of nitrogen content at the interface region 15 (e.g., at or near the interface between the metal nitride layer 20 and the SiC substrate 10) than in a second portion, of the metal nitride layer 20, outside the interface region 15”) providing support for the claimed subject matter of the claims have been fully considered and are persuasive. The 35 USC 112 rejections and drawing objections of the previous Office Action related to the presence of the interface region are withdrawn.
Applicant’s arguments, see p. 8-9, filed 10.9.2025, with respect to Hoshino failing to disclose “the interface region extends into the metal nitride layer not more than 20 nanometers (nm)” because the thickness of layer 2 is 30nm are persuasive. However, in a new interpretation of Hoshino, Hoshino discloses the interface region extends into the metal nitride layer (2/3) not more than 20 nanometers (nm) (per MPEP 2111, IR is selected to end a ½ the thickness of layer 2 which has “a thickness of 30 nm”; ½ of that being 15nm). The start and end points of the IR region can be selected based on MPEP 2111 and in this case, it is selected to be ½ of the thickness of layer 2 which was a thickness of 30nm and said ½ thickness being 15nm and meeting the claimed limitation.
Applicant’s arguments, see p.8-9, filed 10.9.2025, with respect to “the interface region extends into the metal nitride layer not more than 20 nanometers (nm)” being critical, as understood by the examiner, because [0049] discloses “It is advantageous that the maximum of the nitrogen content is at or close to the interface to the semiconductor substrate to increase the electrical performance” have been considered but are not persuasive because MPEP 2144.05 states that “the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range” an in this case [0049] does not appear to rise to the level of showing criticality or unexpected results but rather an expected benefit of the claimed ranges.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/ Primary Patent Examiner, Art Unit 2818