Prosecution Insights
Last updated: July 17, 2026
Application No. 18/097,749

IMAGE SENSOR

Non-Final OA §103
Filed
Jan 17, 2023
Priority
Feb 24, 2022 — RE 10-2022-0024283 +1 more
Examiner
NETTLES, CORALIE ANN
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
23 granted / 34 resolved
At TC average
Strong +32% interview lift
Without
With
+31.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
38 currently pending
Career history
87
Total Applications
across all art units

Statute-Specific Performance

§103
93.3%
+53.3% vs TC avg
§102
3.8%
-36.2% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 34 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 7, 2026 has been entered. Response to Amendment This Office Action is in response to Applicant's amendments filed March 27, 2026. Claims 1, 11-15, and 19-20 have been amended. No claims have been added. Claim 7 has been canceled. Claim 4 stands withdrawn. Currently, claims 1-2, 5, 8, 11-15, and 18-20 are pending. Response to Arguments Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5, 8, 11-12, 15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al. (US 20230215901 A1) herein after “Yamashita” in view of Matsumoto et al. (US 20230143387 A1) herein after “Matsumoto” and Honda et al. (US 20200286937 A1) herein after “Honda”. Regarding claim 1, Figs. 1, 4, and 14 of Yamashita disclose an image sensor (Fig. 1, solid-state imaging element 1, ¶ [0073]) comprising: a substrate (Fig. 4, semiconductor layer 20, ¶ [0102]) including a pixel region (see Annotation 1, Fig. 14 of Yamashita, PX1), the substrate (20) extending in a first direction (see Annotation 1, Fig. 14 of Yamashita, D1) and a second direction (see Annotation 1, Fig. 14 of Yamashita, D2) intersecting the first direction (D1); a first photoelectric conversion region (see Annotation 1, Fig. 14 of Yamashita, PD1) and a second photoelectric conversion region (see Annotation 1, Fig. 14 of Yamashita, PD2) which are disposed in the pixel region (PX1) of the substrate (20) and are adjacent to each other in the first direction (D1), the first photoelectric conversion region (PD1) includes a first portion (Fig. 14, visible-light pixel PDc, ¶ [0126]) and a second portion (Fig. 14, infrared-light pixel PDw, ¶ [0126]), and the second photoelectric conversion region (PD2) includes a third portion (PDw) and a fourth portion (PDc); a deep device isolation pattern (Fig. 14, deep trench part 230, shallow trench part 231, ¶ [0133]) penetrating the substrate (20) in a third direction (see Annotation 1, Fig. 14 of Yamashita, D3) perpendicular to the first direction (D1) and the second direction (D2), and surrounding the pixel region (PX1), the deep device isolation pattern (230, 231) comprising first extensions (see Annotation 1, Fig. 14 of Yamashita, 230A) extending in the second direction (D2) between the first portion (PDc) of the first photoelectric conversion region (PD1) and the third portion (PDw) of the second photoelectric conversion region (PD2), and extending in the second direction (D2) between the second portion (PDw) of the first photoelectric conversion region (PD1) and the fourth portion (PDc) of the second photoelectric conversion region (PD2), and the first extensions (230A) spaced apart from each other in the second direction (D2), and second extensions (see Annotation 1, Fig. 14 of Yamashita, 230B) extending in the first direction (D1) between the first portion (PDc) of the first photoelectric conversion region (PD1) and the second portion (PDw) of the first photoelectric conversion region, and extending in the first direction (D1) between the third portion (PDw) of the second photoelectric conversion region (PD2) and the fourth portion (PDc) of the second photoelectric conversion region (PD2), the second extensions (230B) spaced apart from each other in the first direction (D1); a plurality of first transfer gate electrodes (see Annotation 1, Fig. 14 of Yamashita, TG1) disposed on the pixel region (PX1) of the substrate (20) and vertically overlapping with the first photoelectric conversion region (PD1) in the third direction (D3); and a plurality of second transfer gate electrodes (see Annotation 1, Fig. 14 of Yamashita, TG2) disposed on the pixel region (PX1) of the substrate (20) and vertically overlapping with the second photoelectric conversion region (PD2) in the third direction (D3), wherein the first photoelectric conversion region (PD1) extends in the second direction (D2) under the plurality of first transfer gate electrodes (TG1), wherein the first extensions (230A) and the second extensions (230B) define an active pattern (“active regions”, ¶ [0135]) of the pixel region (PX1), wherein a floating diffusion region (Fig. 14, floating diffusion region FD, ¶ [0128]) is disposed in the active pattern (“active regions”, ¶ [0135]) and is disposed between the first extensions (230A) and between the second extensions (230B), wherein one of the plurality of first transfer gate electrodes (TG1) is configured to electrically connect the first portion (PDc) of the first photoelectric conversion region (PD1) to the floating diffusion region (FD), wherein another of the plurality of first transfer gate electrodes (TG1) is configured to electrically connect the second portion (PDw) of the first photoelectric conversion region (PD1) to the floating diffusion region (FD), wherein the first portion (PDc) and the second portion (PDw) of the first photoelectric conversion region (PD1) are continuously connected to each other under the plurality of first transfer gate electrodes (TG1). PNG media_image1.png 526 705 media_image1.png Greyscale Annotation 1, Fig. 14 of Yamashita Yamashita fails to disclose wherein a first length, in the second direction, of each of the first extensions disposed directly between the first portion of the first photoelectric conversion region and the third portion of the second photoelectric conversion region. and disposed directly between the second portion of the first photoelectric conversion region and the fourth portion of the second photoelectric conversion region is greater than a second length in the second direction of the active pattern disposed directly between the first extensions, and wherein a third length, in the first direction, of each of the second extensions is less than the first length, in the second direction, of each of the first extensions. In the similar field of endeavor of imaging devices, Fig. 14 of Matsumoto discloses wherein a first length, in the second direction, of each of the first extensions (Fig. 14, protruding portion 304, ¶ [0153]) disposed directly between the first portion (Fig. 14, pixels 300a, ¶ [0153]) of the first photoelectric conversion region and the third portion (Fig. 14, pixels 300b, ¶ [0153]) of the second photoelectric conversion region, and disposed directly between the second portion (Fig. 14, pixels 300c, ¶ [0199]) of the first photoelectric conversion region and the fourth portion (Fig. 14, pixels 300d, ¶ [0199]) of the second photoelectric conversion region is greater than a second length in the second direction of the active pattern (Fig. 14, slit 312, ¶ [0153]) disposed directly between the first extensions (304). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the image sensor of Yamashita with the first extensions as disclosed by Matsumoto, to reduce deterioration of the captured image (see Matsumoto, ¶ [0269]). Matsumoto fails to disclose wherein a third length, in the first direction, of each of the second extensions is less than the first length, in the second direction, of each of the first extensions. In the similar field of endeavor of solid-state imaging devices, Fig. 24C of Honda discloses wherein a third length (see Annotation 2, Fig. 24C of Honda, L3), in the first direction (horizontal in Fig. 24C), of each of the second extensions is less than the first length (see Annotation 2, Fig. 24C of Honda, L1), in the second direction (vertical in Fig. 24C), of each of the first extensions. PNG media_image2.png 431 332 media_image2.png Greyscale Annotation 2, Fig. 24C of Honda It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the image sensor of Yamashita with the first and second extensions as disclosed by Honda, to reduce color mixing and improve charge properties (see Honda, ¶ [0192]). Regarding claim 2, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, and Fig. 14 of Yamashita discloses wherein the second photoelectric conversion region (PD2) extends in the second direction (D2) under the plurality of second transfer gate electrodes (TG2). Regarding claim 5, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, but Yamashita fails to explicitly disclose wherein a lower portion of each of the plurality of first transfer gate electrodes extends into the substrate toward the first photoelectric conversion region in the third direction, and wherein a lower portion of each of the plurality of second transfer gate electrodes extends into the substrate toward the second photoelectric conversion region in the third direction. In the similar field of endeavor of imaging devices, Fig. 37 of Matsumoto discloses wherein a lower portion of each of the plurality of first transfer gate electrodes (400a) extends into the substrate (10) toward the first photoelectric conversion region in the third direction (vertical in Fig. 37), and wherein a lower portion of each of the plurality of second transfer gate electrodes (400b) extends into the substrate (10) toward the second photoelectric conversion region in the third direction (vertical in Fig. 37). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transfer gate electrodes of Yamashita with the lower portion as disclosed by Matsumoto, to improve charge transfer (see Matsumoto, ¶ [0235]) and/or because the substitution of one known transfer gate structure for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention (see MPEP 2143IB). Regarding claim 8, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, and Fig. 14 of Yamashita further discloses wherein the plurality of first transfer gate electrodes (TG1) and the plurality of second transfer gate electrodes (TG2) are disposed adjacent to the floating diffusion region (FD). Regarding claim 11, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, and Fig. 14 of Yamashita further discloses wherein one of the plurality of second transfer gate electrodes (TG2) is configured to electrically connect the third portion (PDw) of the second photoelectric conversion region (PD2) to the floating diffusion region (FD), wherein another of the plurality of second transfer gate electrodes (TG2) is configured to electrically connect the fourth portion (PDc) of the second photoelectric conversion region (PD2) to the floating diffusion region (FD). Regarding claim 12, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 11 as applied above, and Fig. 14 of Yamashita further discloses wherein the third portion (PDw) and the fourth portion (PDc) of the second photoelectric conversion region (PD2) are continuously connected to each other under the plurality of second transfer gate electrodes (TG2). Regarding claim 15, Figs. 1, 4, and 14 of Yamashita disclose an image sensor (Fig. 1, solid-state imaging element 1, ¶ [0073]) comprising: a substrate (20) having a first surface and a second surface which are opposite to each other, the substrate (20) comprising a pixel region (PX1), the substrate (20) extending in a first direction (D1) and a second direction (D2) intersecting the first direction (D1); a first photoelectric conversion region (PD1) and a second photoelectric conversion region (PD2) which are disposed in the pixel region (PX1) of the substrate (20) and are adjacent to each other in the first direction (D1), the first photoelectric conversion region (PD1) includes a first portion (PDc) and a second portion (PDw), and the second photoelectric conversion region (PD2) includes a third portion (PDw) and a fourth portion (PDc); a deep device isolation pattern (230, 231) penetrating the substrate (20) in a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2), the deep device isolation pattern (230, 231) surrounding the pixel region (PX1) along the first direction (D1) and second direction (D2), the deep device isolation pattern (230, 231) comprising first extensions (230A) extending in the second direction (D2) between the first portion (PDc) of the first photoelectric conversion region (PD1) and the third portion (PDw) of the second photoelectric conversion region (PD2), and extending in the second direction (D2) between the second portion (PDw) of the first photoelectric conversion region (PD1) and the fourth portion (PDc) of the second photoelectric conversion region (PD2), and the first extensions (230A) spaced apart from each other in the second direction (D2); second extensions (230B) extending in the first direction (D1) between the first portion (PDc) of the first photoelectric conversion region (PD1) and the second portion (PDw) of the first photoelectric conversion region, and extending in the first direction (D1) between the third portion (PDw) of the second photoelectric conversion region (PD2) and the fourth portion (PDc) of the second photoelectric conversion region (PD2), the second extensions (230B) spaced apart from each other in the first direction (D1), a plurality of first transfer gate electrodes (TG1) disposed on the pixel region (PX1) of the substrate (20) and on the first photoelectric conversion region (PD1); and a plurality of second transfer gate electrodes (TG2) disposed on the pixel region (PX1) of the substrate (20) and on the second photoelectric conversion region (PD2), wherein the first photoelectric conversion region (PD1) extends in the second direction (D2) from a side of one of the first extensions (230A) to a side of another of the first extensions (230A), wherein the second photoelectric conversion region (PD2) extends in the second direction (D2) from another side of the one of the first extensions (230A) to another side of the another of the first extensions (230A), wherein the first extensions (230A) and the second extensions (230B) define an active pattern (“active regions”, ¶ [0135]) of the pixel region (PX1), wherein a floating diffusion region (FD) is disposed in the active pattern (“active regions”, ¶ [0135]) and is disposed between the first extensions (230A) and between the second extensions (230B), wherein the first portion (PDc) and the second portion (PDw) of the first photoelectric conversion region (PD1) are continuously connected to each other. Yamashita fails to disclose wherein a first length, in the second direction, of each of the first extensions disposed directly between the first portion of the first photoelectric conversion region and the third portion of the second photoelectric conversion region. and disposed directly between the second portion of the first photoelectric conversion region and the fourth portion of the second photoelectric conversion region is greater than a second length in the second direction of the active pattern disposed directly between the first extensions, and wherein a third length, in the first direction, of each of the second extensions is less than the first length, in the second direction, of each of the first extensions. In the similar field of endeavor of imaging devices, Fig. 14 of Matsumoto discloses wherein a first length, in the second direction, of each of the first extensions (304) disposed directly between the first portion (300a) of the first photoelectric conversion region and the third portion (300b) of the second photoelectric conversion region, and disposed directly between the second portion (300c) of the first photoelectric conversion region and the fourth portion (300d) of the second photoelectric conversion region is greater than a second length in the second direction of the active pattern (312) disposed directly between the first extensions (304). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the image sensor of Yamashita with the first extensions as disclosed by Matsumoto, to reduce deterioration of the captured image (see Matsumoto, ¶ [0269]). Matsumoto fails to disclose wherein a third length, in the first direction, of each of the second extensions is less than the first length, in the second direction, of each of the first extensions. In the similar field of endeavor of solid-state imaging devices, Fig. 24C of Honda discloses wherein a third length (L3), in the first direction (horizontal in Fig. 24C), of each of the second extensions is less than the first length (L1), in the second direction (vertical in Fig. 24C), of each of the first extensions. It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the image sensor of Yamashita with the first and second extensions as disclosed by Honda, to reduce color mixing and improve charge properties (see Honda, ¶ [0192]). Regarding claim 18, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 15 as applied above, and Fig. 14 of Yamashita further discloses wherein the plurality of first transfer gate electrodes (TG1) and the plurality of second transfer gate electrodes (TG2) are disposed adjacent to the floating diffusion region (FD). Regarding claim 19, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 18 as applied above, and Fig. 14 of Yamashita further discloses wherein one of the plurality of first transfer gate electrodes (TG1) is disposed on a first portion (PDc) of the first photoelectric conversion region (PD1), and wherein the first portion (PDc) and the second portion (PDw) of the first photoelectric conversion region (PD1) are continuously connected to each other under the plurality of first transfer gate electrodes (TG1). Regarding claim 20, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 19 as applied above, and Fig. 14 of Yamashita further discloses wherein one of the plurality of second transfer gate electrodes (TG2) is disposed on a third portion (PDw) of the second photoelectric conversion region (PD2), wherein another of the plurality of second transfer gate electrodes (TG2) is disposed on the fourth portion (PDc) of the second photoelectric conversion region (PD2), and wherein the third portion (PDw) and the fourth portion (PDc) of the second photoelectric conversion region (PD2) are continuously connected to each other under the plurality of second transfer gate electrodes (TG2). Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US 20230215901 A1), Matsumoto (US 20230143387 A1) and Honda et al. (US 20200286937 A1) in further view of Abe (US 20140284665 A1). Regarding claim 13, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, but Yamashita and Honda fail to disclose wherein each of the plurality of first transfer gate electrodes includes: a lower portion extending into the substrate toward the first photoelectric conversion region in the third direction; and an upper portion protruding above the substrate, and wherein the upper portions of adjacent first transfer gate electrodes of the plurality of first transfer gate electrodes are directly connected to each other and extend across the first portion of the first photoelectric conversion region and the second portion of the first photoelectric conversion region. In the similar field of endeavor of imaging devices, Fig. 37 of Matsumoto discloses wherein each of the plurality of first transfer gate electrodes (400a) includes: a lower portion extending into the substrate (10) toward the first photoelectric conversion region in the third direction (vertical in Fig. 37). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transfer gate electrodes of Yamashita with the upper and lower portion as disclosed by Matsumoto, to improve charge transfer (see Matsumoto, ¶ [0235]) and/or because the substitution of one known transfer gate structure for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention (see MPEP 2143IB). Matsumoto fails to disclose wherein the upper portions of adjacent first transfer gate electrodes of the plurality of first transfer gate electrodes are directly connected to each other and extend across the first portion of the first photoelectric conversion region and the second portion of the first photoelectric conversion region. In the similar field of endeavor of solid-state imaging devices, Fig. 4 of Abe discloses wherein the upper portions of adjacent first transfer gate electrodes of the plurality of first transfer gate electrodes (Fig. 4, transfer gates 38, ¶ [0058]) are directly connected to each other and extend across the first portion of the first photoelectric conversion region and the second portion of the first photoelectric conversion region (Fig. 4, photodiodes (PDs) 337 separated by element separation region 61, ¶ [0058] and [0084]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the plurality of first transfer gate electrodes of Yamashita with the structure as disclosed by Abe, to obtain the desired electric charge transfer characteristics (see Abe, ¶ [0086]). Regarding claim 14, Yamashita, Matsumoto, and Honda together disclose the image sensor of claim 1 as applied above, but Yamashita and Honda fail to disclose wherein each of the plurality of second transfer gate electrodes includes: a lower portion extending into the substrate toward the second photoelectric conversion region in the third direction; and an upper portion protruding above the substrate, and wherein the upper portions of adjacent second transfer gate electrodes of the plurality of second transfer gate electrodes are connected to each other. In the similar field of endeavor of imaging devices, Fig. 37 of Matsumoto discloses wherein each of the plurality of second transfer gate electrodes (400b) includes: a lower portion extending into the substrate (10) toward the first photoelectric conversion region in the third direction (vertical in Fig. 37); and an upper portion protruding above the substrate (10). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transfer gate electrodes of Yamashita with the upper and lower portion as disclosed by Matsumoto, to improve charge transfer (see Matsumoto, ¶ [0235]) and/or because the substitution of one known transfer gate structure for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention (see MPEP 2143IB). Matsumoto fails to disclose wherein the upper portions of adjacent second transfer gate electrodes of the plurality of second transfer gate electrodes are directly connected to each other and extend across the third portion of the second photoelectric conversion region and the fourth portion of the second photoelectric conversion region. In the similar field of endeavor of solid-state imaging devices, Fig. 4 of Abe discloses wherein the upper portions of adjacent second transfer gate electrodes of the plurality of second transfer gate electrodes (38) are directly connected to each other and extend across the third portion of the second photoelectric conversion region and the fourth portion of the second photoelectric conversion region (Fig. 4, photodiodes (PDs) 337 separated by element separation region 61, ¶ [0058] and [0084]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the plurality of first transfer gate electrodes of Yamashita with the structure as disclosed by Abe, to obtain the desired electric charge transfer characteristics (see Abe, ¶ [0086]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.A.N./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Show 5 earlier events
Nov 13, 2025
Applicant Interview (Telephonic)
Nov 20, 2025
Response Filed
Jan 16, 2026
Final Rejection mailed — §103
Mar 11, 2026
Interview Requested
Mar 27, 2026
Response after Non-Final Action
May 07, 2026
Request for Continued Examination
May 11, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12674094
SEMICONDUCTOR NANOPARTICLE, AND COLOR CONVERSION PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME
3y 3m to grant Granted Jul 07, 2026
Patent 12660176
BACKSIDE PROGRAMMABLE MEMORY
3y 7m to grant Granted Jun 16, 2026
Patent 12660227
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Jun 16, 2026
Patent 12632089
FLEXIBLE DISPLAY PANEL AND ELECTRONIC DEVICE
3y 2m to grant Granted May 19, 2026
Patent 12604468
VERTICAL NOR FLASH THIN FILM TRANSISTOR STRINGS AND FABRICATION THEREOF
4y 3m to grant Granted Apr 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
99%
With Interview (+31.7%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 34 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month