Prosecution Insights
Last updated: October 02, 2026
Application No. 18/097,939

LOW Z-HEIGHT LED ARRAY PACKAGE HAVING TSV SUPPORT STRUCTURE

Final Rejection §103
Filed
Jan 17, 2023
Priority
Jul 15, 2020 — provisional 63/052,151 +3 more
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lumileds LLC
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
379 granted / 568 resolved
-1.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
600
Total Applications
across all art units

Statute-Specific Performance

§103
55.1%
+15.1% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 568 resolved cases

Office Action

§103
Attorney’s Docket Number: 5241.203US2 Filing Date: 1/17/2023 Claimed Priority Dates: 7/15/2021 (PCT/US21/41867) 9/9/2020 (EP 20195344.5) 7/15/2020 (US 63/052,151) Inventors: Hin et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to amendment filed on 6/30/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the illumination system recited in claims 1 and 16 must be shown or the features canceled from the claims. No new matter should be entered. The drawings are objected to because Fig. 5 and Fig. 6 purport to depict a correspondence between the claimed features and the structures shown therein. However, it is unclear how the plurality of waveguides and the lens shown in Fig. 5 are arranged relative to the other claimed features shown in Fig. 6, the pixels, substrate, redistribution layers (RDLs), vias and CMOS. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-8, 10, 11, 13, 14, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu (US 2019/0195466) in view of Banna (US 2017/0358562). Regarding claim 1, Shimizu (see, e.g., fig. 1B) shows most aspects of the instant invention including an adaptive illumination system 1000 comprising: A plurality of pixels 1010/1020/1030 A plurality of waveguides 1062, wherein each pixel is configured to emit light into a respective waveguide (¶0042) A lens 1064 configured to receive an direct the light from the waveguides Shimizu, however, fails to show the system also comprising an inorganic substrate, a via and a CMOS. Banna (see, e.g., fig. 3), in a similar system to Shimizu, show an illumination system 300 comprising: A plurality of pixels 322 An inorganic substrate 301 having a top RDL 239 attached to the pixels At least one through via 338 containing an electrical conductor and defined to pass through the substrate to support an electrical coupling with the top RDL A CMOS 240 electrically coupled to the via wherein the top RDL is between the via and the pixels. Banna (¶0020) teaches that the CMOS facilitated compactness, low power consumption, low cost as well as enhanced user experience for a display system. Accordingly, it would have been obvious at the time of filing the invention to a person having ordinary skill in the art (PHOSITA) to include the substrate, via and CMOS of Banna in the system of Shimizu to facilitate low power consumption and cost. Regarding claim 2, Shimizu (see, e.g., fig. 1B) shows a plurality of pixels 1010/1020/1030. With respect to the limitations reciting that each pixels is independently controllable, this limitation is functional in nature and describes a capability or intended use of the recited pixel structure rather than imposing a structural limitation. Although Shimizu does not explicitly describe that each pixel is independently controllable, the disclosed structure includes individual electrical connections 1015/1040 to pixels, which inherently allows for independent control of each pixel. Further, the functional language “independently controllable” does not require any additional structural limitations beyond those already disclosed by Shimizu. Therefore, the claimed capability is inherent in the disclosed structure and represents an intended use that does not distinguish over the prior art. Regarding claim 3, Shimizu (see, e.g., fig. 1D) shows a plurality of pixel devices arranged in an array, which inherently permits grouping of pixels and control in subsets or blocks through appropriate addressing or driving schemes. With respect to the language reciting that the pixels are controllable in pixel blocks, this limitation similarly recites a functional capability rather than a structural distinction (see paragraph 14 above). The claim does not recite any specific structural features that would distinguish “pixel block” control from the structure disclosed in Shimizu. As such, the recited functionality does not patentably distinguish over the prior art structure. Regarding claim 4, Banna (see, e.g., fig. 3) shows the system further comprising a support 260 supporting the CMOS 240 and a sensor 270 on the support. Accordingly, Banna teaches the claimed support and sensor arrangement. With respect to the limitation that the pixels are “configured to provide light distribution patterns based at least in part on sensor data received from the sensors” this limitation is functional in nature and describes the intended operation or use of the recited pixel system rather than imposing a structural limitation. Banna discloses a plurality of light-emitting elements (pixels) 322 and associated circuitry 240 capable of receiving signals from the sensors 270 (see, e.g., fig. 3). Although Banna does not explicitly describe using sensor data to control light distribution patterns, the claimed functional language does not recite any specific structural features that would distinguish the claimed pixels from those disclosed in Banna. The capability of providing light distribution patterns based on sensor data would have been inherently present in, and at least reasonably achievable by, the structure disclosed in Banna through routine control of the light-emitting elements using input signals, including signals from the sensors. Thus, the “configured to provide” limitation is an intended use that does not distinguish over the prior art and an inherent capability of the disclosed system. Regarding claim 5, Shimizu shows the system further comprising a lens 1064 spaced apart from the pixels and arranged to direct light emitted by the pixels. Regarding claim 6, Shimizu (see, e.g., fig. 1B) teaches that the lens 1064 is disposed over all of the pixels. Regarding claim 7, Shimizu (see, e.g., ¶0042/ll.3-6) teaches that the lens is disposed over only some of the pixels. Regarding claim 8, Banna (see, e.g., fig. 2) shows that the top RDL 239 is attached to each pixel 322 using a copper post 238. Regarding claim 10, Banna (see, e.g., fig. 3) shows the substrate further comprising a bottom RDL 239 opposite from the top RDL, the bottom RDL disposed between the via 338 and the CMOS 240. Regarding claim 11, Banna (see, e.g., fig. 3) shows the bottom RDL 239 directly contacts the via 338. Regarding claim 13, Banna (see, e.g., fig. 3) shows the system further comprising contact pads 257 directly contacting the CMOS 240 and the bottom RDL 239. Regarding claim 14, Banna (see, e.g., fig. 3) shows the system further comprising a support 260 in direct contact with the CMOS 240 on a side of the CMOS opposing the contact pads 257. Regarding claim 16, Shimizu (see, e.g., fig. 1B) shows all aspects of the instant invention including an adaptive illumination system 1000 comprising: A segmented monolithic structure comprising a plurality of light emitting elements (LEEs) 1010/1020/1030 A plurality of waveguides 1062, wherein each LEE is configured to emit light into a respective waveguide (¶0042) A lens 1064 configured to receive an direct the light from the waveguides Shimizu, however, fails to show the system also comprising a substrate, a plurality of vias and a support structure comprising a CMOS. Banna (see, e.g., fig. 3), in a similar system to Shimizu, show an illumination system 300 comprising: A plurality of LEEs 322 A substrate 301 attached to the LEEs A plurality of vias 338 extending through the substrate A support structure comprising a CMOS 240 electrically coupled to the LEEs through the vias Banna (¶0020) teaches that the CMOS facilitated compactness, low power consumption, low cost as well as enhanced user experience for a display system. Regarding claim 16, see also the comments above in paragraphs 12 and 13 with respect to claim 1, which are considered repeated here. Regarding claim 17, Banna (see, e.g., fig. 3) shows the LEEs 322 are centered on the substrate 301. Claims 9 and 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu/Banna in view of Wang (US 2006/0273307). Regarding claim 9, Banna (see, e.g., fig. 2) shows that the top RDL 239 is in direct contact with the Cu post 238. Banna, however, shows that the post is directly connected to the pixel 322, rather than the pixel being in direct contact with solder material attaching it to the post. Wang teaches forming conductive interconnections using low-melting point metals or metal alloys that are reflowed to form direct solder connections between a pixel and a conductive post (see, e.g., ¶¶ 0127-0128 and fig. 11). It would have been obvious to a PHOSITA at the time of filing the invention to substitute the direct connection of Banna’s pixel to the post with a solder-based connection, as taught by Wang, as solder interconnections represent a well-known alternative bonding technique for electrically and mechanically coupling conductive structures. Such substitution would have yielded predictable results, namely, providing an electrical and mechanical connection between the pixel and post. As set forth in KSR Int’l Co. V. Teleflex Inc., 550 US 398, 416 (2007), a claimed invention is obvious where it involves “the substitution of one know element for another to obtain predictable results”. Regarding claim 15, Banna (see, e.g., fig. 3) does not explicitly disclose that the thickness of the inorganic substrate 301, the contact pads 257, the CMOS 240, and the support 260 add up to be between 5 and 25 microns. Wang teaches that substrates and associated structures in electronic devices may be formed with a range of thicknesses depending on design requirements, and that such structures may be tailored in thickness to suit device needs (see, e.g., ¶ [0104], disclosing substrate thickness ranges and material flexibility). It would have been obvious to a PHOSITA at the time of filing the invention to optimize the thicknesses of the substrate, contact pads, CMOS, and support in Shimizu/Banna to achieve a reduced overall thickness, including within the claimed range, as a matter of routine design choice motivated by the desire for compact, low-profile electronic devices. The selection of a particular thickness within a known range or by routine optimization of a result-effective variable would have yielded predictable results, such as reduced device size and improved integration. As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves the application of known techniques to improve similar devices in the same way. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu/Banna in view of Sung (US 2017/0345802). Regarding claim 18, Banna (see, e.g., fig. 3) shows an adaptive illumination system but fails to show that the substrate 301 is disposed on a flexible printed circuit board. Sung teaches a display device including a wiring substrate 1010 on which semiconductor light emitting device packages are mounted and electrically coupled via wiring electrodes (¶¶0136–0139). Sung further teaches that the wiring substrate may be implemented as a printed circuit board (PCB) and that the PCB may be either a non-flexible (¶0138) or a flexible PCB (¶0211). It would have been obvious to a PHOSITA at the time of filing the invention to implement the substrate and external connection arrangement of Shimizu/Banna on a flexible printed circuit board as taught by Sung, since Sung explicitly teaches that PCBs, including flexible PCBs, are suitable wiring substrates for mounting and electrically interconnecting light emitting device packages. Flexible PCBs and non-flexible PCBs represent are known alternative substrate configurations that achieve predictable results, namely providing electrical interconnection and support for light emitting devices. As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves “the substitution of one known element for another to obtain predictable results.” Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu/Banna in view of Vampola (US 2018/0187839). Regarding claim 19, Banna (see, e.g., fig. 3) teaches traces 239 connecting to the through vias 338 for electrically coupling the light emitting elements 322 to associated circuitry. However, Banna does not explicitly disclose that the traces connected to the through vias have a greater density toward a center of the pixel array compared to an outer edge. Vampola teaches a metallized substrate including an array of pads connected by conductive traces that fan out toward the perimeter of the substrate (see, e.g., ¶¶ [0086]-[0090] and fig. 4). Vampola further teaches routing traces from inner pads through more complex paths, including diagonal and multi-directional routing between adjacent pads, in order to reach the perimeter. Due to this fan-out routing configuration, traces associated with pads near the center of the array must traverse more constrained routing paths and pass between multiple adjacent pads, resulting in a higher concentration and density of traces in the central region of the array, whereas traces associated with pads near the perimeter have more direct paths and therefore lower routing density. It would have been obvious to one of ordinary skill in the art at the time of the invention to implement the trace routing of Shimizu/Banna using the fan-out routing scheme taught by Vampola to efficiently route electrical connections from densely packed pixel arrays to external circuitry. Such routing would inherently result in a trace density that is greater toward the center of the array than toward the outer edge, as a consequence of routing constraints in densely packed arrays. As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves applying a known technique to a known device to yield predictable results. Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot because of the new ground of rejection. Conclusion Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action. Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp August 28, 2026
Read full office action

Prosecution Timeline

Jan 17, 2023
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §103
Jun 30, 2026
Response Filed
Sep 01, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751073
VERTICAL THIN FILM TRANSISTOR WITH DUAL GATE ELECTRODES
2y 9m to grant Granted Sep 29, 2026
Patent 12735637
Polymer and Organic Light-Emitting Device Using Same
2y 7m to grant Granted Sep 15, 2026
Patent 12720819
SOURCE OR DRAIN METALLIZATION PRIOR TO CONTACT FORMATION IN STACKED TRANSISTORS
4y 8m to grant Granted Aug 25, 2026
Patent 12709625
ORGANOMETALLIC COMPOUND FOR MASK, LAYER, METHOD FOR PROCESSING ORGANIC SEMICONDUCTOR LAYER, AND METHOD FOR MANUFACTURING ORGANIC SEMICONDUCTOR DEVICE
2y 6m to grant Granted Aug 18, 2026
Patent 12707634
THREE-DIMENSIONAL INTEGRATION STRUCTURE AND METHOD OF FORMING THE SAME
4y 9m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
81%
With Interview (+14.3%)
3y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 568 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month