Attorney’s Docket Number: 5241.203US2
Filing Date: 1/17/2023
Claimed Priority Dates: 7/15/2021 (PCT/US21/41867)
9/9/2020 (EP 20195344.5)
7/15/2020 (US 63/052,151)
Inventors: Hin et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the election and amendment filed on 2/27/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Species Restriction
Applicant’s election without traverse of species 1, reading on figure 4A, in the reply filed on 2/27/2026, is acknowledged. The applicants indicated that claims 1-20 read on the elected species. The examiner agrees.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the silicon vias recited in claim 20 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 12 and 20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor, or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Regarding claim 12, the claim recites that the CMOS is in direct contact with the pixels. The originally filed specification does not reasonably convey to one of ordinary skill in the art that the inventor had possession of a configuration in which the CMOS is in direct contact with the pixels.
The specification consistently describes a structure in which the pixels are electrically and physically coupled to a substrate (e.g., silicon substrate 130) that includes redistribution layers and through silicon vias (TSVs), and the CMOS die is attached to the substrate (see, e.g., ¶¶ [0015], [0048]). As shown in Fig. 6, the pixels are separated from the CMOS die by multiple intervening structures, including solder material, conductive posts, a top redistribution layer, the substrate containing TSVs, and a bottom redistribution layer.
Thus, the specification describes an indirect connection between the pixels and the CMOS via an intervening substrate and interconnect structure, rather than direct physical contact.
The specification does not disclose, suggest, or otherwise describe an embodiment in which the CMOS is in direct contact with the pixels, nor does it describe removal or omission of the intervening substrate and interconnect layers.
Accordingly, the specification fails to reasonably convey possession of the claimed subject matter, and claim 12 lacks adequate written description.
Regarding claim 20, the claim recites, inter alia, a plurality of silicon vias extending partially through a CMOS structure. The originally filed specification does not reasonably convey to one of ordinary skill in the art that the inventor had possession of a CMOS structure comprising a plurality of silicon vias extending partially through the structure.
While the specification describes the use of through silicon vias (TSVs) formed in a silicon substrate 130 to provide electrical interconnection between redistribution layers, the disclosure consistently locates such vias within the substrate/interposer, not within the CMOS structure itself. See, e.g., ¶¶ [0005], [0048], [0055], [0056].
Further, the specification describes and illustrates the CMOS die attached to the substrate 130 indicating that the CMOS structure is a separate component electrically coupled via the substrate and redistribution layers. There is no description of the CMOS structure itself including silicon vias, nor any disclosure of vias extending partially through a CMOS structure. See, e.g., ¶ [0015], ¶ [0048].
Accordingly, the specification fails to describe the claimed configuration in which the CMOS structure itself comprises silicon vias extending partially through it. The disclosure, therefore, does not reasonably convey possession of the full scope of the claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite.
The claim is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention.
Claim 9 recites the limitation "the copper post". There is insufficient antecedent basis for this limitation in the claim.
Claims 12 and 20 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Regarding claim 12, the claim 12 recites that the CMOS is in direct contact with the pixels. The specification does not enable one of ordinary skill in the art to make and use the claimed invention without undue experimentation.
As described in the specification, the disclosed system relies on an intervening substrate with through silicon vias and redistribution layers to electrically couple the pixels and the CMOS die (see, e.g., ¶ [0048]). However, the specification does not provide any teaching regarding how to configure the CMOS to be in direct physical contact with the pixels, how to eliminate or bypass the disclosed substrate and interconnect structures, or how to integrate the light-emitting elements with CMOS circuitry in direct contact while maintaining proper electrical operation, thermal management, and structural integrity.
In the absence of such guidance, the specification fails to enable claim 12.
Regarding claim 20, the claim recites, inter alia, a plurality of silicon vias extending partially through a CMOS structure. The specification does not enable one of ordinary skill in the art to make and use the claimed invention without undue experimentation. Although the specification describes through silicon vias formed in a substrate or interposer (e.g., ¶¶ [0048], [0055]), it does not provide any teaching regarding: formation of silicon vias within the CMOS structure itself, integration of such vias into CMOS circuitry, whether such vias are front-side, back-side, or through-device structures, or how such vias would be fabricated.
The fabrication and integration of vias within a CMOS structure involve complex process considerations (e.g., device layer integrity, metallization schemes, isolation, and thermal constraints), and the specification is silent as to these aspects.
In the absence of such guidance, the specification fails to enable claim 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 10-14, 16, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banna (US 2017/0358562).
Regarding claim 16, Banna (see, e.g., figs. 1a and 3) shows all aspects of the instant invention including an adaptive illumination system comprising:
A segmented monolithic structure 100 comprising a plurality of light emitting elements (LEEs) 322
A substrate 301 attached to the monolithic structure
A plurality of vias 338 extending through the substrate
A support structure 240 comprising a CMOS and electrically coupled to the monolithic structure through the vias
Regarding claim 17, Banna (see, e.g., fig. 3) shows the LEEs 322 are centered on the substrate 301.
Regarding claim 1, Banna (see, e.g., figs. 1a and 3) shows all aspects of the instant invention including an adaptive illumination system comprising:
A plurality of pixels 322
An inorganic substrate 301 having a top redistribution layer (RDL) 239 attached to the pixels
At least one through via 338 containing an electrical conductor and defined to pass through the substrate 301 to support an electrical coupling with the top RDL
A CMOS 240 electrically coupled to the via 338
wherein the top RDL is between the via 338 and the pixels 322.
Regarding claim 2, Banna (see, e.g., fig. 3) shows a plurality of pixels 322 arranged on a substrate 301 with electrical interconnections 338/239. With respect to the limitations reciting that each pixels is independently controllable, this limitation is functional in nature and describes a capability or intended use of the recited pixel structure rather than imposing a structural limitation. Although Banna does not explicitly describe that each pixel is independently controllable, the disclosed structure includes individual electrical connections to pixels, which inherently allows for independent control of each pixel. Further, the functional language “independently controllable” does not require any additional structural limitations beyond those already disclosed by Banna. Therefore, the claimed capability is inherent in the disclosed structure and represents an intended use that does not distinguish over the prior art.
Regarding claim 3, Banna shows a plurality of pixel devices 120 arranged in an array, which inherently permits grouping of pixels and control in subsets or blocks through appropriate addressing or driving schemes. With respect to the language reciting that the pixels are controllable in pixel blocks, this limitation similarly recites a functional capability rather than a structural distinction (see paragraph 34 above). The claim does not recite any specific structural features that would distinguish “pixel block” control from the structure disclosed in Banna. As such, the recited functionality does not patentably distinguish over the prior art structure.
Regarding claim 4, Banna (see, e.g., fig. 3) shows the system further comprising a support 260 supporting the CMOS 240 and a sensor 270 on the support. Accordingly, Banna teaches the claimed support and sensor arrangement.
With respect to the limitation that the pixels are “configured to provide light distribution patterns based at least in part on sensor data received from the sensors” this limitation is functional in nature and describes the intended operation or use of the recited pixel system rather than imposing a structural limitation.
Banna discloses a plurality of light-emitting elements (pixels) 322 and associated circuitry 240 capable of receiving signals from the sensors 270 (see, e.g., fig. 3). Although Banna does not explicitly describe using sensor data to control light distribution patterns, the claimed functional language does not recite any specific structural features that would distinguish the claimed pixels from those disclosed in Banna.
The capability of providing light distribution patterns based on sensor data would have been inherently present in, and at least reasonably achievable by, the structure disclosed in Banna through routine control of the light-emitting elements using input signals, including signals from the sensors.
Thus, the “configured to provide” limitation is an intended use that does not distinguish over the prior art and an inherent capability of the disclosed system.
Regarding claim 8, Banna (see, e.g., fig. 2) shows that the top RDL 239 is attached to each pixel 322 using a copper post 328.
Regarding claim 10, Banna (see, e.g., fig. 3) shows the substrate further comprising a bottom RDL 239 opposite from the top RDL, the bottom RDL disposed between the via 338 and the CMOS 240.
Regarding claim 11, Banna (see, e.g., fig. 3) shows the bottom RDL 239 directly contacts the via 338.
Regarding claim 13, Banna (see, e.g., fig. 3) shows the system further comprising contact pads 257 directly contacting the CMOS 240 and the bottom RDL 239.
Regarding claim 14, Banna (see, e.g., fig. 3) shows the system further comprising a support 260 in direct contact with the CMOS 240 on a side of the CMOS opposing the contact pads 257.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Banna in view of Shimizu (US 2019/0195466).
Regarding claim 5, Banna shows most aspects of the instant invention (see paragraphs 33 above). He, however, fails to show the system further comprising a lens spaced apart from the pixels and arranged to direct light emitted by the pixels. Along these lines, Shimizu teaches that said lens would modify the light such as to efficiently meet a desired photometric specification (see, e.g., ¶[0043]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the lens of Shimizu in the system of Banna to efficiently meet a desired photometric specification.
Regarding claim 6, Shimizu (see, e.g., fig. 1B) teaches that the lens 1064 is disposed over all of the pixels.
Regarding claim 7, Shimizu (see, e.g., ¶0042/ll.3-6) teaches that the lens is disposed over only some of the pixels.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Banna in view of Wang (US 2006/0273307).
Regarding claim 15, Banna (see, e.g., fig. 3) does not explicitly disclose that the thickness of the inorganic substrate 301, the contact pads 257, the CMOS 240, and the support 260 add up to be between 5 and 25 microns.
Wang teaches that substrates and associated structures in electronic devices may be formed with a range of thicknesses depending on design requirements, and that such structures may be tailored in thickness to suit device needs (see, e.g., ¶ [0104], disclosing substrate thickness ranges and material flexibility).
It would have been obvious to one of ordinary skill in the art at the time of the invention to optimize the thicknesses of the substrate, contact pads, CMOS, and support in Banna to achieve a reduced overall thickness, including within the claimed range, as a matter of routine design choice motivated by the desire for compact, low-profile electronic devices.
The selection of a particular thickness within a known range or by routine optimization of a result-effective variable would have yielded predictable results, such as reduced device size and improved integration.
As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves the application of known techniques to improve similar devices in the same way.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Banna in view of Vampola (US 2018/0187839).
Regarding claim 19, Banna (see, e.g., fig. 3) teaches traces 239 connecting to the through vias 338 for electrically coupling the light emitting elements 322 to associated circuitry. However, Banna does not explicitly disclose that the traces connected to the through vias have a greater density toward a center of the pixel array compared to an outer edge.
Vampola teaches a metallized substrate including an array of pads connected by conductive traces that fan out toward the perimeter of the substrate (see, e.g., ¶¶ [0086]-[0090] and fig. 4). Vampola further teaches routing traces from inner pads through more complex paths, including diagonal and multi-directional routing between adjacent pads, in order to reach the perimeter.
Due to this fan-out routing configuration, traces associated with pads near the center of the array must traverse more constrained routing paths and pass between multiple adjacent pads, resulting in a higher concentration and density of traces in the central region of the array, whereas traces associated with pads near the perimeter have more direct paths and therefore lower routing density.
It would have been obvious to one of ordinary skill in the art at the time of the invention to implement the trace routing of Banna using the fan-out routing scheme taught by Vampola to efficiently route electrical connections from densely packed pixel arrays to external circuitry.
Such routing would inherently result in a trace density that is greater toward the center of the array than toward the outer edge, as a consequence of routing constraints in densely packed arrays.
As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves applying a known technique to a known device to yield predictable results.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Banna in view of Sung (US 2017/0345802).
Regarding claim 18, Banna (see, e.g., fig. 3) shows an adaptive illumination system but fails to show that the substrate 301 is disposed on a flexible printed circuit board.
Sung teaches a display device including a wiring substrate 1010 on which semiconductor light emitting device packages are mounted and electrically coupled via wiring electrodes (¶¶0136–0139). Sung further teaches that the wiring substrate may be implemented as a printed circuit board (PCB) and that the PCB may be either a non-flexible (¶0138) or a flexible PCB (¶0211).
It would have been obvious to one of ordinary skill in the art at the time of the invention to implement the substrate and external connection arrangement of Banna on a flexible printed circuit board as taught by Sung, since Sung explicitly teaches that PCBs, including flexible PCBs, are suitable wiring substrates for mounting and electrically interconnecting light emitting device packages.
Flexible PCBs and non-flexible PCBs represent are known alternative substrate configurations that achieve predictable results, namely providing electrical interconnection and support for light emitting devices.
As set forth in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007), a claimed invention is obvious where it involves “the substitution of one known element for another to obtain predictable results.”
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
April 3, 2026
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