DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites conflicting limitations that require correction. Lines 1-3 of this claim recites that the gate conductive layer comprises polycrystalline silicon and that the first gate structure and the second gate structure comprises a gate stack structure. Lines 4-5 the polycrystalline silicon layer is in direct contact with the gate oxide, thereby making the limitation “both that the polycrystalline silicon layer is located on the gate oxide layer” that precedes this statement unnecessary.
The conflicting issues arises in lines 6-7 of this claim, which states that the gate stack structure is located on the polycrystalline silicon layer and the gate stack structure is in direct contact with the polycrystalline silicon layer. As recited in claim 13, lines 8-9, the gate structure contains the first conductive layer and the gate oxide layer. Therefore, from the claim language, since the polycrystalline silicon layer is part of the gate structure, it is not possible for the gate structure to be on itself, thereby making these limitations indefinite.
For examination purposes, any prior art that teaches a polycrystalline gate electrode will meet the limitations of this claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 13-14, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori et al, US Patent Application Publication 20100167482 (newly submitted)
Regarding claim 1, Mori teaches a method for manufacturing a semiconductor device, comprising:
providing a substrate 1, wherein the substrate is provided with a first device area (pMos or nMos in MV or HV region or nMos in LV region) and, a second device area (pMos or nMos in MV or HV region or nMos in LV region), a third device area (pMos or nMos in MV or HV region or nMos in LV region) and a fourth device area (pMos in LV region), and a doping type of the first device area is different from a doping type of the second device area, a doping type of the third device area is different from a doping type of the fourth device area (figure 3A);
forming a gate oxide layer 36/39/44 which covers the first device area and, the second device area, the third device area and the fourth device area (figures 3B-3D);
forming, on the third device area, a mask layer 40 which covers the gate oxide layer;
removing the gate oxide layer which covers the fourth device area after the mask layer is formed (figure 3E);
forming a stress regulation layer 41 which covers the fourth device area by selective epitaxy after the gate oxide layer which covers the fourth device area is removed;
removing the mask layer and the gate oxide layer which cover the third device area (figure 3F);
forming a gate conductive layer 45 which covers the gate oxide layer;
forming a first gate structure on the first device area, wherein the first gate structure comprises the gate conductive layer 45 and the gate oxide layer 44 or 39/44 or 36/39/44; and
forming a second gate structure on the second device area, wherein the second gate structure comprises the gate conductive layer 45 and the gate oxide layer 39/44 or 36/39/44; and wherein in the first device area and the second device area, the gate conductive layer covers the gate oxide layer; and
forming a third gate structure 45 with 39/44 or 36/39/44on the third device area being exposed; and
forming a fourth gate structure 45 with 44/42a on the stress regulation layer (figures 3A-3J, which are then processed to form transistor structures, which is used to form transistors, as seen in figure 1O).
Regarding claim 2, Mori teaches forming the first gate structure on the first device area comprises: forming a gate stack structure 14/15 which covers the gate conductive layer 13, wherein the gate stack structure is in direct contact with the gate conductive layer; and removing part of the gate stack structure, part of the gate conductive layer, and part of the gate oxide layer to form the first gate structure, wherein the first gate structure is located on the first device area;
wherein forming the second gate structure 16 on the second device area comprises: forming the gate stack structure 14/15 which covers the gate conductive layer 13, wherein the gate stack structure is in direct contact with the gate conductive layer; and removing part of the gate stack structure, part of the gate conductive layer, and part of the gate oxide layer to form the second gate structure, wherein the second gate structure is located on the second device area (figures 1L-1O).
Regarding claim 4, Mori teaches the first device area is a P-type device area, and the second device area is an N-type device area (figure 1O)
Regarding claim 5, Mori teaches the third device area is an N-type device area, and the fourth device area is a P- type device area (figure 1O)
Regarding claim 13, Mori teaches a semiconductor device, comprising:
a substrate 1, wherein the substrate is provided with a first device area (pMos or nMos in MV or HV region or nMos in LV region) and a second device area (pMos or nMos in MV or HV region or nMos in LV region), a third device area (pMos or nMos in MV or HV region or nMos in LV region) and a fourth device area (pMos in LV region), and a doping type of the first device area is different from a doping type of the second device area, a doping type of the third device area is different from a doping type of the fourth device area;
a gate oxide layer 36/39/44 located on the first device area and the second device area;
a gate conductive layer 45 located on the gate oxide layer;
a first gate structure, wherein the first gate structure comprises the gate conductive layer 45 and the gate oxide layer 44, and the first gate structure is located on the first device area; and
a second gate structure, wherein the second gate structure comprises the gate conductive layer 45 and the gate oxide layer 39/44 or 36/39/44, and the second gate structure is located on the second device area;
a third gate structure located on the third device area of the substrate, wherein the third gate structure comprises an oxide layer 39 and a high dielectric material layer 44, wherein the oxide layer is in direct contact with the substrate, and the high dielectric material layer is in direct contact with the oxide layer;
a stress regulation layer 41 formed by selective epitaxy located on the fourth device area of the substrate, wherein the stress regulation layer is in direct contact with a surface of the substrate; and
a fourth gate structure located on the stress regulation layer, wherein the fourth gate structure comprises the oxide layer 42a and the high dielectric material layer 44, wherein the oxide layer is in direct contact with the stress regulation layer, and the high dielectric material layer is in direct contact with the oxide layer (figure 3J)
Regarding claim 14, Mori teaches the gate conductive layer 45 comprises a polycrystalline silicon layer, and the first gate structure and the second gate structure comprise a gate stack structure; the polycrystalline silicon layer is located on the gate oxide layer, and the polycrystalline silicon layer is in direct contact with the gate oxide layer; the gate stack structure is located on the polycrystalline silicon layer, and the gate stack structure is in direct contact with the polycrystalline silicon layer (figure 3J)
Regarding claim 16, Mori teaches a thickness of the gate oxide layer in the first device area (nPos or pMos in MV and HV regions, which is 39/44 or 36/39/44) and the second device area (nPos or pMos in MV and HV regions, which is 39/44 or 36/39/44) is greater than a thickness of the oxide layer 44 in the third device area (nMOs in LV region) and the fourth device area (pMOs in LV region).
Regarding claim 17, Mori fails to teach the thickness of the gate oxide layer 36 in a direction perpendicular to the substrate ranges from 4 nm to 8 nm [0132]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al, US Patent Application Publication 20100167482 (newly submitted)
Regarding claims 18, Mori fails to teach the thickness of the oxide layer in a direction perpendicular to the substrate ranges from 0.5 nm to 2 nm.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al, US Patent Application Publication 20100167482 (newly submitted) in view of Munden et al, US Patent 6,762,952 (as cited in previous Office Action)
Regarding claim 19, Mori teaches a memory, comprising: a storage cell and a control circuit coupled to the storage cell; the storage cell is configured to store data;
the control circuit is configured to control the storage cell to perform a read or write operation, wherein the control circuit comprises the semiconductor device.
a semiconductor device comprising: a substrate 10, wherein the substrate is provided with a first device area (pMos or nMos in MV or HV region or nMos in LV region) and, a second device area (pMos or nMos in MV or HV region or nMos in LV region), a third device area (pMos or nMos in MV or HV region or nMos in LV region) and a fourth device area (pMos in LV region), and a doping type of the first device area is different from a doping type of the second device area, a doping type of the third device area is different from a doping type of the fourth device area;
a gate oxide layer 36/39/44 located on the first device area and the second device area;
a gate conductive layer 45 located on the gate oxide layer;
a first gate structure, wherein the first gate structure comprises the gate conductive layer 45 and the gate oxide layer 36/39/44 or 39/44, and the first gate structure is located on the first device area; and
a second gate structure, wherein the second gate structure comprises the gate conductive layer 45 and the gate oxide layer36/39/44 or 39/44, and the second gate structure is located on the second device area;
a third gate structure located on the third device area of the substrate, wherein the third gate structure comprises an oxide layer 39 and a high dielectric material layer 44, wherein the oxide layer is in direct contact with the substrate, and the high dielectric material layer is in direct contact with the oxide layer;
a stress regulation layer 41 formed by selective epitaxy located on the fourth device area of the substrate, wherein the stress regulation layer is in direct contact with a surface of the substrate; and
a fourth gate structure located on the stress regulation layer, wherein the fourth gate structure comprises the oxide layer 42a and the high dielectric material layer 44, wherein the oxide layer is in direct contact with the stress regulation layer, and the high dielectric material layer is in direct contact with the oxide layer (figure 3J).
Mori fails to teach a storage cell and a control circuit coupled to the storage cell; the storage cell is configured to store data and the control circuit is configured to control the storage cell to perform a read or write operation, wherein the control circuit comprises the semiconductor device.
However, Munden teaches a completed memory device, which is a conventionally-used semiconductor device, which includes a storage cell and a control circuit coupled to the storage cell (column 3, lines 45-48); the storage cell is configured to store data (column 3, lines 61-62); the control circuit is configured to control the storage cell to perform a read or write operation (column 3, lines 45-48), wherein the control circuit comprises the semiconductor device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Munden with that of Mori because a memory device is one of several conventionally-used semiconductor device that uses the disclosed reference of Mori
Regarding claim 20, Munden in view of Mori teaches storage cell comprises: a transistor and a charge storage coupled to the transistor (column 3, lines 61-62 of Munden, which has a transistor, which is taught by Mori).
Allowable Subject Matter
The indicated allowability of previous claims 3 and 5 is withdrawn in view of the newly discovered reference(s) to Mori et al, US Patent Application Publication 20100167482. Rejections based on the newly cited reference(s) are as stated above.
Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art fails to anticipate or render obvious the claimed invention including “...forming a metal gate structure which covers the first conductive layer; forming a first mask pattern on the metal gate structure; and removing part of the metal gate structure, part of the first conductive layer, part of the second gate stack layer, part of the high dielectric material layer, and part of the oxide layer based on the first mask pattern to form the third gate structure..” in combination with the remaining limitations. Claims 8-10 are dependent upon claim 6 and are therefore allowable.
With regards to claim 6, Mori meet the limitations of “forming the third gate structure on the exposed third device area (nmos area in LV region in figure 4C) comprises: forming successively an oxide layer 39, a high dielectric material layer 44 and a first gate stack layer 51a which cover the substrate (figure 4C); removing the first gate stack layer in the third device area (figure 4D); forming successively a second gate stack layer 58 and a first conductive layer 59 which cover the high dielectric material layer 57” but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 6 and 8-10 have been found to be allowable.
Regarding claim 7, the prior art fails to anticipate or render obvious the claimed invention including “...forming successively a second gate stack layer and a first conductive layer which cover the first gate stack layer; forming a metal gate structure which covers the first conductive layer; forming a second mask pattern on the metal gate structure; and removing part of the metal gate structure, part of the first conductive layer, part of the second gate stack layer, part of the first gate stack layer, part of the high dielectric material layer, and part of the oxide layer based on the second mask pattern to form the fourth gate structure...” in combination with the remaining limitations.
With regards to claim 7, Mori meet the limitations of “forming the fourth gate structure on the stress regulation layer comprises: forming successively an oxide layer 42a, a high dielectric material layer 44 and a first gate stack layer 45 which cover the stress regulation layer”, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 6-8 have been found to be allowable.
Regarding claim 11, the prior art fails to anticipate or render obvious the claimed invention including “...the gate stack structure comprises a fifth barrier layer and a fifth conductive layer; wherein forming the gate stack structure which covers the gate conductive layer comprises: forming the fifth barrier layer which covers the polycrystalline silicon layer; and forming the fifth conductive layer which covers the fifth barrier layer...” in combination with the remaining limitations. Claim 12 is dependent upon claim 11 and is therefore allowable.
With regards to claim 11, the cited prior art(s) of record teach all of the limitations presented, but fail to recite the limitation above. Further, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 11-12 have been found to be allowable.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4-14, and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899