DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 10/21/2025 in response to the Office Action mailed on 07/29/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into
fully consideration all the amendments.
Response to Arguments
On page 12 of the remarks filed on 10/21/2025, with respect to the 102 Rejection of Claim 15, Applicant argues that Darmawikarta does not disclose "a lower encapsulant upper side contacting the upper substrate lower side and a lower encapsulant lower side contacting the lower substrate upper side.". This argument has been fully considered but is not persuasive. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation (BRI), the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim. As such, the term “contacting” as recited in Claim 15 broadly includes contacting through other intermediate layers. Thus, Darmawikarta teaches the lower encapsulant 133-1 contacts the upper substrate 148 through the layers 116, 112 and contacts the lower substrate 102 through the underfill 127 (see annotated Fig. 1). Therefore, the rejection of Claim 15 and all dependent claims in view of Darmawikarta is maintained.
Applicant’s arguments, see pages 13-14 of the remarks filed on 10/21/2025, with respect to the rejection of claim 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Darmawikarta/Kim and newly found prior art reference of Wu. Wu discloses a method of manufacturing an electronic device, the method comprising removing the alignment pads 55 (see Fig. 4F: 55 and Fig. 4G, column 3, lines 37-38), and the combination of Darmawikarta/Kim/Wu implicitly teach that removing the alignment pads would expose ends of the connect die lower interconnects. A new ground of rejection is also made for all dependent claims in view of Darmawikarta/Kim and newly found prior art reference of Wu.
On page 14 of the remarks filed on 10/21/2025, with respect to the 103 Rejection of Claim 10, Applicant argues that Chow’s die 1104 is not a dielectric base block as set forth in claims 10-13 and that the bottom side of die 1104 is adhered to substrate 1102 via adhesive layer 1103 and therefore is not coplanar with the bottom side of the encapsulant 1114. These arguments have been fully considered but is not persuasive. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation (BRI), the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim. As such, the semiconductor die 1104 together with the adhesive layer 1103 can be broadly interpreted as the dielectric base block. According to paragraph 0058 and 0018 of Chow, the die 1104 is made of silicon and the die adhesive layer 1103 is made of epoxy with silicon and thus the bulk silicon of the die and the epoxy with silicon adhesive layer together can be broadly treated as a base dielectric block supporting multiple metal layers or embedded conductors. Further, Chow teaches wherein a lower side of the lower encapsulant 1114 is coplanar with a lower side of the dielectric base block 1104, 1103 (Fig. 11: 1104, 1103, 1106, 1114, paragraph 0072, 0073). Therefore, the rejection of Claim 15 and all dependent claims in view of Darmawikarta/Chow is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Darmawikarta et al. (US 20230197661 A1).
Regarding Claim 15, Darmawikarta et al. discloses an electronic device 100 comprising:
a lower substrate 102 comprising a lower substrate upper side and a lower substrate lower side (see annotated Fig. 1 of Darmawikarta et al.: 102, paragraph 0021);
an upper substrate 148 comprising an upper substrate upper side and an upper substrate lower side (see annotated Fig. 1 of Darmawikarta et al.: 148, paragraph 0021);
a first electronic component 114-2 and a second electronic component 114-3 coupled to the upper substrate upper side (see annotated Fig. 1 of Darmawikarta et al.: 114-2, 114-2, paragraph 0021);
a first device interconnect 152-1 and a second device interconnect 152-2 that couple the lower substrate upper side to the upper substrate lower side (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, paragraph 0021);
and a connect die 114-1 coupled to the lower substrate upper side laterally between the first device interconnect 152-1 and the second device interconnect 152-2, wherein the connect die 114-1 electrically couples the first electronic component 114-2 to the second electronic component 114-3 (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, 114-2, 114-3, paragraph 0021).
and a lower encapsulant 133-1 comprising a lower encapsulant upper side contacting the upper substrate 148 lower side and a lower encapsulant lower side contacting the lower substrate 102 upper side, wherein the lower encapsulant 133-1 encapsulates the connect die 114-1 (See annotated Fig. 1 of Darmawikarta et al.: 133-1, 148, 114-1, paragraph 0029).
Note that the lower encapsulant 133-1 contacts the upper substrate 148 through the layers 116, 112 and contacts the lower substrate 102 through the underfill 127 (see annotated Fig. 1).
Regarding Claim 18, Darmawikarta et al. teaches the electronic device of claim 15, comprising: first component fine-pitch interconnects 130-1 and first component coarse-pitch interconnects 130-2 that coupled the first electronic component 114-2 to the upper substrate 148; and second component fine-pitch interconnects 130-3 and second component coarse-pitch interconnects 130-4 that coupled the second electronic component 114-3 to the upper substrate 148; and wherein the connect die 114-1 couples the first electronic component 114-2 to the second electronic component 114-3 via the first component fine-pitch interconnects 130-1 and the second component fine-pitch interconnects 130-3 (See annotated Fig. 1 of Darmawikarta et al.: 130-1, 130-2, 130-3, 130-4, 114-1, 114-2, 114-3, paragraph 0021).
Regarding Claim 19, Darmawikarta et al. teaches the electronic device of claim 15, comprising: an underfill 127 that fills a first gap between the first electronic component 114-2 and the upper substrate 148 and a second gap between the second electronic component 114-3 and the upper substrate 148 (see Fig. 1: 127, 148, 114-2, 114-3, paragraph 0032).
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Annotated Fig. 1 of Darmawikarta et al. (US 20230197661 A1)
Regarding Claim 20, Darmawikarta et al. teaches The electronic device of claim 19, comprising: an upper encapsulant 133-2 that encapsulates the first electronic component 114-2, the second electronic component 114-3, and the underfill 127; and wherein the lower encapsulant 133-1 encapsulates the first device interconnect 152-1 and the second device interconnect 152-2 (See annotated Fig. 1 of Darmawikarta et al.: 133-1, 133-2, 127, 114-1, 114-2, 114-3, 152-1, 152-2, paragraph 0029).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Kim et al. (US 20160247767 A1) and Wu (US 6010945).
Regarding Claim 1, Darmawikarta et al. teaches a method of manufacturing an electronic device, the method comprising:
providing a first device interconnect 152-1, a second device interconnect 152-1, a connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, paragraph 0021),
encapsulating the connect die 114-1, the first device interconnect 152-1, and the second device interconnect 152-2 with a lower encapsulant 133-1 (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, 133-1, paragraph 0029);
providing an upper substrate 148 on the lower encapsulant 133-1 such that a conductive structure 194, 196 of the upper substrate 148 is coupled to the first device interconnect 152-1, the second device interconnect 152-2, and connect die upper interconnects 124 of the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 148, 133-1, 194, 196, 152-1, 152-2, 114-1, 124, paragraph 0021);
and coupling a first electronic component 114-2 and a second electronic component 114-3 to the upper substrate 148 such that the first electronic component 114-2 is electrically coupled to the second electronic component 114-3 via the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 114-1, 114-2, 114-3, 148, paragraph 0021).
Darmawikarta et al. fails to teach
providing alignment pads, wherein the alignment pads are laterally between the first device interconnect and the second device interconnect;
coupling connect die lower interconnects of a connect die to the alignment pads;
and removing the alignment pads to expose ends of the connect die lower interconnects.
However, Kim et al. teaches a method of manufacturing an electronic device, the method comprising providing, alignment pads 210, wherein the alignment pads 210 are laterally between the first device interconnect 220 and the second device interconnect 220, and coupling connect die lower interconnects 320 of a connect die 310 to the alignment pads 210 (Fig. 2B: 220, 210, Fig. 2C: 210, 220, 320, paragraph 0038, 0043).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Darmawikarta et al. and Kim et al. in order to provide alignment pads, wherein the alignment pads are laterally between the first device interconnect and the second device interconnect, and couple connect die lower interconnects of a connect die to the alignment pads. Doing so would ensure proper alignment of the connect die on the carrier substrate.
Further, Wu teaches a method of manufacturing an electronic device, the method comprising removing the alignment pads 55 (see Fig. 4F: 55 and Fig. 4G, column 3, lines 37-38).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Darmawikarta et al., Kim et al. and Wu in order to remove the alignment pads of Kim placed in the electronic device of Darmawikarta et al. Doing so would expose the ends of the connect die lower interconnects allowing them to interface with other electronics.
Furthermore, a person of ordinary skill in the art would have recognized that when the step of removing the alignment pads taught by Wu is incorporated into the manufacturing method of Darmawikarta et al./Kim et al., removing the alignment pads of Kim et al. would inevitably expose ends of the connect die lower interconnects of Kim et al.
Regarding Claim 4, Darmawikarta et al. teaches the method of claim 1, wherein coupling the first electronic component 114-2 and the second electronic component 114-3 to the upper substrate 148 comprises: coupling the first electronic component 114-2 to the upper substrate 148 via first component fine- pitch interconnects 130-1 and first component coarse-pitch interconnects 130-2 such that the first electronic component 114-2 is coupled to the connect die 114-1 via the first component fine-pitch interconnects 130-1; and coupling the second electronic component 114-3 to the upper substrate 148 via second component fine-pitch interconnects 130-3 and second component coarse-pitch interconnects 130-4 such that the second electronic component 114-3 is coupled to the first electronic component 114-1 via the second component fine- pitch interconnects 130-3 and the connect die 114-1 (See annotated Fig. 1 of Darmawikarta et al.: 130-1, 130-2, 130-3, 130-4, 114-1, 114-2, 114-3, 148, paragraph 0021).
Regarding Claim 5, the combination of Darmawikarta et al., Kim et al. and Wu teaches , the method of claim 1, comprising, after removing the alignment pads (as taught by Wu, see Fig. 4F: 55 and Fig. 4G, column 3, lines 37-38), providing a lower substrate 102 on a lower side of the lower encapsulant 133-1 such that a conductive structure 146 of the lower substrate 102 is coupled to the first device interconnect 152-1, the second device interconnect 152-2 (as taught by Darmawikarta et al. in annotated Fig. 1: 152-1, 152-2, 133-1, 102, 146, paragraph 0021), and the exposed ends of the connect die lower interconnects 320 (as taught by Kim et al. in Fig. 2C: 320, paragraph 0043 and Wu in Fig. 4F: 55 and Fig. 4G, column 3, lines 37-38).
Regarding Claim 6, Darmawikarta et al. fails to teach the method of claim 5, comprising providing external interconnects on a lower side of the lower substrate such that at least one of the external interconnects is electrically coupled to at least one of the connect die lower interconnects via the lower substrate.
However, Kim et al. teaches providing external interconnects 30 on a lower side of the lower substrate 100 such that at least one of the external interconnects 30 is electrically coupled to at least one of the connect die lower interconnects 320 via the lower substrate 100 (Fig. 2H: 30, 100, 320, paragraph 0084).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Darmawikarta et al. and Kim et al. in order to come up with the claimed invention. Doing so would enable the connect die to interface with external electronic components.
Regarding Claim 7, Darmawikarta et al. teaches the method of claim 1, comprising filling a first gap between the first electronic component 114-2 and the upper substrate 148 and a second gap between the second electronic component 114-3 and the upper substrate 148 with an underfill 127 (Fig. 1: 114-2, 114-3, 127, 148, paragraph 0032).
Regarding Claim 8, Darmawikarta et al. teaches the method of claim 1, comprising: filling a first gap between the first electronic component 114-2 and the upper substrate 148 and a second gap between the second electronic component 114-3 and the upper substrate 148 with an underfill 127 (Fig. 1: 114-2, 114-3, 127, 148, paragraph 0032); and encapsulating the first electronic component 114-2, the second electronic component 114-3, and the underfill 127 with an upper encapsulant 133-2 (Fig. 1: 133-2, 127, 114-2, 114-3, paragraph 0053).
Regarding Claim 9, the combination of Darmawikarta et al. and Kim et al. teaches the method of claim 1, wherein:
the connect die 114-1 comprises a connect die body comprising a connect die body upper side and a connect die body lower side (as taught by Darmawikarta et al. in Fig. 1: 114-1, paragraph 0021);
connect die interconnects 115 that pass between the connect die body upper side and the connect die body lower side (as taught by Darmawikarta et al. in Fig. 1: 115, 114-1, paragraph 0020);
connect die pads 122 on the connect die body lower side and coupled to lower ends of the connect die interconnects 115 (as taught by Darmawikarta et al. in Fig. 1: 122, 115, paragraph 0020);
the connect die lower interconnects 320 are on the connect die body lower side (as taught by Kim et al. in Fig. 2C: 320, paragraph 0043) and coupled to respective ones of the connect die pads 122 (as taught by Darmawikarta et al. in Fig. 1: 122, paragraph 0020);
the connect die upper interconnects 124 are on the connect die body upper side (as taught by Darmawikarta et al. in Fig. 1: 124, paragraph 0020);
and one or more of the connect die upper interconnects 124 (as taught by Darmawikarta et al.) are coupled to one or more of the connect die lower interconnects 320 (as taught by Kim et al. in Fig. 2C: 320) via the connect die interconnect 115 through the connect die body and the connect die pads 122 (as taught by Darmawikarta et al. in Fig. 1: 122, 115, paragraph 0020).
Darmawikarta et al. fails to teach a connect die insulating layer on the connect die body lower side, wherein the connect die insulating layer laterally encapsulates lateral sidewalls of the connect die pads.
However, Kim et al. teaches a connect die insulating layer 340 on the connect die body lower side (of connect die 310, see Fig. 2C: 340, 310, paragraph 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. and Kim et al. in order to have a connect die insulating layer on the connect die body lower side. By doing so, the insulating layer would protect the contact die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, which may occur during or after a semiconductor package fabricating process, as recognized by Kim et al. (paragraph 0051).
Further a person of ordinary skill in the art would have recognized that when the connect die insulating layer 340 of Kim et al. is disposed under the connect die 114-1 of Darmawikarta et al., the connect die insulating layer 340 of Kim et al. would laterally encapsulate lateral sidewalls of the connect die pads 122 of Darmawikarta et al. (see Fig. 1: 114-1, 122 of Darmawikarta et al. and Fig. 2C: 340 of Kim et al.).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Kim et al. (US 20160247767 A1) and Wu (US 6010945), as applied to Claim 1 above, further in view of Yang (US 6759307 B1).
Regarding Claim 2, the combination of Darmawikarta et al. and Kim et al. teaches the method of claim 1, wherein: the first device interconnect 152, the second device interconnect 152 (as taught by Darmawikarta et al.), and the alignment pads 210 (as taught by Kim et al.) are provided on an upper side of a device carrier 105/100 (see Fig. 4A: 152, 105, and paragraph 0044 of Darmawikarta et al., Fig. 2B: 210, 100, and paragraph 0038 of Kim et al.).
Furthermore, in contrast to Darmawikarta et al., Kim et al. teaches filling, with an interface material 340, a gap between a lower side of the connect die 310 and the upper side of the device carrier 100 (Fig. 2C: 340, 310, 100, paragraph 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. and Kim et al. in order to fill, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier. By doing so, the interface material would protect the contact die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, as recognized by Kim et al. (paragraph 0051).
The combination of Darmawikarta et al. and Kim et al. fails to teach or explicitly teach the following:
the method comprises: providing a first alignment feature and a second alignment feature on the upper side of the device carrier, wherein the first alignment feature is laterally between the first device interconnect and the alignment pads and the second alignment feature is laterally between the second device interconnect and the alignment pads;
that the interface material is laterally retained between an inner lateral side of the first alignment feature and an inner lateral side of the second alignment feature.
However, Yang teaches a method of manufacturing an electronic device, the method comprises
providing a first alignment feature 30 (to the left of die 12b) and a second alignment feature 30 (to the left of die 12b) on the upper side of the device carrier 40, wherein the first alignment feature 30 and the second alignment feature 30 are laterally between the first device interconnect 32 (to the left of die 12b) and the second device interconnect 32 (to the right of die 12b) (Fig. 4: 30, 12b, 40, column 7, lines 56-67, column 7, lines 1-6).
Therefore, a person of ordinary skill in the art, using the combined teachings of Darmawikarta et al., Kim et al. and Yang, would have adapted the alignment feature of Yang in the electronic device of Darmawikarta et al./Kim et al., so as to provide a first alignment feature and a second alignment feature on the upper side of the device carrier. Doing so would prevent the overflow of interface material, as recognized by Yang (column 8, lines 7-15).
Furthermore, a person of ordinary skill in the art would have recognized that when the interface material 340 of Kim et al. and the alignment features 30 of Yang are disposed on the electronic device of Darmawikarta et al.:
the first alignment feature 30 of Yang would laterally be between the first device interconnect 152-1 of Darmawikarta et al. and the alignment pads 210 of Kim et al. and the second alignment feature 30 of Yang will laterally be between the second device interconnect 152-2 of Darmawikarta et al. and the alignment pads 210 of Kim et al.
the interface material 340 will be laterally retained between an inner lateral side of the first alignment feature 30 of Yang and an inner lateral side of the second alignment feature 30 of Yang. (Also note that in a different embodiment shown in Fig 7, Yang teaches an interface material 13a retained between an inner lateral side of the alignment feature 30)
Regarding Claim 3, the combination of Darmawikarta et al. and Kim et al. teaches the method of claim 1, wherein: the first device interconnect 152, the second device interconnect 152 (as taught by Darmawikarta et al.), and the alignment pads 210 (as taught by Kim et al.) are provided on an upper side of a device carrier 105/100 (see Fig. 4A: 152, 105, and paragraph 0044 of Darmawikarta et al., Fig. 2B: 210, 100, and paragraph 0038 of Kim et al.).
Furthermore, in contrast to Darmawikarta et al., Kim et al. teaches filling, with an interface material 340, a gap between a lower side of the connect die 310 and the upper side of the device carrier 100 such that the interface material 340 encapsulates the connect die lower interconnects 320 and the alignment pads 210 (Fig. 2C: 340, 310, 100, 320, 210, paragraph 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. and Kim et al. in order to fill, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier such that the interface material encapsulates the connect die lower interconnects and the alignment pads. By doing so, the interface material would protect the contact die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, as recognized by Kim et al. (paragraph 0051).
The combination of Darmawikarta et al. and Kim et al. fails to teach the method comprises: providing a first alignment feature and a second alignment feature on the upper side of the device carrier, wherein the first alignment feature is laterally between the first device interconnect and the alignment pads and the second alignment feature is laterally between the second device interconnect and the alignment pads.
However, Yang teaches a method of manufacturing an electronic device, the method comprises
providing a first alignment feature 30 (to the left of die 12b) and a second alignment feature 30 (to the left of die 12b) on the upper side of the device carrier 40, wherein the first alignment feature 30 and the second alignment feature 30 are laterally between the first device interconnect 32 (to the left of die 12b) and the second device interconnect 32 (to the right of die 12b) (Fig. 4: 30, 12b, 40, column 7, lines 56-67, column 7, lines 1-6).
Therefore, a person of ordinary skill in the art, using the combined teachings of Darmawikarta et al., Kim et al. and Yang, would have adapted the alignment feature of Yang in the electronic device of Darmawikarta et al./Kim et al., so as to provide a first alignment feature and a second alignment feature on the upper side of the device carrier. Doing so would prevent the overflow of interface material, as recognized by Yang (column 8, lines 7-15).
Furthermore, a person of ordinary skill in the art would have recognized that when the interface material 340 of Kim et al. and the alignment features 30 of Yang are disposed on the electronic device of Darmawikarta et al., the first alignment feature 30 of Yang would laterally be between the first device interconnect 152-1 of Darmawikarta et al. and the alignment pads 210 of Kim et al. and the second alignment feature 30 of Yang will laterally be between the second device interconnect 152-2 of Darmawikarta et al. and the alignment pads 210 of Kim et al.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Chow et al. (US 20080164618 A1).
Regarding Claim 10, Darmawikarta et al. teaches a method of manufacturing an electronic device, the method comprising:
providing a first device interconnect 152-1, a second device interconnect 152-2, a connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, paragraph 0021),
encapsulating the connect die 114-1, the first device interconnect 152-1, and the second device interconnect 152-2 with a lower encapsulant 133-1 (see annotated Fig. 1 of Darmawikarta et al.: 133-1, 152-1, 152-2, 114-1, paragraph 0021, 0029);
providing an upper substrate 148 on the lower encapsulant 133-1 such that a conductive structure 194, 196 of the upper substrate 148 is coupled to the first device interconnect 152-1, the second device interconnect 152-2, and connect die upper interconnect 124 of the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 148, 152-1, 152-2, 114-1, 124, paragraph 0021);
and coupling a first electronic component 114-2 and a second electronic component 114-2 to the upper substrate 148 such that the first electronic component 114-2 is electrically coupled to the second electronic component 114-3 via the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 148, 152-1, 152-2, 114-1, 114-2, 114-3, paragraph 0021).
Darmawikarta et al. fails to teach providing and a dielectric base block, wherein the dielectric base block is laterally between the first device interconnect and the second device interconnect, and coupling a lower side of a connect die to an upper side of the dielectric base block, wherein a lower side of the lower encapsulant is coplanar with a lower side of the dielectric base block.
However, Chow et al. teaches a method of manufacturing an electronic device comprising providing a dielectric base block 1104, 1103 and coupling a lower side of a connect die 1106 to an upper side of the dielectric base block 1104, 1103, wherein a lower side of the lower encapsulant 1114 is coplanar with a lower side of the dielectric base block 1104, 1103 (Fig. 11: 1104, 1103, 1106, 1114, paragraph 0072, 0073).
Note that the die 1104 and adhesive layer 1103 of Fig. 11 together is interpreted as the dielectric base block.
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. with the teachings of Chow et al. in order to have a dielectric base block and couple a lower side of the connect die to an upper side of the dielectric base block such that a lower side of the lower encapsulant is coplanar with a lower side of the dielectric base block. Doing so would aid in proper alignment of the connect die on the carrier substrate.
Further, a person of ordinary skill in the art would have recognized that when the base block 1104 of Chow et al. (see Fig. 11) is disposed in the electronic device of Darmawikarta et al., the base block will laterally be in between the first device interconnect 152-1 and the second device interconnect 152-2 of Darmawikarta et al. (see annotated Fig. 1).
Regarding Claim 11, Chow et al. teaches the method of claim 10, wherein coupling the lower side of the connect die 1106 comprises coupling the lower side of the connect die 1106 to the upper side of the dielectric base block 1104, 1103 through an interface material 1105 (Fig. 11: 1104, 1103, 1105, 1106, paragraph 0072).
Regarding Claim 12, Chow et al. teaches the method of claim 10, wherein coupling the lower side of the connect die 1106 comprises coupling the lower side of the connect die 1106 to the upper side of the dielectric base block 1104, 1103 through a die attach film, an adhesive film 1105, and/or an adhesive tape (Fig. 11: 1104, 1103, 1105, 1106, paragraph 0072).
Regarding Claim 13, Darmawikarta et al. teaches the method of claim 10, wherein coupling the first electronic component 114-2 and the second electronic component 114-3 to the upper substrate 148 comprises: coupling a lower side of the first electronic component 114-2 to the upper substrate 148 via first component interconnects 130 (Fig. 1: 114-2, 114-3, 148, 130, paragraph 0021).
Darmawikarta et al. fails to teach coupling an upper side of the second electronic component to the upper substrate via bond wires.
However, Chow et al teaches coupling an upper side of a second electronic component 1108 to the substrate 1102 via bond wires 1118 (Fig. 11: 1108, 1102, 1118, paragraph 0072).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. with the teachings of Chow et al. in order to couple an upper side of the second electronic component to the upper substrate via bond wires. Doing so would simplify the semiconductor manufacturing and packaging process flow as wire bonding can be done after die attach allowing for more flexible assembly.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Chow et al. (US 20080164618 A1), as applied to Claim 10 above, further in view of Kim et al. (US 20160247767 A1).
Darmawikarta et al. teaches the method of claim 10, comprising: providing a lower substrate 102 on a lower side of the lower encapsulant 133-1 such that a conductive structure 146 of the lower substrate 102 is coupled to the first device interconnect 152-1 and the second device interconnect 152-2 (as taught by Darmawikarta et al. in annotated Fig. 1: 152-1, 152-2, 133-1, 102, 146, paragraph 0021).
Darmawikarta et al. fails to teach providing external interconnects on a lower side of the lower substrate such that at least one of the external interconnects is electrically coupled to the first device interconnect via the lower substrate.
However, Kim et al. teaches providing external interconnects 30 on a lower side of the lower substrate 100 such that at least one of the external interconnects 30 is electrically coupled to the first device interconnect 220 via the lower substrate 100. (Fig. 2H: 30, 100, 320, 220, paragraph 0084).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Darmawikarta et al. and Kim et al. in order to come up with the claimed invention. Doing so would enable the connect die to interface with external electronic components.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), as applied to Claim 15 above, further in view of Kim et al. (US 20160247767 A1).
Darmawikarta et al. teaches the electronic device of claim 15, wherein the connect die 114-1 comprises:
a connect die body comprising a connect die body upper side and a connect die body lower side (see Fig. 1: 114-1, paragraph 0021);
connect die interconnects 115 that pass between the connect die body upper side and the connect die body lower side (see Fig. 1: 115, paragraph 0020);
connect die pads 122 on the connect die body lower side and coupled to lower ends of the connect die interconnects 115 (Fig. 1: 122, 115, paragraph 0020);
connect die upper interconnects 124 on the connect die body upper side (see Fig. 1: 124, paragraph 0020);
Darmawikarta et al. fails to teach:
a connect die insulating layer on the connect die body lower side, wherein the connect die insulating layer laterally encapsulates lateral sidewalls of the connect die pads;
and connect die lower interconnects on the connect die body lower side and coupled to respective ones of the connect die pads;
and wherein one or more of the connect die upper interconnects are coupled to one or more of the connect die lower interconnects via the connect die interconnects through the connect die body and the connect die pads.
However, Kim et al. teaches an electronic device comprising a connect die insulating layer 340 on the connect die body lower side of a connect die 310, and connect die lower interconnects 320 on the connect die body lower side (Fig. 2C: 310, 320, 340, paragraphs 0043 and 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. and Kim et al. in order to have a connect die insulating layer and connect die lower interconnects on the connect die body lower side. By doing so, the insulating layer would protect the contact die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, as recognized by Kim et al. (paragraph 0051). Additionally, the connect die lower interconnects would electrically and mechanically couple the connect die to the package substrate.
Further a person of ordinary skill in the art would have recognized that when the connect die insulating layer 340 and the connect die lower interconnects 320 of Kim et al. are disposed under the connect die 114-1 of Darmawikarta et al.,
the connect die insulating layer 340 of Kim et al. would laterally encapsulate lateral sidewalls of the connect die pads 122 of Darmawikarta et al. (see Fig. 1: 114-1, 122 of Darmawikarta et al. and Fig. 2C: 340 of Kim et al.)
the connect die lower interconnects 320 of Kim et al. would be coupled to respective ones of the connect die pads 122 of Darmawikarta et al. (see Fig. 1: 114-1, 122 of Darmawikarta et al. and Fig. 2C: 340 of Kim et al.)
and wherein one or more of the connect die upper interconnects 124 of Darmawikarta et al. will be coupled to one or more of the connect die lower interconnects 320 of Kim et al. via the connect die interconnects 115 of Darmawikarta et al. through the connect die body and the connect die pads 122 of Darmawikarta et al. (see Fig. 1: 114-1, 122 of Darmawikarta et al. and Fig. 2C: 340 of Kim et al.)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), as applied to Claim 15 above, further in view of Chow et al. (US 20080164618 A1).
Darmawikarta et al. fails to teach the electronic device of claim 15, a base block laterally between the first device interconnect and the second device interconnect; and wherein a lower side of the connect die is coupled to an upper side of the base block.
However, Chow et al. teaches an electronic device comprising a base block 1104, 1103 and wherein a lower side of the connect die 1106 is coupled to an upper side of the base block 1104, 1103 (Fig. 11: 1104, 1103, 1106, paragraph 0072).
Note that the die 1104 and adhesive layer 1103 together is interpreted as the base block.
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al. with the teachings of Chow et al. in order to have a base block such that a lower side of the connect die is coupled to an upper side of the base block. Doing so would aid in proper alignment of the connect die on the carrier substrate.
Further, a person of ordinary skill in the art would have recognized that when the base block 1104, 1103 of Chow et al. (see Fig. 11) is disposed in the electronic device of Darmawikarta et al., the base block will laterally be in between the first device interconnect 152-1 and the second device interconnect 152-2 of Darmawikarta et al. (see annotated Fig. 1 of Darmawikarta et al.).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 03/10/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 20, 2026