DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/23/2026 has been entered.
Response to Amendment
An amendment filed on 06/23/2026 in response to the Office Action mailed on 03/23/2026 is
being acknowledged and entered into the record. The present Non-Final rejection is made by taking into
fully consideration all the amendments.
Response to Arguments
On pages 12-13 of the remarks filed on 06/23/2026, with respect to the 102 Rejection of Claims 15 and 18-20, Applicant argues that Darmawikarta does not disclose " a lower encapsulating material providing a lower encapsulating material upper side directly contacting the upper substrate lower side and a lower encapsulating material lower side directly contacting the lower substrate upper side, wherein the lower encapsulating material encapsulates the connect die.". This argument has been fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 102 rejection is made for Claim 15 in view of newly found prior art reference of Guo et al. As outlined in the rejection below, Guo et al. teaches the above limitations. Further, a new ground of 102 rejection is made for dependent claims 19 and 20 in view of Guo et al. and a new ground of 103 rejection is made for dependent claim 18 in view of Guo et al. and previously cited Darmawikarta et al.
On pages 14-16 of the remarks filed on 06/23/2026, with respect to the 103 Rejection of Claim 1, Applicant argues that Kim does not teach using its pads 210 to align its semiconductor die 310 to the interposer 100 or that its pads 210 may aid in aligning its semiconductor die 310 on the interposer 100 but rather teaches that the pads 210 are used to electrically connect the semiconductor die 310 to circuit pattern 131 of the interposer 100. This argument has been fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made for Claim 1 in view of previously applied prior art reference of Darmawikarta and newly found prior art reference of Hwang et al. Hwang et al. teaches pads 160 aiding in the alignment of the chip pads 210 of the die 200 (see Fig. 16: 160, 200, 210, paragraph 0035-0038, 0057).
On pages 14-16 of the remarks filed on 06/23/2026, with respect to the 103 Rejection of Claim 1, Applicant argues that Darmawikarta die 114-1 does not make electrical connections to circuit patterns of its carrier 105 and does not indicate that there are any alignment issues to overcome with regard to placing its die 114-1 on the carrier 105 and thus one skilled in the art would not find it obvious to combine Darmawikarta and Kim in the proposed manner. This argument is fully considered but is not persuasive. One cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As such, while Darmawikarta alone does not teach electrical connections to circuit patterns of its carrier, the combination of Darmawikarta and Hwang teaches these limitations as outlined in the rejection of Claim 1 below. Furthermore, in semiconductor packaging, die alignment is a well-known consideration as misalignment can lead to reliability issues. Thus, a person of ordinary skill in the art would have been motivated to incorporate known alignment pads to the device of Darmawikarta/Hwang to improve placement accuracy even if the reference does not expressly identify any alignment problem. Therefore, Darmawikarta is still relied upon to teach some of the limitations of Claim 1.
On pages 16-17of the remarks filed on 06/23/2026, with respect to the 103 Rejection of Claim 1, Applicant argues that Wu does not disclose removal of an alignment pad but a "method for preventing alignment marks from disappearing after chemical mechanical polishing and the alignment marks are raised portions of a device upper surface that are used to optically align subsequent processing steps. This argument has been fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made for Claim 1 in view of previously applied prior art reference of Darmawikarta and newly found prior art reference of Ryan et al. Ryan et al. teaches removal of alignment pads as outlined in the rejection below.
On pages 17-18 of the remarks filed on 06/23/2026, with respect to the 103 Rejection of Claim 10, Applicant argues that Chow’s dielectric base block comprising adhesive layer 1103 and die 1104 together lacks a dielectric material that extends from a lower side of the block to an upper side of the proposed block. This argument has been fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 102 rejection is made for Claim 1 in view of newly found prior art reference of Guo et al. Ryan et al. teaches the above limitations as outlined in the rejection below. New grounds of rejections are also made for all claims dependent on Claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10, 15, 17, 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guo et al. (US 20200411443 A1).
Regarding Claim 10, Guo et al. teaches a method of manufacturing an electronic device, the method comprising:
providing a first device interconnect 130 (pillar 130 on the L.H.S of connect chip 35), a second device interconnect 130 (pillar 130 on the R.H.S of connect chip 35), and a dielectric base block 77, wherein the dielectric base block 77 is laterally between the first device interconnect 130 and the second device interconnect 130, and wherein the dielectric base block 77 comprises a dielectric material that extends from a lower side of the dielectric based block 77 to an upper side of the dielectric base block 77 (Fig. 1: 130, 77, paragraph 0042, 0059);
coupling a lower side of a connect die 35 to the upper side of the dielectric base block 77 (Fig. 1: 35, 77, paragraph 0039, 0059),
encapsulating the connect die 35, the first device interconnect 130, and the second device interconnect 130 with a lower encapsulant 120, wherein a lower side of the lower encapsulant 120 is coplanar with a lower side of the dielectric base block 77, (Fig. 1: 120, 35, 130, 77, paragraph 0042);
providing an upper substrate 30 on the lower encapsulant 120 such that a conductive structure 100, 110 of the upper substrate 30 is coupled to the first device interconnect 130, the second device interconnect 130, and connect die upper interconnect 80a, 80b, 80c, 80d, 80e of the connect die 35 (Fig. 1: 30, 80a-e, 100, 110, paragraph 0042, 0047);
and coupling a first electronic component 20 and a second electronic component 25 to the upper substrate 30 such that the first electronic component 20 is electrically coupled to the second electronic component 25 via the connect die 35 (Fig. 1: 20, 25, 30, 35, paragraph 0039).
Regarding Claim 15, Guo et al. discloses an electronic device 100 comprising:
a lower substrate 140 comprising a lower substrate upper side and a lower substrate lower side (Fig. 1: 140, paragraph 0042, 0067);
an upper substrate 30 comprising an upper substrate upper side and an upper substrate lower side (Fig. 1: 30, paragraph 0038);
a first electronic component 20 and a second electronic component 25 coupled to the upper substrate 30 upper side (Fig. 1: 25, 30, paragraph 0066);
a first device interconnect 130 (pillar 130 on the L.H.S of connect chip 35) and a second device interconnect 130 (pillar 130 on the R.H.S of connect chip 35) that couple the lower substrate 140 upper side to the upper substrate 30 lower side (Fig. 1: 130, 140, 30, paragraph 0067);
and a connect die 35 coupled to the lower substrate 140 upper side laterally between the first device interconnect 130 and the second device interconnect 130, wherein the connect die 35 electrically couples the first electronic component 20 to the second electronic component 25 (Fig. 1: 130, 20, 25, Fig. 19: 35, paragraph 0039).
and a lower encapsulating material 120 providing a lower encapsuling material upper side directly contacting the upper substrate 30 lower side and a lower encapsuling material lower side directly contacting the lower substrate 140 upper side, wherein the lower encapsuling material 120 encapsulates the connect die 35 (Fig. 1: 120, 35, 130, paragraph 0042).
Regarding Claim 17, Guo et al. teaches the electronic device of claim 15, comprising a base block 77 and wherein a lower side of the connect die 35 is coupled to an upper side of the base block 77 (Fig. 1: 77, 35, paragraph 0059).
Note that the adhesive layer 77 made of epoxy is interpreted as the base block.
Regarding Claim 19, Guo et al. teaches the electronic device of claim 15, comprising: an underfill 175 that fills a first gap between the first electronic component 20 and the upper substrate 30 and a second gap between the second electronic component 25 and the upper substrate 30 (see Fig. 1: 127, 20, 25, 30, paragraph 0066).
Regarding Claim 20, Guo et al. teaches The electronic device of claim 19, comprising: an upper encapsulant 150 that encapsulates the first electronic component 20, the second electronic component 25, and the underfill 175; and wherein the lower encapsulating material 120 encapsulates the first device interconnect 130 and the second device interconnect 130 (Fig. 1 : 150, 175, 120, 20, 25, 130, paragraph 0066).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Hwang et al. (US 20220415771 A1) and Ryan et al. (US 20230343606 A1).
Regarding Claim 1, Darmawikarta et al. teaches a method of manufacturing an electronic device, the method comprising:
a first device interconnect 152-1, a second device interconnect 152-1, (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, paragraph 0021), and alignment pads, wherein the alignment pads are laterally between the first device interconnect and the second device interconnect;
coupling connect die lower interconnects of a connect die to the alignment pads;
encapsulating the connect die 114-1, the first device interconnect 152-1, and the second device interconnect 152-2 with a lower encapsulant 133-1 (see annotated Fig. 1 of Darmawikarta et al.: 152-1, 152-2, 114-1, 133-1, paragraph 0029);
providing an upper substrate 148 on the lower encapsulant 133-1 such that a conductive structure 194, 196 of the upper substrate 148 is coupled to the first device interconnect 152-1, the second device interconnect 152-2, and connect die upper interconnects 124 of the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 148, 133-1, 194, 196, 152-1, 152-2, 114-1, 124, paragraph 0021);
coupling a first electronic component 114-2 and a second electronic component 114-3 to the upper substrate 148 such that the first electronic component 114-2 is electrically coupled to the second electronic component 114-3 via the connect die 114-1 (see annotated Fig. 1 of Darmawikarta et al.: 114-1, 114-2, 114-3, 148, paragraph 0021);
and removing the alignment pads to expose ends of the connect die lower interconnects.
Hwang et al. teaches a method of manufacturing an electronic device, the method comprising the following limitations not disclosed by Darmawikarta et al.:
providing alignment pads 160, wherein the alignment pads 160 are laterally between the first device interconnect 550 and the second device interconnect 550 (see Fig. 16: 160, 550, paragraph 0035-0038, 0057),
Note that the pads 160 are used to align the chip pads 210 of the die 200 (see paragraph 0057) and hence are interpreted as the alignment pads. Further note that paragraph 0049 of the instant application (see originally filed disclosure) refers to alignment pads as pads, lands and/or terminals comprising copper, aluminum, gold, silver, nickel, palladium, and/or solder. Thus, the structure of the pads 160 is similar to that of the instant application.
coupling connect die lower interconnects 250 of a connect die 200 to the alignment pads 160 (Fig. 16: 250, 200, 160, paragraph 0041).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Darmawikarta et al. and Hwang et al. in order to provide alignment pads, wherein the alignment pads are laterally between the first device interconnect and the second device interconnect, and couple connect die lower interconnects of a connect die to the alignment pads. Doing so would ensure proper alignment of the connect die on the carrier substrate as well as enable coupling of the connect die to external circuit elements via the substrate.
Further, Ryan et al. teaches a method of manufacturing an electronic device, the method comprising the following limitations not disclosed by Darmawikarta et al.:
removing the alignment pads 208 to expose ends of the connect die lower interconnects 224 (see Fig. 2G-2J: 208, 224, paragraph 0045, 0044, 0050).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Darmawikarta et al., Hwang et al. and Ryan et al. in order to remove the alignment pads to expose ends of the connect die lower interconnects placed in the electronic device of Darmawikarta et al. Doing so would expose the ends of the connect die lower interconnects allowing them to interface with other electronics.
Regarding Claim 4, Darmawikarta et al. teaches the method of claim 1, wherein coupling the first electronic component 114-2 and the second electronic component 114-3 to the upper substrate 148 comprises: coupling the first electronic component 114-2 to the upper substrate 148 via first component fine- pitch interconnects 130-1 and first component coarse-pitch interconnects 130-2 such that the first electronic component 114-2 is coupled to the connect die 114-1 via the first component fine-pitch interconnects 130-1; and coupling the second electronic component 114-3 to the upper substrate 148 via second component fine-pitch interconnects 130-3 and second component coarse-pitch interconnects 130-4 such that the second electronic component 114-3 is coupled to the first electronic component 114-1 via the second component fine- pitch interconnects 130-3 and the connect die 114-1 (See annotated Fig. 1 of Darmawikarta et al.: 130-1, 130-2, 130-3, 130-4, 114-1, 114-2, 114-3, 148, paragraph 0021).
Regarding Claim 5, the combination of Darmawikarta et al., Hwang et al. and Ryan et al. teaches , the method of claim 1, comprising, after removing the alignment pads 208 (as taught by Ryan et al., see Fig. 2G-2J: 208, 224, paragraph 0045, 0044, 0050), providing a lower substrate 102 on a lower side of the lower encapsulant 133-1 such that a conductive structure 146 of the lower substrate 102 is coupled to the first device interconnect 152-1, the second device interconnect 152-2 (as taught by Darmawikarta et al. in annotated Fig. 1: 152-1, 152-2, 133-1, 102, 146, paragraph 0021), and the exposed ends of the connect die lower interconnects 250 (as taught by Hwang et al., see Fig. 16: 250, 200, 160, paragraph 0041 and as taught by Ryan et al., see Fig. 2G-2J: 208, 224, paragraph 0045, 0044, 0050).
Regarding Claim 7, Darmawikarta et al. teaches the method of claim 1, comprising filling a first gap between the first electronic component 114-2 and the upper substrate 148 and a second gap between the second electronic component 114-3 and the upper substrate 148 with an underfill 127 (Fig. 1: 114-2, 114-3, 127, 148, paragraph 0032).
Regarding Claim 8, Darmawikarta et al. teaches the method of claim 1, comprising: filling a first gap between the first electronic component 114-2 and the upper substrate 148 and a second gap between the second electronic component 114-3 and the upper substrate 148 with an underfill 127 (Fig. 1: 114-2, 114-3, 127, 148, paragraph 0032); and encapsulating the first electronic component 114-2, the second electronic component 114-3, and the underfill 127 with an upper encapsulant 133-2 (Fig. 1: 133-2, 127, 114-2, 114-3, paragraph 0053).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Hwang et al. (US 20220415771 A1) and Ryan et al. (US 20230343606 A1), as applied to Claim 1 above, further in view of Kim et al. (US 20160247767 A1) and Yang (US 6759307 B1).
Regarding Claim 2, the combination of Darmawikarta et al. and Hwang et al. teaches the method of claim 1,
wherein: the first device interconnect 152, the second device interconnect 152 (as taught by Darmawikarta et al.), and the alignment pads 160 (as taught by Hwang et al.) are provided on an upper side of a device carrier 102/100 (see Fig. 1: 152, 102, and paragraph 0021 of Darmawikarta et al., Fig. 16: 160, 100, and paragraph 0035-0038, 0057 of Hwang et al.);
and the method comprises: providing a first alignment feature and a second alignment feature on the upper side of the device carrier, wherein the first alignment feature is laterally between the first device interconnect and the alignment pads and the second alignment feature is laterally between the second device interconnect and the alignment pads;
and filling, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier such that the interface material is laterally retained between an inner lateral side of the first alignment feature and an inner lateral side of the second alignment feature.
Kim et al. teaches a method of manufacturing an electronic device, the method comprising: filling, with an interface material 340, a gap between a lower side of the connect die 310 and the upper side of the device carrier 100 (Fig. 2C: 340, 310, 100, paragraph 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al., Hwang et al. and Kim et al. in order to fill, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier. By doing so, the interface material would protect the connect die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, as recognized by Kim et al. (paragraph 0051).
Yang teaches a method of manufacturing an electronic device, the method comprising the following limitations:
providing a first alignment feature 30 (to the left of die 12b) and a second alignment feature 30 (to the left of die 12b) on the upper side of the device carrier 40, wherein the first alignment feature 30 and the second alignment feature 30 are laterally between the first device interconnect 32 (to the left of die 12b) and the second device interconnect 32 (to the right of die 12b) (Fig. 4: 30, 12b, 40, column 7, lines 56-67, column 7, lines 1-6).
Therefore, a person of ordinary skill in the art, using the combined teachings of Darmawikarta et al., Hwang et al. and Yang, would have adapted the alignment feature of Yang in the electronic device of Darmawikarta et al./Hwang et al., so as to provide a first alignment feature and a second alignment feature on the upper side of the device carrier. Doing so would prevent the overflow of interface material, as recognized by Yang (column 8, lines 7-15).
Furthermore, a person of ordinary skill in the art would have recognized that when the interface material 340 of Hwang et al. and the alignment features 30 of Yang are disposed on the electronic device of Darmawikarta et al./Hwang et al.:
the first alignment feature 30 of Yang would laterally be between the first device interconnect 152-1 of Darmawikarta et al. and the alignment pads 160 of Hwang et al. and the second alignment feature 30 of Yang will laterally be between the second device interconnect 152-2 of Darmawikarta et al. and the alignment pads 160 of Hwang et al.
the interface material 340 of Kim et al. will be laterally retained between an inner lateral side of the first alignment feature 30 of Yang and an inner lateral side of the second alignment feature 30 of Yang. (Also note that in a different embodiment shown in Fig 7, Yang teaches an interface material 13a retained between an inner lateral side of the alignment feature 30).
Regarding Claim 3, the combination of Darmawikarta et al. and Hwang et al. teaches the method of claim 1,
wherein: the first device interconnect 152, the second device interconnect 152 (as taught by Darmawikarta et al.), and the alignment pads 210 (as taught by Kim et al.) are provided on an upper side of a device carrier 105/100 (see Fig. 4A: 152, 105, and paragraph 0044 of Darmawikarta et al., Fig. 2B: 210, 100, and paragraph 0038 of Kim et al.).
and the method comprises: providing a first alignment feature and a second alignment feature on the upper side of the device carrier, wherein the first alignment feature is laterally between the first device interconnect and the alignment pads and the second alignment feature is laterally between the second device interconnect and the alignment pads;
and filling, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier such that the interface material encapsulates the connect die lower interconnects and the alignment pads.
Kim et al. teaches a method of manufacturing an electronic device, the method comprising: filling, with an interface material 340, a gap between a lower side of the connect die 310 and the upper side of the device carrier 100 such that the interface material 340 encapsulates the connect die lower interconnects 320 and the pads 210 (Fig. 2C: 340, 310, 100, 320, 210, paragraph 0049).
Therefore, a person of ordinary skill in the art would have combined the teachings of Darmawikarta et al., Hwang et al. and Kim et al. in order to fill, with an interface material, a gap between a lower side of the connect die and the upper side of the device carrier such that the interface material encapsulates the connect die lower interconnects and the alignment pads. By doing so, the interface material would protect the contact die pads and the connect die lower interconnects from external impacts, such as mechanical shocks or corrosion, as recognized by Kim et al. (paragraph 0051).
Yang teaches a method of manufacturing an electronic device, the method comprises
providing a first alignment feature 30 (to the left of die 12b) and a second alignment feature 30 (to the left of die 12b) on the upper side of the device carrier 40, wherein the first alignment feature 30 and the second alignment feature 30 are laterally between the first device interconnect 32 (to the left of die 12b) and the second device interconnect 32 (to the right of die 12b) (Fig. 4: 30, 12b, 40, column 7, lines 56-67, column 7, lines 1-6).
Therefore, a person of ordinary skill in the art, using the combined teachings of Darmawikarta et al., Hwang et al., Kim et al. and Yang, would have adapted the alignment feature of Yang in the electronic device of Darmawikarta et al./Kim et al., so as to provide a first alignment feature and a second alignment feature on the upper side of the device carrier. Doing so would prevent the overflow of interface material, as recognized by Yang (column 8, lines 7-15).
Furthermore, a person of ordinary skill in the art would have recognized that when the interface material 340 of Kim et al. and the alignment features 30 of Yang are disposed on the electronic device of Darmawikarta et al., the first alignment feature 30 of Yang would laterally be between the first device interconnect 152-1 of Darmawikarta et al. and the alignment pads 160 of Hwang et al. et al. and the second alignment feature 30 of Yang will laterally be between the second device interconnect 152-2 of Darmawikarta et al. and the alignment pads 160 of Hwang et al.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Hwang et al. (US 20220415771 A1) and Ryan et al. (US 20230343606 A1), as applied to Claim 5 above, further in view of Kim et al. (US 20160247767 A1).
Regarding Claim 6, the combination of Darmawikarta et al., Hwang et al. and Ryan et al. fails to teach the method of claim 5, comprising providing external interconnects on a lower side of the lower substrate such that at least one of the external interconnects is electrically coupled to at least one of the connect die lower interconnects via the lower substrate.
However, Kim et al. teaches providing external interconnects 30 on a lower side of the lower substrate 100 such that at least one of the external interconnects 30 is electrically coupled to at least one of the connect die lower interconnects 320 via the lower substrate 100 (Fig. 2H: 30, 100, 320, paragraph 0084).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Darmawikarta et al. and Kim et al. in order to come up with the claimed invention. Doing so would enable the connect die to interface with external electronic components.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Darmawikarta et al. (US 20230197661 A1), in view of Hwang et al. (US 20220415771 A1) and Ryan et al. (US 20230343606 A1), as applied to Claim 1 above, further in view of Chun et al. (US 20170345713 A1).
Regarding Claim 9, Darmawikarta et al. teaches the method of claim 1,
wherein: the connect die 114-1 comprises a connect die body comprising a connect die body upper side and a connect die body lower side (as taught by Darmawikarta et al. in Fig. 1: 114-1, paragraph 0021);
connect die interconnects 115 that pass between the connect die body upper side and the connect die body lower side (as taught by Darmawikarta et al. in Fig. 1: 115, 114-1, paragraph 0020);
connect die pads 122 on the connect die body lower side and coupled to lower ends of the connect die interconnects 115 (as taught by Darmawikarta et al. in Fig. 1: 122, 115, paragraph 0020);
a connect die insulating layer on the connect die body lower side, wherein the connect die insulating layer laterally encapsulates lateral sidewalls of the connect die pads;
the connect die lower interconnects are on the connect die body lower side and coupled to respective ones of the connect die pads;
the connect die upper interconnects 124 are on the connect die body upper side (as taught by Darmawikarta et al. in Fig. 1: 124, paragraph 0020);
and one or more of the connect die upper interconnects are coupled to one or more of the connect die lower interconnects via the connect die interconnect through the connect die body and the connect die pads.
Chun et al. teaches a method of manufacturing an electronic device comprising the following limitations:
wherein the connect die 100 comprises: a connect die body comprising a connect die body upper side S1 and a connect die body lower side S2 (see annotated Fig. 11: 100, S1, S2, paragraph 0029);
connect die interconnects 130, 140 that pass between the connect die body upper side S1 and the connect die body lower side S2 (see annotated Fig. 11: 130, 140, S1, S2, paragraph 0029);
Note that the conductive structures 130 and 140 of Fig. 11 together are interpreted as the connect die interconnects.
connect die pads 170 on the connect die body lower side S2 and coupled to lower ends of the connect die interconnects 130, 140 (see annotated Fig. 11: 170, 130, 140, S2, paragraph 0056);
and a connect die insulating layer 172, 250 on the connect die body lower side S2, wherein the connect die insulating layer 172, 250 laterally encapsulates lateral sidewalls of the connect die pads 170 (see annotated Fig. 11: 172, 250, 170, paragraph 0057, 0128);
Note that the underfill 250 and the protection layer 172 of Fig. 11 together are interpreted as the insulating layer.
the connect die upper interconnects 180-1 on the connect die body upper side S1 (see annotated Fig. 11: 180-1, S1, paragraph 0127);
the connect die lower interconnects 180 on the connect die body lower side S2 and coupled to respective ones of the connect die pads 170 (see annotated Fig. 11: 180, S2, 170, paragraph 0127);
and one or more of the connect die upper interconnects 180-1 are coupled to one or more of the connect die lower interconnects 180 via the connect die interconnects 130, 140 through the connect die body and the connect die pads 170 (see annotated Fig. 11: 180, 180-1, 130, 140, 170, paragraph 0127).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Darmawikarta et al. and Chun et al. in order to come up with the invention as recited in Claim 9. By doing so would, the connect die interconnects and the connect die pads would enable efficient vertical signal and power routing from other external circuits through the connect die, while the insulating layer would protect the lower connect die pads for improved mechanical reliability.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20200411443 A1), as applied to Claim 10 above, further in view of Uzoh et al. (US 20220293567 A1).
Regarding Claim 11, Guo et al. fails to explicitly teach the method of claim 10, wherein coupling the lower side of the connect die comprises coupling the lower side of the connect die to the upper side of the dielectric base block through an interface material.
Uzoh et al. teaches a method of manufacturing an electronic device, the method comprising:
wherein coupling the lower side of the connect die 2306 comprises coupling the lower side of the connect die 2306 to the upper side of the dielectric base block 2302_1 through an interface material 2303_2 (see annotated Fig. 23: 2306, 2303_1, 2303_2, paragraph 0102).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Guo et al. and Uzoh et al. in order to couple the lower side of the connect die to the upper side of the dielectric base block through an interface material. Doing so would improve the bonding strength between the connect die and the dielectric base block.
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Annotated Fig. 23 of Uzoh et al. (US 20220293567 A1)
Regarding Claim 12, Guo et al. fails to explicitly teach the method of claim 10, wherein coupling the lower side of the connect die comprises coupling the lower side of the connect die to the upper side of the dielectric base block through a die attach film, an adhesive film, and/or an adhesive tape.
Uzoh et al. teaches a method of manufacturing an electronic device, the method comprising:
wherein coupling the lower side of the connect die 2306 comprises coupling the lower side of the connect die 2306 to the upper side of the dielectric base block 2303_1 through a die attach film, an adhesive film 2302_2, and/or an adhesive tape (see annotated Fig. 23: 2306, 2303_1, 2303_2, paragraph 0067, 0102).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Guo et al. and Uzoh et al. in order to couple the lower side of the connect die to the upper side of the dielectric base block through a die attach film, an adhesive film, and/or an adhesive tape. Doing so would improve the bonding strength between the connect die and the dielectric base block.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20200411443 A1), as applied to Claim 10 above, further in view of Kawase et al. (US 20160111345 A1).
Regarding Claim 13, Guo et al. teaches the method of claim 10,
wherein coupling the first electronic component 20 and the second electronic component 25 to the upper substrate 30 comprises: coupling a lower side of the first electronic component 20 to the upper substrate 30 via first component interconnects 115 (Fig. 1: 20, 25, 30, 115, paragraph 0043).
and coupling an upper side of the second electronic component to the upper substrate via bond wires.
Kawase et al teaches a method of manufacturing an electronic device, the method comprising:
coupling an upper side of a second electronic component 8 to the substrate 3 via bond wires 12 (Fig. 1: 8, 3, 12, paragraph 0027).
Therefore, a person of ordinary skill in the art would have combined the teachings of Guo et al. with the teachings of Kawase et al. in order to couple an upper side of the second electronic component to the upper substrate via bond wires. Doing so would simplify the semiconductor manufacturing and packaging process flow as wire bonding can be done after die attach allowing for more flexible assembly.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20200411443 A1), as applied to Claim 10 above, further in view of Kim et al. (US 20160247767 A1).
Guo et al. teaches the method of claim 10, comprising:
providing a lower substrate 140 on a lower side of the lower encapsulant 120 such that a conductive structure 135 of the lower substrate 140 is coupled to the first device interconnect 130 and the second device interconnect 130 (Fig. 1: 140, 130, 135, paragraph 0042);
and providing external interconnects on a lower side of the lower substrate such that at least one of the external interconnects is electrically coupled to the first device interconnect via the lower substrate.
However, Kim et al. teaches a method of manufacturing an electronic device, the method comprising:
providing external interconnects 30 on a lower side of the lower substrate 100 such that at least one of the external interconnects 30 is electrically coupled to the first device interconnect 220 via the lower substrate 100. (Fig. 2H: 30, 100, 320, 220, paragraph 0084).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Guo et al. and Kim et al. in order to provide external interconnects on a lower side of the lower substrate such that at least one of the external interconnects is electrically coupled to the first device interconnect via the lower substrate. Doing so would enable the connect die to interface with external electronic components.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20200411443 A1), as applied to Claim 15, further in view of Chun et al. (US 20170345713 A1).
Regarding Claim 16, Guo et al. teaches the electronic device of claim 15,
wherein the connect die 35 comprises: a connect die body comprising a connect die body upper side and a connect die body lower side (see Fig. 1: 114-1, paragraph 0021);
connect die interconnects that pass between the connect die body upper side and the connect die body lower side;
connect die pads on the connect die body lower side and coupled to lower ends of the connect die interconnects;
a connect die insulating layer on the connect die body lower side, wherein the connect die insulating layer laterally encapsulates lateral sidewalls of the connect die pads;
connect die upper interconnects 124 on the connect die body upper side (see Fig. 1: 124, paragraph 0020);
and connect die lower interconnects on the connect die body lower side and coupled to respective ones of the connect die pads;
and wherein one or more of the connect die upper interconnects are coupled to one or more of the connect die lower interconnects via the connect die interconnects through the connect die body and the connect die pads.
Chun et al. teaches an electronic device comprising the following limitations:
wherein the connect die 100 comprises: a connect die body comprising a connect die body upper side S1 and a connect die body lower side S2 (see annotated Fig. 11: 100, S1, S2, paragraph 0029);
connect die interconnects 130, 140 that pass between the connect die body upper side S1 and the connect die body lower side S2 (see annotated Fig. 11: 130, 140, S1, S2, paragraph 0029);
Note that the conductive structures 130 and 140 of Fig. 11 together are interpreted as the connect die interconnects.
connect die pads 170 on the connect die body lower side S2 and coupled to lower ends of the connect die interconnects 130, 140 (see annotated Fig. 11: 170, 130, 140, S2, paragraph 0056);
a connect die insulating layer 172, 250 on the connect die body lower side S2, wherein the connect die insulating layer 172, 250 laterally encapsulates lateral sidewalls of the connect die pads 170 (see annotated Fig. 11: 172, 250, 170, paragraph 0057, 0128);
Note that the underfill 250 and the protection layer 172 of Fig. 11 together are interpreted as the insulating layer.
connect die upper interconnects 180-1 on the connect die body upper side S1 (see annotated Fig. 11: 180-1, S1, paragraph 0127);
and connect die lower interconnects 180 on the connect die body lower side S2 and coupled to respective ones of the connect die pads 170 (see annotated Fig. 11: 180, S2, 170, paragraph 0127);
and wherein one or more of the connect die upper interconnects 180-1 are coupled to one or more of the connect die lower interconnects 180 via the connect die interconnects 130, 140 through the connect die body and the connect die pads 170 (see annotated Fig. 11: 180, 180-1, 130, 140, 170, paragraph 0127).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Guo et al. and Chun et al. in order to come up with the invention as recited in Claim 16. By doing so would, the connect die interconnects and the connect die pads would enable efficient vertical signal and power routing from other external circuits through the connect die, while the insulating layer would protect the lower connect die pads for improved mechanical reliability.
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Annotated Fig. 11 of Chun et al. (US 20170345713 A1)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US 20200411443 A1), as applied to Claim 15, further in view of Darmawikarta et al. (US 20230197661 A1).
Regarding Claim 18, Guo et al. fails to teach the electronic device of claim 15, comprising: first component fine-pitch interconnects and first component coarse-pitch interconnects that coupled the first electronic component to the upper substrate; and second component fine-pitch interconnects and second component coarse-pitch interconnects that coupled the second electronic component to the upper substrate; and wherein the connect die couples the first electronic component to the second electronic component via the first component fine-pitch interconnects and the second component fine-pitch interconnects.
Darmawikarta et al. teaches the electronic device comprising: first component fine-pitch interconnects 130-1 and first component coarse-pitch interconnects 130-2 that coupled the first electronic component 114-2 to the upper substrate 148; and second component fine-pitch interconnects 130-3 and second component coarse-pitch interconnects 130-4 that coupled the second electronic component 114-3 to the upper substrate 148; and wherein the connect die 114-1 couples the first electronic component 114-2 to the second electronic component 114-3 via the first component fine-pitch interconnects 130-1 and the second component fine-pitch interconnects 130-3 (See annotated Fig. 1 of Darmawikarta et al.: 130-1, 130-2, 130-3, 130-4, 114-1, 114-2, 114-3, paragraph 0021).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to have combined the teachings of Guo et al. and Darmawikarta et al. in order to come up with the invention as recited in Claim 18. By doing so, the fine-pitch interconnects between the first and second electronic components would enable high bandwidth, low latency die-die communication, while the coarse-pitch interconnects coupled to the substrate would provide a cost-effective, mechanically robust connection for power delivery and external I/O.
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Annotated Fig. 1 of Darmawikarta et al. (US 20230197661 A1)
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US20160174365A1) teaches an electronic device comprising alignment features
Guillotte et al. (US 5012322) teaches an electronic device comprising a die mounted on a base block
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 07/05/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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