Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, with traverse, of claims 1 and 5-7 in the “Response to Restriction Requirement” filed on 01/19/2026 is acknowledged and entered by the Examiner.
Applicant’s traversal arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 08/03/2018, see “In addition, as set forth in 37 C.F.R. § 1.146, a reasonable number of species are permitted in a single application. The present application contains two species, which should be considered to be a reasonable number of species. Further, examination of both species together in one application would not place an undue burden on the Examiner. It is respectfully submitted that the Examiner's Election of Species Requirement is improper in view of the fact that a reasonable number of species are set forth in the present application, and such is permitted by Rule 146”, (remarks on page 2) have been fully considered. The examiner respectfully disagrees with the Applicant’s arguments for the following reasons:
Firstly, Species D.1-D.13, as claimed, are independent or distinct because they have been disclosed in separate figures and different embodiments, and are characterized by mutually exclusive characteristics. Secondly, there is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reasons apply: the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter as exemplified by the aforementioned mutually exclusive characteristics, while the species or groupings of patentably indistinct species require a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Further clarification is provided below.
Regarding Species D.1-D.13, are mutually exclusive with “an exemplary device embodiment according to a second example where the dielectric inorganic substrate comprises a control pad disposed on the second side of the dielectric inorganic substrate, the at least one second metal structure connecting the control pad, and wherein: the control pad has an area which is greater than an area of the control electrode by at least a factor 3; and/or an edge of the control pad is closer to an edge of the semiconductor transistor chip than an edge of the control electrode” (as described for some embodiments (specifically discussed in [0132])) in Species 1, and, “an exemplary device embodiment according to a third example where the dielectric inorganic substrate comprises a control electrode ring surrounding an active area of the semiconductor transistor chip in a vertical projection, and wherein the control electrode ring is embedded in the dielectric inorganic substrate” (as described for some embodiments (specifically discussed in [0133])) in Species 2, and, “an exemplary device embodiment according to a fourth example where the dielectric inorganic substrate comprises at least one control electrode finger extending into an active area of the semiconductor transistor chip in a vertical projection, and wherein the at least one control electrode finger is embedded in the dielectric inorganic substrate” (as described for some embodiments (specifically discussed in [0134]) in Species 3, and, “an exemplary device embodiment according to a fifth example to a seventh example where a high-voltage load electrode ring extending adjacent to an edge of the semiconductor transistor chip, wherein the high- voltage load electrode ring is partly or completely embedded in the dielectric inorganic substrate“(as described for some embodiments (specifically discussed in [0076, 0135-0137]) in Species 4, and, “an exemplary device embodiment according to an eight example where a plurality of low-voltage load electrode field plates, wherein the low-voltage load electrode field plates are vertical metal structures electrically connected to the low-voltage load electrode“ (as described for some embodiments (specifically discussed in [0138]) in Species 5, and, “an exemplary device embodiment according to a ninth example where a plurality of control electrode field plates, wherein the control electrode field plates are vertical metal structures electrically connected to the control electrode“ (as described for some embodiments (specifically discussed in [0139]) in Species 6, and, “an exemplary device embodiment according to a tenth example to an eleventh example where a barrier layer disposed on the first side the dielectric inorganic substrate“ (as described for some embodiments (specifically discussed in [0085, 0140-0141]) in Species 7, and, “an exemplary device embodiment according to a twelfth example to a thirteenth example where an active or passive electrical component mounted on the second side of the dielectric inorganic substrate“ (as described for some embodiments (specifically discussed in [0101, 0142-0143]) in Species 8, and, “an exemplary device embodiment according to a fourteenth example where a third metal structure running through the dielectric inorganic substrate and connected to an intermediate voltage region on the front side of the semiconductor transistor chip and to an intermediate voltage pad disposed on the second side of the dielectric inorganic substrate, wherein the intermediate voltage region is located near an edge of the semiconductor transistor chip“ (as described for some embodiments (specifically discussed in [0144]) in Species 9, and, “an exemplary device embodiment according to a fifteenth example where the dielectric inorganic substrate is a glass substrate“ (as described for some embodiments (specifically discussed in [0145]) in Species 10, and, “an exemplary device embodiment according to a sixteenth example where the front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate by a glass frit connection“ (as described for some embodiments (specifically discussed in [0146]) in Species 11, and, “an exemplary device embodiment according to a seventeenth example where wherein the first metal structures and/or the at least one second metal structure are plated metal pillars“ (as described for some embodiments (specifically discussed in [0147]) in Species 12, and, “an exemplary device embodiment according to a eighteenth example where the dielectric inorganic substrate comprises a plurality of stacked dielectric inorganic substrate layers“ (as described for some embodiments (specifically discussed in [0148]) in Species 13.
There is a search and/or examination burden for the patentably distinct species as set forth above because at least the following reasons apply:
the species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter as exemplified by the aforementioned mutually exclusive characteristics, while the species or groupings of patentably indistinct species require a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Therefore, restriction for examination purposes as indicated is proper.
The requirement is still deemed proper and is therefore made FINAL.
This office action consider claims 1-18 pending for prosecution, wherein claims 2-4 and 8-18 are withdrawn from further consideration, and claims 1 and 5-7 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1 and 5-7 are rejected under 35 U.S.C.103 as being unpatentable over Wu (US 20210375753 A1; hereinafter Wu) in view of Shilimkar et al. (US 20220115298 A1; hereinafter Shilimkar) and the following statement.
Regarding claim 1, Wu teaches a semiconductor device (see the entire document, specifically Fig. 1A+; [0004+], and as cited below), comprising:
a (see below for “high-voltage”) semiconductor transistor chip (Fig. 14B; see [0039, 0042, 0044, 0062, 0069]) comprising a front side and a backside, wherein a low-voltage load electrode (38; Fig. 14B; [0048], source region; see [0099] of the Specification of the instant invention states that “the source area (i.e. the LV load electrode120)”) and a control electrode (54; Fig. 14B; [0040-0041]; see [0035] of the Specification of the instant invention states that “the control electrode130 may, e.g., form the gate electrode”) are disposed on the front side of the semiconductor transistor chip
As noted above, Wu does not expressly disclose “a high-voltage semiconductor transistor chip comprising a front side and a backside”.
However, in the analogous art, Shilimkar teaches semiconductor devices ([0002]), wherein (Fig. 1+; [0090+]) Die body (72; Fig. 4; [0050]) of semiconductor device (70; Fig. 4; [0050]) comprising a layered die technology of a type enabling relatively high transistor power densities. An example of such a power dense die technology is a layered GaN structure in which one or more layers of a GaN material (that is, a semiconductor material containing GaN as its primary constituent, by weight) are formed over one or more substrate layers of another material, such as silicon carbide (SiC). Other examples of layered die technologies suitable for producing die body 72 of semiconductor device 70 include GaAs structures, which likewise support the formation of transistor ICs (e.g., transistor 92) having relatively high power densities. As is the case when die body 72 is composed of a high resistivity Si (or other bulk semiconductor) material, such layered die technologies also typically possess relatively high electrical resistances exceeding 520Ω per cm taken through the thickness of the layered die structure ([0050]).
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify the transistor structure of Wu with the transistor structure of Shilimkar, and thereby, modified Wu’s (by Shilimkar) device will have a high-voltage semiconductor transistor chip (Wu Fig. 14B; see [0039, 0042, 0044, 0062, 0069] in view of Shilimkar 70; Fig. 4; [0050]) comprising a front side and a backside, wherein a low-voltage load electrode (Wu 38; Fig. 14B; [0048], source region; see [0099] of the Specification of the instant invention states that “the source area (i.e. the LV load electrode120)”) and a control electrode (Wu 54; Fig. 14B; [0040-0041]; see [0035] of the Specification of the instant invention states that “the control electrode130 may, e.g., form the gate electrode”) are disposed on the front side of the semiconductor transistor chip (Wu Fig. 14B; see [0039, 0042, 0044, 0062, 0069] in view of Shilimkar 70; Fig. 4; [0050]).
The ordinary artisan would have been motivated to modify Wu in the manner set forth above, at least, because this inclusion provides a semiconductor device comprising a high transistor power densities (Shilimkar [0050]), which helps increase the functionality of the overall device.
Modified Wu (by Shilimkar) further teaches
a dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]) comprising a first side and a second side opposite the first side;
a pattern of first metal structures (Wu {94A, 94B, 112}; Fig. 14B; [0059-0064]) running through the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]) and connected to the low-voltage load electrode (Wu 38; Fig. 14B; [0048], source region; see [0099] of the Specification of the instant invention states that “the source area (i.e. the LV load electrode120)”); and
at least one second metal structure (Wu {94A, 94B}; Fig. 14B; [0059-0064]) running through the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]) and connected to the control electrode (Wu 54; Fig. 14B; [0040-0041]; see [0035] of the Specification of the instant invention states that “the control electrode130 may, e.g., form the gate electrode”),
wherein the front side of the semiconductor transistor chip (Wu Fig. 14B; see [0039, 0042, 0044, 0062, 0069] in view of Shilimkar 70; Fig. 4; [0050]) is attached to the first side the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]),
wherein the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]) has a thickness measured between the first side and the second side (see below for “of at least 50 um”).
While Wu does not expressly disclose wherein the dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 um, some if its values fall within the claim range of less than or equal to about 30 Å, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “planar dielectric spacer liner 82 may have a thickness in a range from 3 nm to 15 nm, such as from 5 nm to 10 nm, although lesser and greater thicknesses may also be used”, “the thickness of the etch stop dielectric liner 84 may be in a range from 5 nm to 20 nm, such as from 8 nm to 12 nm, although lesser and greater thicknesses may also be used”, and “thickness of the via-level dielectric layer 86, as measured from the topmost surface of the etch stop dielectric liner 84, may be in a range from 100 nm to 1,000 nm, such as from 200 nm to 500 nm, although lesser and greater thicknesses may also be used” ([0049, 0051, 0053]), as disclosed in prior art Wu, to arrive at the recited limitation of wherein the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]) has a thickness measured between the first side and the second side of at least 50 um (see [0049, 0051, 0053]; where some of the values from a thickness range, for example thicknesses greater than 1000nm , are within the claimed thickness range; see MPEP § 2144.05.I; where a thicknesses greater than 1000nm, such as 60,000 nm, would be within the claimed range).
Regarding claim 5, modified Wu (by Shilimkar) teaches all of the features of claim 1.
Modified Wu (by Shilimkar) further comprising: a high-voltage load electrode ring (in view of Shilimkar 112; Fig. 4; [0048, 0053]) extending adjacent to an edge of the semiconductor transistor chip (Wu Fig. 14B; see [0039, 0042, 0044, 0062, 0069] in view of Shilimkar 70; Fig. 4; [0050]), wherein the high- voltage load electrode ring (in view of Shilimkar 112; Fig. 4; [0048, 0053]) is partly or completely embedded in the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]).
Regarding claim 6, modified Wu (by Shilimkar) teaches all of the features of claim 5.
Modified Wu (by Shilimkar) further teaches wherein the high- voltage load electrode ring (in view of Shilimkar 112; Fig. 4; [0048, 0053]) comprises electrically floating rings embedded in the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]).
Regarding claim 7, modified Wu (by Shilimkar) teaches all of the features of claim 5.
Modified Wu (by Shilimkar) further comprising: a plurality of high-voltage load electrode field plates (in view of Shilimkar {83, 88}; Fig. 4; [0047]) embedded in the dielectric inorganic substrate (Wu {86, 84, 82}; Fig. 14B; [0049, 0051, 0053]), wherein the high- voltage load electrode field plates are vertical metal structures electrically connected to the high-voltage load electrode ring (in view of Shilimkar 112; Fig. 4; [0048, 0053]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898