DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 1/16/2026. Claims 1-18 are pending and have been examined. Claims 1-2, 8, 10-11 and 16-17 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claim 16 recites the following underlined contingent limitations: “…further comprising at the scheduler, canceling, in response to a cache miss of a preceding load instruction in a dependency chain of the producer instruction, all instructions in a subsequent dependency chain to the preceding load instruction, the canceling being based on the indicator.”
The contingent limitations use the language “in response to” and are contingent because they precede steps that are only required to be performed in response to (i.e. when or if) a condition being met. For example, the steps of “a scheduler canceling of instructions” are only required to be performed in response to (e.g. “when” or “if”) a preceding load instruction in a dependency chain causes a cache miss. However, if a preceding load instruction in the dependency chain that causes a cache miss is not encountered none of the steps of “canceling” are required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)). For purposes of examination the examiner will provide a prior art rejection with the above broadest reasonable interpretation.
The examiner suggests amending the claim to remove the contingent limitations stating “in response to” and to positively recite each step of the method claim (e.g. the applicant should amend the claim to include a positive step of “detecting” a cache miss of a preceding load instruction…).
The examiner notes that claim 17 is dependent upon claim 16 above, and is similarly rejected in light of the broadest reasonable interpretation given above based on contingent limitations of the method claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 1, line 14 the limitation stating “a plurality of the consumer instructions” lacks clarity. The limitation lacks clarity because “the consumer instructions” lacks proper antecedent basis as there is no prior recitation of “consumer instructions”. (note the claim only mentions a single consumer instruction in claim 1, line 11).
In regards to claim 1, line 15 the limitation stating “a plurality of the indicators” lacks clarity. The limitation lacks clarity because “the indicators” lacks proper antecedent basis as there is no prior recitation of “indicators”. (note the claim only mentions a single indicator in claim 1, line 7).
In regards to claim 10, line 14 the limitation stating “a plurality of the consumer instructions” lacks clarity. The limitation lacks clarity because “the consumer instructions” lacks proper antecedent basis as there is no prior recitation of “consumer instructions”. (note the claim only mentions a single consumer instruction in claim 10, line 11).
In regards to claim 10, line 16 the limitation stating “a plurality of the indicators” lacks clarity. The limitation lacks clarity because “the indicators” lacks proper antecedent basis as there is no prior recitation of “indicators”. (note the claim only mentions a single indicator in claim 10, line 6).
Claims 2-9 and 11-18 are dependent upon one of the claims above and therefore are similarly rejected for including the deficiencies of the claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 10-12 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, PGPUB No. 2006/0095732, and further in view of Jiang, PGPUB No. 2007/0204135.
In regards to claim 1, Tran discloses An arithmetic processing apparatus ([0021 and See Fig. 3]: wherein a processor which performs arithmetic processing is disclosed (see paragraphs [0314-0315 and 0318]: which disclose the arithmetic processing units of a processor)) comprising: control circuitry ([0021-0023 and Figs. 3-5]: wherein scoreboard circuitry controls instruction issuing and operand forwarding) wherein the arithmetic processing apparatus executes a plurality of instructions in parallel and sequentially from executable instructions ([See Fig. 3 and 0163]: wherein the processor of Fig. 3 executes a plurality of instructions in parallel and sequentially from executable instructions. Wherein a plurality of pipelines execute instructions in parallel and each pipeline receives and executes instructions sequentially) and the control circuitry holds an indicator indicating a pipeline that executes a producer instruction included in the plurality of instructions ([0097]: wherein the scoreboard circuitry holds an indicator (which includes type bits) indicating a pipeline that executes a producer instruction included in a plurality instructions (see [0314-0315 and 0318) and Figs. 3-5)) and uniquely identifying an execution stage on the pipeline of the producer instruction from which a result of an operation is to be forwarded ([0074-0075, 0080-0081 and 0096]: wherein upper bits of scoreboard (current position entry bits of indicator) are used to uniquely identify an execution stage on the pipeline of the producer instruction from which a result of an operation is to be forwarded (as an example see Fig. 3 wherein bits “01000” indicate execute stage E2 forwards data and the position of the “1” bit uniquely identifies the execute stage of the producer instruction) (also see Figs. 4-5 for further clarity)) the pipeline has multiple types of latency ([0068-0072]: wherein the pipeline has multiple types of latency, such as a latency type of forwarding data from a second stage (E2) to a first stage (E1) and a second latency type of forwarding data from a last stage (E5) to a first stage (E1) (note the pipeline includes various forwarding latencies such as disclosed in Fig. 3)) and the control circuitry executes data dependency resolution between the producer instruction and a consumer instruction that uses an execution result of the producer instruction and that is included in the plurality of instructions ([0081-0084 and 0093-0097]: wherein the scoreboard circuitry executes data dependency resolution by controlling operand forwarding of an execution result of the producer instruction to a dependent consumer instruction included in the plurality of instructions (also see abstract and Figs. 3-5 for further clarity)) and controls issuing timings of the plurality of instructions. ([0082-0083 and 0329]: wherein scoreboard circuitry uses lowers bits (element 1720) to control issuing timings of instructions by delaying consumer instruction issuing to avoid data dependency hazards (See Figs. 3-5 for clarity)) and the control circuitry holds a plurality of the indicators each indicating the pipeline of the producer instruction for each of the plurality of consumer instructions. ([0013, 0093-0099]: scoreboard circuitry includes a plurality of indicators each indicating the pipeline of the producer instruction (the two type bits of the seven-bit indicators) for each of the plurality of consumer dependent instructions having source operands which are dependent upon the producer instructions results. (see abstract for further discussion of candidate consumer instructions and Figs. 4-5 for a plurality of indicators and [0251]: which discloses example of multiple consumer candidate instructions checking data of scoreboard from previous producer instructions)
Tran thus far does not disclose a queue storing the plurality of instructions, wherein the queue stores a plurality of consumer instructions.
Jiang discloses a queue storing the plurality of instructions ([0039 and 0044]: wherein an instruction dispatch buffer queue stores a plurality of instructions (See element 700 of Fig. 7 that illustrates an instruction dispatch buffer queue)) wherein the queue stores a plurality of consumer instructions. ([0039, 0044, 0059, 0104]: wherein a queue stores consumer instructions)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Tran to include an instruction queue to store a plurality of instructions prior to issuing instructions as the processor of Jiang. It would have been obvious to one of ordinary skill in the art because an instruction queue can allow for buffering of instructions before they are issued to execution units, thus supporting simultaneous processing of multiple instructions and improving throughput in processors including multiple pipelines such as superscalar processors.
Claim 10 is similarly rejected on the same basis as claim 1 above.
In regards to claim 2, the combination of Tran and Jiang discloses The arithmetic processing apparatus according to claim 1 (see rejection of claim 1 above) wherein the indicator comprises: pipeline identification information of the pipeline to which the producer instruction is issued (Tran [0097-0098]: wherein the scoreboard circuitry holds an indicator (type bits included in 7 bits of upper row bits) indicating a pipeline to which the producer instruction is issued (see [0314-0315 and 0318) and Figs. 3-5)) and stage identification information uniquely allocated to each stage (Tran [0074-0075, 0080-0081, 0096 and 0098]: wherein 5 upper bits of scoreboard (current position entry bits of scoreboard) are uniquely allocated to each execution stage on the pipeline; wherein each bit position uniquely identifies a respective execute stage (as an example see Fig. 3 wherein bits “01000” indicate execute stage E2 forwards data and the position of the “1” bit uniquely identifies the execute stage E2) (also see Figs. 4-5 for further clarity))) from a stage corresponding from a first issuing timing at which the result of the operation is forwarded from the producer instruction to the consumer instruction at a shortest forwarding timing (Tran [0071-0075 and 0082-0083]: wherein a pipe stage (E2) corresponds to a first issuing timing at which the result of the operation is forwarded from the producer instruction to the consumer instruction at a shortest forwarded timing) to a stage corresponding to a second issuing timing at which the result of the operation is stored in a register and comes to be ready to be read by the consumer instruction. (Tran [0076-0078 and 0082-0083]: wherein pipe stage (E5) corresponds to a second issuing timing which the result of the operation is stored in a register file (element 1660) and comes to be ready to be read by a consumer instruction because E5 is a writeback stage)
Claim 11 is similarly rejected on the same basis as claim 2 above.
In regards to claim 3, the combination of Tran and Jiang discloses The arithmetic processing apparatus according to claim 2 (see rejection of claim 2 above) wherein the control circuity generates a plurality of indicators one for each entry of the queue and each operand of the plurality of instructions in relation to each of a plurality of producer instructions. (Tran [0086 and 0093-0099]: scoreboard circuitry includes a plurality of indicators one for each issuing instruction and each operand of the plurality of instructions in relation to a producer instructions (see Figs 4-5; wherein there are plurality of scoreboard units each corresponding to each register of a register file)| Note: Jiang discloses an instruction queue as claimed above and thus the combination of Tran and Jiang would disclose the above limitation relative to indicators for each entry of the queue (See Jiang [0028 and 0064-0067]: wherein instruction dispatch buffer queue (element 700) includes a plurality of operand availability bits including the counters for each entry in the queue and each operand of the plurality of instructions in relation to producer instructions))
Claim 12 is similarly rejected on the same basis as claim 3 above.
In regards to claim 5, the combination of Tran and Jiang discloses The arithmetic processing apparatus according to claim 3 (see rejection of claim 3 above) wherein the control circuitry executes the data dependency resolution, using the indicator retained in each operand of the plurality of instructions. (Tran [0080-0081 and 0093-0098]: wherein the scoreboard circuitry executes data dependency resolution using the indicator in each of the scoreboard units retained for each operand of the plurality of instructions by indicating producer pipeline stage data that can be forwarded too dependent instructions as to resolve data dependencies between producer and consumer instructions. In addition the lower bits of the scoreboard units delay issuing of consumer instructions as to wait to issue instructions until data dependencies have been resolved (i.e. waiting until operand data is ready before issuing) (See Figs. 3-5))|Jiang [0067-0072 and 0085-0092]: wherein the instruction dispatcher executes dependency resolution using the count indicators retained in each operand of the plurality of instructions by using the count indicators to determine when bypassing of data is enabled for resolving data dependencies between producer and consumer instructions)
Claim 14 is similarly rejected on the same basis as claim 5 above.
In regards to claim 6, the combination of Tran and Jiang discloses The arithmetic processing apparatus according to claim 1 (see rejection of claim 1 above) further comprising forwarding control circuitry that forwards, based on the indicator, the result of the operation of the producer instruction to an operand of the consumer instruction (Tran [0074-0077]: wherein bypass buses/paths (elements 1682, 1684, 1686 and 1692) forward, based on indicators of scoreboard units, result data of operations of producer instructions to an operand of consumer instructions (See Figs. 4-5)|Jiang [0029, 0058 and 0061-0062]: wherein pipeline circuitry, including bypassing buses as shown in Fig. 4, are used to bypass results of producer instructions to operands of consumer instructions based on counter value indicators) the consumer instruction being issued to a pipeline that executes the consumer instruction at a timing according to the control by the control circuitry. (Tran [0082-0083 and Figs. 3-5]: wherein a consumer instruction is issued to a pipeline that executes the consumer instruction at a timing according to the lower bits of scoreboard units of the scoreboard circuitry. Wherein the timing indicates whether a consumer can issue or must wait one or two cycles to issue as to ensure data dependency resolution| Jiang [0029, 0058, 0061-0062 and 0099]: wherein the consumer instruction is issued to a pipeline at a timing according to the control indicated by the instruction dispatch unit (control circuitry) which uses the counter values)
Claim 15 is similarly rejected on the same basis as claim 6 above.
In regards claim 16, the combination of Tran and Jiang discloses The method according to claim 10 (see rejection of claim 10) at the scheduler, canceling, in response to a cache miss of a preceding load instruction in a dependency chain of the producer instruction, all instructions in a subsequent dependency chain to the preceding load instruction, the canceling being based on the indicator. (Tran [0068]: wherein instruction decode pipe issues (scheduler) instructions. (Note: the claim is rejected under the broadest reasonable interpretation in light of the contingent limitations of the method claim, thus all that is required is an instruction scheduler))
In regards claim 17, the combination of Tran and Jiang discloses The method according to claim 16 (see rejection of claim 16 above) further comprising at the scheduler, setting information representing whether the data dependency resolution succeeds or not to a value indicating that, due to the cache miss causing data dependency resolution failure, each producer instruction is awaiting re-issue by the scheduler, on each of all instructions in the subsequent dependency chain to the preceding load instruction, in the canceling. (Tran [0068]: wherein instruction decode pipe issues (scheduler) instructions. (Note: the claim is rejected under the broadest reasonable interpretation in light of the contingent limitations of the method claim, thus all that is required is an instruction scheduler, as under the broadest reasonable interpretation there is no cache miss required to occur))
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran, Jiang and further in view of Teruyama, PGPUB No. 2003/0182536.
In regards to claim 9, the combination of Tran and Jiang discloses The arithmetic processing apparatus according to claim 1 (see rejection of claim 1 above).
The combination of Tran and Jiang does not disclose further comprising updating control circuitry that controls, based on the indicator, updating of an Inflight Condition Flag. Tran discloses an indicator that includes pipeline execution information relative to a producer instruction, wherein the indicator is used to determine when consumer instructions can be executed when the consumer instructions are dependent upon producer instruction execution. However, Tran does not disclose a flag used to determine when instructions are in an in-flight state or not (i.e., executing or not).
Teruyama discloses further comprising updating control circuitry that controls, based on an indication, updating of an Inflight Condition Flag ([0076, 0081-0082 and 0089]: wherein update circuitry updates an in-flight bit to indicate whether an instruction entry in an instruction window is currently being executed or not, based on an indication that the instructions are being executed (i.e., issued for execution) or not) The combination would have an instruction issuing circuitry of Tran and Jiang that tracks when producer and consumer instructions can be executed in a processor including update circuitry and an in-flight condition bit as taught in Teruyama; such that a bit can be used to track when producer instructions are being executed which would indicate when consumer instruction operands would be ready.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the instruction issuing circuitry of Tran and Jiang to include an in-flight condition bit and circuitry to update said bit as taught in Teruyama. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (updating an in-flight condition bit in a instruction buffer/queue to track when instructions are being executed as taught in Teruyama) to a known device (multi-pipeline processor of Tran and Jiang that issues producer and consumer instructions for execution based on a plurality of instruction operand indicators) ready for improvement to yield predictable results (using update circuitry and an in-flight condition bit to track when instructions are being executed, such that producer instruction execution can be tracked in order to determine when consumer instruction operands will be ready) for the benefit of using additional information (in-flight condition bits) to track and determine instruction execution (i.e. tracking execution of producer instructions can be used to improve consumer instruction issuing because that information indicates when consumer instruction operands are ready) (MPEP 2143, Example D).
Claim 18 is similarly rejected on the same basis as claim 9 above.
Allowable Subject Matter
Claims 4, 7-8 and 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 4 filed on 12/20/24. The prior art of record has not taught either individually or in combination and together with all claimed features “ wherein: the stage identification information is set at a first cycle earlier by a first given number of cycles than a last cycle at which the producer instruction is executed, and is reset at a second cycle later by a second given number of cycles than the last cycle; and unique identifiers are allocated one to each of one or more cycles from the first cycle to the second cycle” as claimed in claim 4, which is dependent upon and includes all limitations of claim 1-2.
The closest prior art of record Tran discloses using shift registers to store stage identification information that are used to control issuing of consumer instructions, wherein a “bit” is shifted in a register to indicate an execute stage of a producer instruction which forwards data to a consumer instruction. However, Tran does not disclose setting the uniquely allocated stage identifiers at a first cycle earlier by a first given number of cycles than a last cycle at which the producer instruction is executed, and is reset at a second cycle later by a second given number of cycles than the last cycle nor unique identifiers being allocated one to each of one or more cycles from the first cycle to the second cycle as claimed. While, Husby (PGPUB No. 2014/0129805) discloses using counter values of a resource tracker to determine when producer instruction results are produced such that consumer instructions can be issued for execution. However, Husby does not disclose the above claim limitations of claim 4, which include all limitations of claims 1-2 from which it depends.
Therefore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claim 13 is allowable over the prior art for similar reasons as claim 4 above.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, alone or in combination, fail to disclose or render obvious claim 7 filed on 1/23/23. The prior art of record has not taught either individually or in combination and together with all claimed features “further comprising canceling control circuitry that cancels, when a preceding load instruction exists in a dependency chain of the producer instruction and the preceding load instruction results in a cache miss, all instructions in a subsequent dependency chain to the preceding load instruction, the canceling being based on the indicator” as claimed in claim 7.
The closest prior art of record Tran generally discloses forwarding data from a producer load instruction pipeline to a consumer instruction, and that a cache miss can occur. However, Tran does not disclose canceling control circuitry that cancels, all instructions in a subsequent dependency chain to a preceding load instruction, the canceling being based on the indicator as claimed. While, Reynolds (USPAT No. 10,514,925) discloses using kill bits and dependency vectors to cancel instructions dependent upon a producer load instruction causing a cache miss. However, Reynolds does not disclose canceling a subsequent dependency chain, wherein the canceling being based on the indicator as claimed in claim 7; and wherein the indicator indicates a pipeline that executes a producer instruction included in the plurality of instructions and uniquely identifies an execution stage of the producer instruction in the pipeline as claimed in claim 1, which claim 7 is dependent upon.
Therefore, the prior art of record has not taught either individually or in combination and together with all other claimed features the limitations discussed above. Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight.
Claims 8 is dependent upon claim 7 above, and is therefore similarly allowable over the prior art for the same reasons as claim 7 above.
Response to Arguments
Applicant’s arguments, see page 8 of remarks, filed on 1/16/2026, with respect to previous to claim objections have been fully considered and are persuasive. Therefore, the previous claim objections have been withdrawn.
Applicant argues the previous contingent claim interpretations of claim 16, on page 8 of the remarks in the substance that:
“"when" phrase in claim 16 was interpreted as a contingent limitation. The Examiner's suggested correction was much appreciated. Contingent interpretation is no longer applicable to claim 16 in view of the above amendments to claim 16.”
The examiner respectfully disagrees with the applicant’s assertions above because although the limitation “when” has been amended, the newly added limitation states “in response to” which is also considered to be contingent in a method claim. The language remains contingent in a method claim because a cache miss of a preceding load instruction may not be encountered. The examiner suggests the applicant amend the claim to state “...detecting a cache miss of a preceding load instruction in a dependency chain of the producer instruction, and in response to the detecting, at the scheduler canceling all instructions …” as to positively recite that the cache miss is occurring in the method claim.
Applicant's arguments filed on 1/16/2026, with respect to the 35 USC 103 rejections of Tran and Jiang have been fully considered but they are not persuasive. Therefore, the previous 35 USC 103 rejections in view of Tran and Jiang with regards to claims 1 and 10 have been maintained.
Claims 2-3, 5-6, 9, 11-12 and 14-18 are argued at least based upon their dependencies upon one of independent claims 1 and 10 above, and therefore remain rejected for similar reasons as independent claims 1 and 10 above.
Applicant argues the previous 103 rejections of similar claims 1 and 10, on page 10 of the remarks filed on 1/16/2026, in the substance that:
“As quoted above, Tran appears to merely describe that the Type control circuit 1768 stores each Type Entry 1760 into the particular Type register pertaining to a producer instruction destination operand, and that Type Entries are fed to a mux 1765 controlled by the Issuing Instruction: Query scoreboard for each register operand needed, but does not describe "the control circuitry holds a plurality of the indicators each indicating the pipeline of the producer instruction for each of the plurality of consumer instructions" (underlined emphasis added) of claims 1 and 10.
Hence, the noted feature(s) of claims 1 and 10 is a distinction over Tran. The noted feature(s) also is a distinction over Jiang as evidenced, e.g., by the Office Action. That is, the Office Action does not assert Jiang as disclosing the noted feature(s) of claim 1. Besides, Teruyama does not describe or suggest the feature(s) of claims 1 and 10, individually or in combination of Trans and/or Jiang.”
It appears the applicant is arguing above that Tran does not disclose storing a plurality of indicators each indicating the pipeline of the producer instruction for each of the plurality of consumer instructions. However, the examiner respectfully disagrees.
Tran discloses in paragraphs [0094-0098] and Figs. 4-5 a scoreboard storing, a plurality of indicators, wherein each indicator includes seven bits (see [0098]), wherein two of the bits of the seven-bit indicators are type bits that indicate the pipeline of each producer instruction which produces a result of a register used as a source operand of a consumer instruction (e.g. it indicates the pipeline the producer instruction which forwards operand data to a consumer instruction is executed) (see [0013 and abstract]). Thus, each of the indicators indicating a pipeline of the producer instructions is for each of the plurality of consumer instructions (e.g. candidate instructions which are dependent upon producer instructions).
The examiner notes that Tran is similar to applicants’ own disclosure of indicators as stated in paragraphs [0109-0110] of the instant application, as it appears the instant applications indicators (PS information 207) includes a stage ID 208 for each operand and a pipeline ID 209, which is an example of the pipeline identification information of a pipeline to which the producer instruction has been issued. Thus, applicants’ disclosure discloses indicators for each of the operands used by consumer instructions. Thus, if the indicators which indicate pipeline of producer instructions are used by consumer instructions to identify source operand information, they would indicate the pipeline of the producer instruction for each of the consumer instructions which depend upon the producer instructions.
Therefore, the indicators of Tran which indicate the pipeline of producer instructions (as disclosed in Figs. 4-5), that are used by each of the candidate dependent instructions (consumer instructions) are for each of the consumer instructions which utilize the indicators of the scoreboards to be issued. Thus, Tran does disclose the amended claim language.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183