Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to response to application 18/100270 filed on 01/23/23.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Oath/Declaration
The oath/declaration filed on January 23th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12, 14-16 and 18-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parks et al. (US Pub. 2020/0234242).
As to claim 1 the prior art teaches a finite state machine repair circuitry comprising:
at least one control unit, and at least one memory for storing instructions to be executed by the at least one control unit, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine (see fig 5a-5c element 500 and 550) repair circuitry at least to perform:
causing overriding (see paragraph 0190) at least one of one or more input signals and/or one or more output signals of a finite state machine circuit by corresponding one or more override signals generated by the finite state machine (see fig 5a-5c element 500 and 550) repair circuitry so as to a form a channel mimicking, fully or partly, correct operation of said finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 00180-0185 and 0190-0191, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)).
As to claim 2, the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to operate the channel based on the one or more input signals of the finite state machine circuit (see fig 3a-3d paragraph 0151-0154).
As to claim 3 the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to perform:
maintaining, in said at least one memory, command information for one or more channels for fully or partly overriding one or more finite state machine circuits, wherein the command information defines, for each channel, at least a set of one or more commands for operating the channel so that correct operation of a corresponding finite state machine circuit is replicable by the finite state machine repair circuitry see fig 5a-5c paragraph 00185-0191);
and operating the channel according to the command information (see fig 5a-5c, fig 6a-6b 0190-0197).
As to claim 4 the prior art teaches further comprising: a control interface, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to start the operating of the channel according to the command information maintained in said at least one memory from a start address of said at least one memory defined, before the operating of the channel, via the control interface and to end the operating of the channel according to the command information when a pre-defined end command is read (see fig 4-6 and 0179-0183).
As to claim 5 the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to perform the overriding of said finite state machine circuit also in response to receiving a software request for activating the channel via the control interface and/or in response to receiving a hardware request for activating the channel (see fig 4-6 and 0182-0185).
As to claim 6 the prior art teaches wherein said at least one of the one or more input signals and/or the one or more output signals comprises all or at least one of the one or more output signals of the finite state machine circuit (see fig 5a-5c, 6a-6b and 0184-0191).
As to claim 7 the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to perform the causing of the overriding separately for a plurality of finite state machine circuits, the plurality of finite state machine circuits comprising the finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 00180-0185 and 0190-0191, paragraph 0190-0191 teach override signal generated by FSM (finite state machine).
As to claim 8 the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to perform:
monitoring values of one or more external feedback signals for triggering operation of one or more finite state machine circuits comprising the finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 0178-0183);
and performing the causing of the overriding in response to detecting a value for one of the one or more external feedback signals satisfying one or more predefined criteria (see fig 5a-5c element 500 and 550 paragraph 0181-0187).
As to claim 9, the prior art teaches wherein the one or more pre-defined criteria comprise one or more pre-defined values (see fig 5a-5c fig 6a-6b paragraph 00185-0190)
As to claim 10 the prior art teaches wherein the one or more external feedback signals comprise a plurality of external feedback signals and the one or more finite state machine circuits comprise a plurality of finite state machine circuits, the one or more pre-defined criteria being defined separately for the plurality of external feedback signals (see fig 5a-5c fig 6a-6b paragraph 00190-0200).
As to claim 11 the prior art teaches wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to cause the overriding by at least causing configuration of first overriding means preceding the finite state machine circuit to output at least one first override signal receivable from the finite state machine repair circuitry to the finite state machine circuit, wherein the first overriding means comprise one or more first override multiplexers and/or one or more first logical OR gates and/or one or more first logical AND gates (see fig 5a-5c and 6a-6b paragraph 0184-0194, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)); and/or causing configuration of second overriding means following the finite state machine circuit to output at least one second override signal receivable from the finite state machine repair circuitry, wherein the second overriding means comprise one or more second override multiplexers and/or one or more second logical OR gates and/or one or more second logical AND gates (see fig 5a-5c, 6a-6b and 0190-0197, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)).
As to claim 12 the prior art teaches further comprising:
an arbiter for performing arbitration for two or more channels requested, via software and/or hardware requests, for activating two or more channels for overriding, fully or partly, two or more of the plurality of finite state machine circuits, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry to cause the overriding also in response to receiving a software or hardware request for activating the channel (see fig 5a-5c 0188-0192);
and a second multiplexer configured to receive hardware requests for activating channels and to output at least one of said hardware requests to the arbiter (see fig 5a-5c paragraph 0201-0208)
As to claim 14 the prior art teaches further comprising: a timer for implementing timing functionalities of the channel for, fully or partly, overriding the finite state machine circuit (see fig 5a-5c 0177-0180).
As to claim 15 the prior art teaches further comprising: a plurality of timers for implementing timing functionalities of a plurality of channels for, fully or partly, overriding the plurality of finite state machine circuit (see fig 5a-5c 6a-6b, paragraph 0191 and 0206-0210).
As to claim 16, the prior art teaches further comprising: a first multiplexer configured to receive the one or more external feedback signals and to output at least one of the one or more external feedback signals to the at least one control unit (see fig 5a-5c 6-7 paragraph 0208-0215).
As to claim 18 the prior art teaches A system comprising: a finite state machine repair circuitry comprising: at least one control unit, and at least one memory for storing instructions to be executed by the at least one control unit, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry at least to perform: causing overriding at least one of one or more input signals and/or one or more output signals of a finite state machine circuit by corresponding one or more override signals generated by the finite state machine repair circuitry so as to a form a channel mimicking, fully or partly, correct operation of said finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 00180-0185 and 0190-0191, paragraph 0190-0191 teach override signal generated by FSM (finite state machine));
first overriding means for overriding one or more inputs of one or more finite state machine circuits with one or more first override signals received from the finite state machine repair circuitry, wherein the first overriding means comprise one or more first override multiplexers and/or one or more first logical OR gates and/or one or more first logical AND gates (see fig 5a-5c and 6a-6b paragraph 0184-0194, paragraph 0190-0191 teach override signal generated by FSM (finite state machine));
and second overriding means for overriding one or more outputs of the one or more finite state machine circuits with one or more second override signals received from the finite state machine repair circuitry, wherein the second overriding means comprise one or more second override multiplexers and/or one or more second logical OR gates and/or one or more second logical AND gates (see fig 5a-5c, 6a-6b and 0190-0197, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)).
As to claim 19 the prior art teaches a method comprising: causing overriding at least one of one or more input signals and/or one or more output signals of a finite state machine circuit by corresponding one or more override signals so as to a form a channel mimicking, fully or partly, correct operation of said finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 00180-0185 and 0190-0191, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)).
As to claim 20 the prior art teaches a non-transitory computer readable medium comprising program instructions stored thereon for performing at least the following: causing overriding at least one of one or more input signals and/or one or more output signals of a finite state machine circuit by corresponding one or more override signals so as to a form a channel mimicking, fully or partly, correct operation of said finite state machine circuit (see fig 5a-5c element 500 and 550 paragraph 00180-0185 and 0190-0191, paragraph 0190-0191 teach override signal generated by FSM (finite state machine)).
Allowable Subject Matter
Claim 13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851