Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 30 July 2026 have been fully considered but they are not persuasive.
Regarding the 35 U.S.C. § 102 rejection of claim 1 using the Sakamoto reference, the applicant argues on pages 9-10 of the Remarks that Sakamoto does not teach the limitation of “the heat protective layer is entirely bound by one or more of the encapsulant, the housing, one or more of the terminal elements and/or the printed circuit board” since the hollow portion 26 is partly bounded by communication openings in the case member 12. The examiner respectfully disagrees. Using broadest reasonable interpretation, the words of the claims must be given their plain meaning, i.e., the ordinary and customary meaning given to the term by those of ordinary skill in the art.1 Hence, the limitation above can be construed as requiring the heat protective layer to be contained or confined2 within the physical dimensions of any one of the elements listed, or within a combination of one or more of the elements listed. In the case of Sakamoto, Figs. 6 & 7, reproduced below, disclose the heat protective layer (26; ¶ [0039] discloses hollow portion 26 as an internal space) being entirely enclosed within the dimensional limits of the housing (12), with the housing also enclosing other elements listed, such as encapsulant (14), terminal elements (7), and printed circuit board (20).
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Sakamoto Figs. 6 and 7.
Regarding the 35 U.S.C. § 103 rejection of claim 1 using the Matsuoka in view of Sakamoto reference, the applicant argues on pages 11-12 of the Remarks that Matsuoka does not teach the limitation of “the heat protective layer is entirely bound by one or more of the encapsulant, the housing, one or more of the terminal elements and/or the printed circuit board” since the gel 14 is partly bound by the insulating substrate, the metal wiring patterns 7a to 7c, and the semiconductor element 11. The examiner respectfully disagree. Using broadest reasonable interpretation, the words of the claims must be given their plain meaning, i.e., the ordinary and customary meaning given to the term by those of ordinary skill in the art.3 Hence, the limitation above can be construed as requiring the heat protective layer to be contained or confined within the physical dimensions of one of the elements listed, or within a combination of one or more of the elements listed4. In the case of Matsuoka, Fig. 1 clearly shows the heat protective layer being contained within the physical dimensions of the physical entity that comprises the housing (1 & 2), encapsulant (15), terminals (8 & 40), and top plate (Matsuoka in view of Sakamoto replaces the top plate with a printed circuit board)5.
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Matsuoka Fig. 1
Regarding the 35 U.S.C. § 103 rejection of claims 8 and 22 using the Matsuoka in view of Sakamoto reference, the applicant argues on pages 12-13 of the Remarks that Matsuoka does not teach the limitation of “the plurality of terminal elements is arranged distant from the heat protective layer” since power terminal 10 clearly extends into gel 14. The examiner respectfully disagree. The claim terms does not necessarily require the terminal elements to be entirely arranged distant from the heat protective layer. Instead, the limitation can be construed to mean that at least a portion of the terminal elements is arranged distant from the heat protective layer. Fig. 2 of Matsuoka clearly shows portions (P) of the terminals (8 and 10) are arranged distant from the heat protective layer (14).
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Matsuoka Fig. 2
Regarding the 35 U.S.C. § 103 rejection of claims 22-24 using the Matsuoka in view of Sakamoto reference, the applicant argues on pages 13-16 that there’s no reason for a person of ordinary skill to replace Matsuoka’s top plate 3 with Sakamoto’s circuit board 20, i.e., add electrical connections to the top plate, since Matsuoka teaches that vibrations may cause solder cracking and failure of the semiconductor device in the vicinity of the top plate and allegedly teaches isolating the top plate from metal wiring patterns 7a and 7b of the substrate 5. The examiner respectfully disagree. First, the ordinary skilled artisan would find it obvious, prior to the effective date of the invention, that the substitution of the printed circuit board would lead to the predictable result6 of adding more electrical components to the device7. Second, the ordinary skilled artisan would also find it obvious that the substitution would improve the device density5,8. Lastly, the person of ordinary skill is also a person of ordinary creativity, not an automaton9. As explained in Matsuoka ¶ [0029], the vibration is reduced or eliminated by having folded portions 10c and 10d of the power terminal, with Fig. 1 showing these folded portions, being themselves electrical connections, disposed on a top surface of the top plate. In other words, Matsuoka has resolved the issue of vibration. Furthermore, there are no disclosures in Matsuoka that prohibits adding any electrical components or connections on the top plate due to an alleged inoperability of the device. Rather, Matsuoka encourages disposing and firmly attaching electrical connections to the top surface of the top plate10. Since Matsuoka does not teach away from transforming the top plate to a printed circuit board having additional electrical components, then the person of ordinary skill may find it obvious to substitute Matsuoka’s top plate with Sakamoto’s printed circuit board while retaining favorable aspects of Matsuoka’s invention, i.e., bolted and secured terminal loops, if the said artisan is faced with the similar vibration issue in their device.
Regarding the 35 U.S.C. § 103 rejection of claim 1 using the Masumoto11 in view of Furukawa reference, the applicant argues on pages 16-17 of the Remarks that the ordinary skilled artisan would not consider the cover 20 to be part of the heat protective layer. The examiner respectfully disagrees. Masumoto’s paragraphs [0026], [0030], and [0032] disclose how parts of the cover, such as the concave portion 20a and fitting portion 20b, interacts with the air gap 22 in order to reduce stress and increase the reliability of the product. To put in a different way, the ordinary artisan would know that air expands or contracts as the temperature of the device rises or falls. Since the cover preserves the structure of the air gap, then the ordinary skilled artisan would consider the cover to be part of the heat protective layer.
Regarding the 35 U.S.C. § 103 rejection of claims 2 and 18 using the Masumoto in view of Furukawa reference, the applicant argues on pages 17-18 of the Remarks that Masumoto’s cover contains a fitting portion 20b that disqualifies it from being “fully embedded in the encapsulant.” The examiner respectfully disagrees. Using broadest reasonable interpretation, the words of the claims must be given their plain meaning, i.e., the ordinary and customary meaning given to the term by those of ordinary skill in the art.12 Hence, the limitation above can be construed as the heat protective layer being fully under a top surface of the encapsulation13. This is clearly shown in Fig. 1 of Masumoto wherein both cover (20) and air gap (22), together acting as a heat protective layer, are below the top surface of encapsulant (21).
Regarding the 35 U.S.C. § 103 rejection of claim 19 using the Masumoto in view of Furukawa reference, the applicant argues on page 19 of the Remarks that Masumoto does not disclose that the heat protective layer [sic: cavity]14 is “surrounded by a casing,” citing a dictionary entry that “surround” means to enclose on all sides. The examiner respectfully disagrees. Using broadest reasonable interpretation, the words of the claims must be given their plain meaning, i.e., the ordinary and customary meaning given to the term by those of ordinary skill in the art.15 Hence, the limitation above can be construed as “the casing constituting part of the environment of the cavity16” and not necessarily require “the casing to surround all sides of the cavity”. Fig. 1 of Masumoto clearly shows the casing (20) being part of the immediate environment of cavity (22).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Sakamoto (US 2009/0086431 A1) as evidenced by MatWeb and Engineering Toolbox (see NPL mailed on 27 August 2025).
Regarding claim 1, Sakamoto teaches a power semiconductor module arrangement (Figs. 6A-6B and Fig. 7; see ¶ [0089] ), comprising:
a housing (12);
a substrate (18, see Fig. 2B and ¶ 0066) arranged inside the housing;
a printed circuit board arranged (20) inside the housing distant from and in parallel to the substrate (Fig. 6B shows 20 distant from and in parallel to 18);
a plurality of terminal elements (30, see Fig. 7) each extending from the substrate to the printed circuit board;
an encapsulant (14&16) at least partly filling an interior of the housing and covering the substrate and the printed circuit board; and
a heat protective layer (the air inside cavity 26 in Fig. 6B and the air outside and directly contacting the device as shown in Fig. 6A; 26 is a hollow space made of air; air protects the device from overheating, see ¶ [0055], ¶ [0059], ¶ [0088]; hence 26 is a heat protective layer) arranged inside the housing between the substrate and the printed circuit board (Fig. 6B shows 26 inside 12 and between 18 and 20 along the vertical axis ), and extending in a plane that is parallel to the substrate and the printed circuit board (Fig. 6B shows 26 parallel to both 18 and 20), wherein the heat protective layer is entirely bounded by one or more of the encapsulant (14, see Fig. 6B), the housing (12A & 12B), one or more of the terminal elements (30, see Fig. 7: note 30 and 26 are not labeled in Fig. 7 but is otherwise shown in Fig. 6A-6B), and/or the printed circuit board (20, see Fig. 6B), and
wherein a thermal resistance of the heat protective layer (thermal conductivity of air: 0.0262 W/mK as evidenced by Engineering Toolbox) is greater than a thermal resistance of the encapsulant (¶ [0051]: 14 is made of epoxy; thermal conductivity of epoxy is 0.167-0.795 W/mK as evidenced by MatWeb; hence, air has a lower thermal conductivity than epoxy; since thermal resistance is inversely proportional to thermal conductivity, then the thermal resistance of air is greater than that of epoxy).
Regarding claim 3, the power semiconductor module arrangement of claim 1, wherein the heat protective layer:
directly adjoins the printed circuit board with a first side (Fig. 6B shows the top surfaces of the cavity of 26 directly contacting the bottom side of 20); and
directly adjoins the encapsulant with a second side opposite the first side (Fig. 6B shows the bottom side of the cavity of 26 directly contacting 14), wherein the second side faces the substrate (the bottom side of the cavity of 26 faces 18).
Regarding claim 4, the power semiconductor module arrangement of claim 1, wherein the heat protective layer is formed by a cavity (the cavity of housing 12 that forms 26) filled with air (¶ [0082]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 8 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as evidenced by Matweb (see NPL mailed on 27 August 2025 and NPL on silicone thermal property).
Regarding claim 1, Matsuoka teaches a power semiconductor module arrangement, comprising:
a housing (1 & 2);
a substrate (5) arranged inside the housing;
a top plate (3) arranged inside the housing distant from (3 is distant from 5 along the vertical axis) and in parallel to the substrate (parallel along the horizontal axis);
a plurality of terminals (8 & 10) each extending from the substrate to the top plate;
an encapsulant (15; ¶ [0013]: 15 is made of epoxy) at least partly filling an interior (space filled by 15) of the housing and covering the substrate (from a top view perspective, 15 covers the substrate 5) and the top plate (3); and
a heat protective layer (14; ¶ [0014]: 14 is made of silicone and is a heat protective layer due to its thermal resistance, see below) arranged inside the housing between the substrate and the top plate (as shown in Fig. 1, 14 is between 3 and 5 along the vertical axis), and extending in a plane (horizontal plane) that is parallel to the substrate and the top plate, wherein the heat protective layer is entirely bound by one or more of the encapsulant (15), the housing (1 & 2), one or more of the terminal elements (8 & 10), and/or (plain meaning: used as a function word to indicate that two words or expressions are to be taken together or individually) the top plate (3; as shown in Fig. 1, 14 is entirely bounded by 15, 1& 2, 8&10 and/or 3), and
wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of silicone: 0.06 -0.163 W/m-K) is greater than a thermal resistance of the encapsulant (as evidenced by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal conductivity is inversely proportional to the thermal resistance and since the thermal conductivity of silicone is smaller than that of epoxy, then the thermal resistance of silicone is greater than that of epoxy).
However, Matsuoka does not teach the top plate to be a printed circuit board.
Sakamoto, in the same field of invention teaches the top plate (20, see Fig. 2A) that is parallel to and distant from a substrate (18) is a printed circuit board (see ¶ [0044] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sakamoto into the device of Matsuoka to substitute the top plate of Matsuoka with the printed The ordinary artisan would have been motivated to modify Matsuoka in the manner set forth above for at least the purpose of using the conductive pattern (21, Sakamoto ¶ [0044] ) of the printed circuit board to mount and electrically connect electronic components (24, ¶ [0049], [0050]: capacitor, microcomputer, crystal oscillators ), which are required components in an inverter device (Fig. 4 and ¶ [0077]-[0078] ) for the further purpose of decreasing the size of the device (¶ [0015]).
Regarding claim 8, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, but do not teach: wherein each of the plurality of terminal elements is arranged distant from the heat protective layer.
Matsuoka, through a different embodiment (Fig. 2), teaches the plurality of terminal elements is arranged distant from the heat protective layer (8 and 10 are embedded in casing 2 and away from heat protective layer 14).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Matsuoka into the device of Matsuoka et al. to arrange the plurality of terminal elements to be distant from the heat protective layer. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of substituting different methods (Fig. 1 versus Fig. 2) of connecting the plurality of terminals to the substrate, with the embodiment in Fig. 1 directly connecting the terminals to wiring patterns (7c) on the substrate, whereas, the embodiment in Fig. 2 connects terminals to MOSFETs (11a, 11b) through bonding wires (12).
Regarding claim 22, Matsuoka teaches a semiconductor module arrangement, comprising:
a housing (1 & 2);
a substrate (5) arranged inside the housing;
a top plate (3) arranged inside the housing distant from (3 is distant from 5 along the vertical axis) and in parallel to the substrate (parallel along the horizontal axis);
an encapsulant (15; ¶ [0013]: 15 is made of epoxy) at least partly filling an interior (space filled by 15) of the housing and covering the substrate (from a top view perspective, 15 covers the substrate 5) and the top plate (3);
a plurality of terminal elements (8 & 10); and
a heat protective layer (14; ¶ [0014]: 14 is made of silicone and is a heat protective layer due to its thermal resistance, see below) arranged inside the housing between the substrate and the top late (as shown in Fig. 1, 14 is between 3 and 5 along the vertical axis), and extending in a plane (horizontal plane) that is parallel to the substrate and the top plate, wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of silicone: 0.06 -0.163 W/m-K) is greater than a thermal resistance of the encapsulant (as evidenced by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal conductivity is inversely proportional to the thermal resistance and since the thermal conductivity of silicone is smaller than that of epoxy, then the thermal resistance of silicone is greater than that of epoxy),
wherein each of the plurality of terminal elements (8 and 10) extends from the substrate (5) to the top plate (3; see Fig. 1).
However, Matsuoka does not teach the top plate to be a printed circuit board.
Sakamoto, in the same field of invention teaches the top plate (20, see Fig. 2A) that is parallel to and distant from a substrate (18) is a printed circuit board (see ¶ [0044] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sakamoto into the device of Matsuoka to substitute the top plate of Matsuoka with a printed circuit board. The ordinary artisan would have been motivated to modify Matsuoka in the manner set forth above for at least the purpose of using the conductive pattern (21, Sakamoto ¶ [0044] ) of the printed circuit board to mount and electrically connect electronic components (24, ¶ [0049], [0050]: capacitor, microcomputer, crystal oscillators ), which are required components in an inverter device (Fig. 4 and ¶ [0077]-[0078] ) for the further purpose of decreasing the size of the device (¶ [0015]).
However, Matsuoka et al. do not teach: wherein each of the plurality of terminal elements is arranged distant from the heat protective layer.
Matsuoka, through a different embodiment (Fig. 2), teaches the plurality of terminal elements is arranged distant from the heat protective layer (8 and 10 are embedded in casing 2 and away from heat protective layer 14).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Matsuoka into the device of Matsuoka et al. to arrange the plurality of terminal elements to be distant from the heat protective layer. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of substituting different methods (Fig. 1 versus Fig. 2) of connecting the plurality of terminals to the substrate, with the embodiment in Fig. 1 directly connecting the terminals to wiring patterns (7c) on the substrate, whereas, the embodiment in Fig. 2 connects terminals to MOSFETs (11a, 11b) through bonding wires (12).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as applied to claim 1 above, and further in view of Lee (US 2020/0275583 A1).
Regarding claim 9, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, wherein the substrate is arranged on a first heat sink (1, see Matsuoka Fig. 1).
However, Matsuoka et al. do not teach the device further comprising: at least one heat conduction element coupled to the printed circuit board with a first end, and to the first heat sink with a second end and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink.
Lee, in the same field of invention, teaches a device (Fig. 12) further comprising: at least one heat conduction element (3&4, see ¶ [0053]) coupled to a printed circuit board (21&22) with a first end (top end of 3&4), and to a first heat sink (1, see ¶ [0052]) with a second end (bottom end of 3&4) and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink (¶ [0052], ¶ [0055]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the device of Matsuoka et al. to provide at least one heat conduction element coupled to the printed circuit board with a first end, and to the first heat sink with a second end and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of providing another pathway to conduct the heat generated by the printed circuit board away from the board and towards the heat sink for improved heat dissipation (Lee ¶ [0052]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as applied to claim 1 above, and further in view of Hirose (US 2018/0061736 A1).
Regarding claim 10, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, but do not teach the device further comprising: at least one heat sink thermally coupled to the printed circuit board and configured to conduct heat away from the printed circuit board, wherein the printed circuit board is arranged between the at least one heat sink and the substrate.
Sakamoto further teaches at least one package component device (24, see Fig. 2A) mounted on the top surface of the printed circuit board.
Hirose, in the same field of invention, teaches a device (Fig. 3L) comprising: at least one heat sink (55&33; 55 is a heat dissipating sheet and 33 is a heat spreader; using BRI, 55&53 is a heat sink) thermally coupled to a package component device (43) and configured to conduct heat away from the package component device (¶ [0123]), wherein the package component device is arranged between the at least one heat sink and a substrate (41; Fig. 3L shows 43 in between 55 and 41).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hirose into the device of Sakamoto to thermally couple at least one heat sink to the printed circuit board, with the heat sink configured to conduct heat away from the printed circuit board and wherein the printed circuit board is arranged between the at least one heat sink and the substrate. The ordinary artisan would have been motivated to modify Sakamoto in the manner set forth above for at least the purpose of improving the cooling efficiency of package component devices that are mounted on the printed circuit board (Hirose ¶ [0123], ¶ [0005]), noting that Sakamoto teaches package component devices mounted on the printed circuit board, as stated above.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as applied to claim 1 above, and further in view of Lee (US 2020/0275583 A1) and Hirose (US 2018/0061736 A1).
Regarding claim 11, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, and further teach: wherein the substrate is arranged on a first heat sink (1, see Matsuoka Fig. 1).
However, Matsuoka et al. do not teach the device further comprising:
At least one heat conduction element coupled to the printed circuit board with a first end, and to a first heat sink with a second end, and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink.
Lee, in the same field of invention, teaches a device (Fig. 12) further comprising: At least one heat conduction element (3&4) coupled to a printed circuit board (21&22) with a first end (top end of 3&4), and to a first heat sink (1) with a second end (bottom end of 3&4), and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink (¶ 0052, ¶ 0055).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Lee into the device of Matsuoka et al. to provide at least one heat conduction element coupled to a printed circuit board with a first end, and to a first heat sink with a second end and the at least one heat conduction element is configured to conduct heat away from the printed circuit board to the first heat sink. The ordinary artisan would have been motivated to modify Sakamoto in the manner set forth above for at least the purpose of providing another pathway to conduct the heat generated by the printed circuit board away from the board and towards the heat sink for improved heat dissipation (Lee ¶ [0052]).
Sakamoto further teaches at least one package component device (24, see Fig. 2A) mounted on the top surface of the printed circuit board.
However, Matsuoka et al. do not teach:
at least one second heat sink thermally coupled to the printed circuit board and configured to conduct heat away from the printed circuit board, wherein the printed circuit board is arranged between the at least one second heat sink and the substrate.
Hirose, in the same field of invention, teaches a device (Fig. 3L) comprised of at least one second heat sink (55&33) thermally coupled to a package component device (43) and configured to conduct heat away from the package component device (¶ [0123]), wherein the package component device is arranged between the at least one second heat sink and the substrate (41; Fig. 3L shows 43 in between 55 and 41).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hirose into the device of Matsuoka et al. to thermally couple at least one second heat sink to a printed circuit board, with the second heat sink configured to conduct heat away from the printed circuit board and wherein the printed circuit board is arranged between the second heat sink and a substrate in a power semiconductor module arrangement at least comprising of a housing, the substrate inside the housing, the printed circuit board inside the housing and distant from and in parallel to the substrate, and above-mentioned second heat sink. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of improving the cooling efficiency of package component devices that are mounted on the printed circuit board (Hirose ¶ [0123], ¶ [0005]), noting that Sakamoto teaches package component devices mounted on the printed circuit board, as stated above.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as applied to claim 1 above, and further in view of Sato (WO 2022/085284 A1; see NPL for English translation).
Regarding claim 12, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, and further teach the heat protective layer to be comprised of silicone (Matsuoka ¶ [0014]). However, Matsuoka et al. do not teach the device wherein the heat protective layer comprises a glass or plastic material.
Sato, in the same field of invention, teaches a heat protective layer (Title: heat conductive sheet) that can be made of silicone (¶ [0019] ) and/or other of plastic materials (¶ [0015]-[0019]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Matsuoka et al. to use a plastic material in lieu of the silicone material. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of using the silicone and/or plastic materials as binder resins for the further purpose of adding fillers (3 & 4; note: ¶ [0022]: filler 3 is made of glass, i.e., silica) in the heat protective layer in order to improve the thermal characteristics of the heat protective layer (¶ [0003]-[0006] ) and to increase the filling rate of the fillers (¶ [0002] ).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) as applied to claim 1 above, and further in view of Bunyan (US 2003/0222249 A1).
Regarding claim 13, Matsuoka et al. teach the power semiconductor module arrangement of claim 1, wherein the heat protective layer has a higher thermal resistivity than the material of the encapsulant (as evidenced by Matweb, the thermal conductivity of silicone: 0.06 -0.163 W/m-K and the thermal conductivity of epoxy is 0.167-0.795 W/m-K; see also claim 1 rejection for details). Matsuoka further teaches the heat protective layer comprising a material (¶ [0014]: 14 is made of silicone). However, Matsuoka et al. do not teach the heat protective layer comprises a plurality of particles or fillers distributed therein.
Bunyan, in the same field of invention, teaches a thermally conductive gap filler (see Title) made of silicone (¶ [0020]: “The gel component may be… a silicone gel” ) and further comprising of a plurality of particles or fillers distributed therein (¶ [0020] : “a filler which may be thermally and/or electrically-conductive particles”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Bunyan into the device of Matsuoka et al. to add a plurality of particles or fillers together with the silicone material of the heat protective layer. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of improving the loading level of the material that comprises the heat protective layer and still be able to retain its high thermal resistivity, as compared to the material of the encapsulant (Bunyan ¶ [0020] ).
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka (US 2014/0167241 A1) in view of Sakamoto (US 2009/0086431 A1) and Sato (WO 2022/085284 A1; see NPL for English translation) as evidenced by Matweb (see NPL mailed on 27 August 2025 and NPL on silicone thermal property).
Regarding claim 23, Matsuoka teaches a power semiconductor module arrangement, comprising:
a housing (1 & 2);
a substrate (5) arranged inside the housing;
a top plate (3) arranged inside the housing distant from (3 is distant from 5 along the vertical axis) and in parallel to the substrate (parallel along the horizontal axis);
an encapsulant (15; ¶ [0013]: 15 is made of epoxy) at least partly filling an interior (space filled by 15) of the housing and covering the substrate (from a top view perspective, 15 covers the substrate 5) and the top plate (3); and
a heat protective layer (14; ¶ [0014]: 14 is made of silicone and is a heat protective layer due to its thermal resistance, see below) arranged inside the housing between the substrate and the printed circuit board (as shown in Fig. 1, 14 is between 3 and 5 along the vertical axis), and extending in a plane (horizontal plane) that is parallel to the substrate and the printed circuit board,
wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of silicone: 0.06 -0.163 W/m-K) is greater than a thermal resistance of the encapsulant (as evidenced by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal conductivity is inversely proportional to the thermal resistance and since the thermal conductivity of silicone is smaller than that of epoxy, then the thermal resistance of silicone is greater than that of epoxy).
However, Matsuoka does not teach the top plate to be a printed circuit board.
Sakamoto, in the same field of invention teaches the top plate (20, see Fig. 2A) that is parallel to and distant from a substrate (18) is a printed circuit board (see ¶ [0044] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sakamoto into the device of Matsuoka to substitute the top plate of Matsuoka with the printed The ordinary artisan would have been motivated to modify Matsuoka in the manner set forth above for at least the purpose of using the conductive pattern (21, Sakamoto ¶ [0044] ) of the printed circuit board to mount and electrically connect electronic components (24, ¶ [0049], [0050]: capacitor, microcomputer, crystal oscillators ), which are required components in an inverter device (Fig. 4 and ¶ [0077]-[0078] ) for the further purpose of decreasing the size of the device (¶ [0015]).
Matsuoka further teaches the heat protective layer to be comprised of silicone (Matsuoka ¶ [0014]). However, Matsuoka et al. do not teach the device wherein the heat protective layer comprises a glass or plastic material.
Sato, in the same field of invention, teaches a heat protective layer (Title: heat conductive sheet) that can be made of silicone (¶ [0019] ) and/or other of plastic materials (¶ [0015]-[0019] of English translation).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Matsuoka et al. to use a plastic material in lieu of the silicone material. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of using the silicone and/or plastic materials as binder resins for the further purpose of adding fillers (3 & 4; note: ¶ [0022]: filler 3 is made of glass, i.e., silica) in the heat protective layer in order to improve the thermal characteristics of the heat protective layer (¶ [0003]-[0006] ) and to increase the filling rate of the fillers (¶ [0002] ).
Regarding claim 24, Matsuoka teaches a power semiconductor module arrangement, comprising:
a housing (1 & 2);
a substrate (5) arranged inside the housing;
a top plate (3) arranged inside the housing distant from (3 is distant from 5 along the vertical axis) and in parallel to the substrate (parallel along the horizontal axis);
an encapsulant (15; ¶ [0013]: 15 is made of epoxy) at least partly filling an interior (space filled by 15) of the housing and covering the substrate (from a top view perspective, 15 covers the substrate 5) and the top plate (3); and
a heat protective layer (14; ¶ [0014]: 14 is made of silicone and is a heat protective layer due to its thermal resistance, see below) arranged inside the housing between the substrate and the printed circuit board (as shown in Fig. 1, 14 is between 3 and 5 along the vertical axis), and extending in a plane (horizontal plane) that is parallel to the substrate and the printed circuit board, wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of silicone: 0.06 -0.163 W/m-K) is greater than a thermal resistance of the encapsulant (as evidenced by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal conductivity is inversely proportional to the thermal resistance and since the thermal conductivity of silicone is smaller than that of epoxy, then the thermal resistance of silicone is greater than that of epoxy).
However, Matsuoka does not teach the top plate to be a printed circuit board.
Sakamoto, in the same field of invention teaches the top plate (20, see Fig. 2A) that is parallel to and distant from a substrate (18) is a printed circuit board (see ¶ [0044] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sakamoto into the device of Matsuoka to substitute the top plate of Matsuoka with the printed. The ordinary artisan would have been motivated to modify Matsuoka in the manner set forth above for at least the purpose of using the conductive pattern (21, Sakamoto ¶ [0044] ) of the printed circuit board to mount and electrically connect electronic components (24, ¶ [0049], [0050]: capacitor, microcomputer, crystal oscillators ), which are required components in an inverter device (Fig. 4 and ¶ [0077]-[0078] ) for the further purpose of decreasing the size of the device (¶ [0015]).
Matsuoka further teaches the heat protective layer to be comprised of a material (¶ [0014] : silicone) and heat protective layer having a higher thermal resistivity than the material of the encapsulant (see above). However, Matsuoka et al. do not teach the device wherein the heat protective layer further comprises a plurality of particles or fillers distributed therein.
Sato, in the same field of invention, teaches a heat protective layer made of a silicon binder and further comprised a plurality of particles or fillers (3 and 4) distributed therein.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sato into the device of Matsuoka et al. add particles or fillers in the heat protective layer. The ordinary artisan would have been motivated to modify Matsuoka et al. in the manner set forth above for at least the purpose of improve the thermal characteristics of the heat protective layer (¶ [0003]-[0005] ) and to increase the filling rate of the fillers (¶ [0002] ).
Claims 1, 2, 4-5, 8, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Masumoto (US 2020/0286799 A1) in view of Furukawa (US 2013/0056883 A1) as evidenced by Matweb (see NPL mailed on 27 August 2025).
Regarding claim 1, Masumoto teaches a power semiconductor module arrangement, comprising:
a housing (10);
a substrate (1 & 2 & 3 & 4 & 5) arranged inside the housing;
a plurality of terminal elements (11 & 13 & & 14 & 15 & 16 & 17 & 19) each extending from the substrate;
an encapsulant (21) at least partly filling an interior of the housing and covering the substrate; and
a heat protective layer (20 & 22; note: 22 is an air gap) arranged inside the housing, and extending in a plane (horizontal plane) that is parallel to the substrate, wherein the heat protective layer is entirely bound by the one or more of the encapsulant (21: ¶ [0028]: 21 is made of epoxy), the housing (10), and/or (plain meaning: used as a function word to indicate that two words or expressions are to be taken together or individually) one or more of the terminal elements (14), and
wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of air is 0.0262 W/m-K) is greater than a thermal resistance of the encapsulant (as evidence by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal resistance is inversely proportional to the thermal conductivity, then air has a greater thermal resistance than epoxy).
However, Masumoto does not teach the device comprising of a printed circuit board arranged inside the housing distant from and in parallel to the substrate,
wherein the plurality of terminal elements extend from the substrate to the printed circuit board,
wherein the encapsulant covers the printed circuit board, and
wherein the heat protective layer is arranged between the substrate and the printed circuit board and extends in a plane that is parallel to the printed circuit board.
Furukawa, in the same field of invention, teaches a device (see Figs. 1, 2 or 4C or 5C) comprising of a printed circuit board (60) arranged inside the housing distant from and in parallel to the substrate (30),
wherein the plurality of terminal elements (21) extend from the substrate to the printed circuit board,
wherein the encapsulant (72) covers the printed circuit board, and
wherein the heat protective layer is arranged between the substrate and the printed circuit board and extends in a plane (horizontal plane) that is parallel to the printed circuit board (Masumoto in view of Furukawa teaches the heat protective layer of Masumoto to be within the first sealing layer 71 and below the second sealing layer 72; hence the heat protective layer is arranged between the substrate 30 and the printed circuit board 60).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Furukawa into the device of Masumoto to add a printed circuit board inside the housing, with the printed circuit board distant from and parallel to the substrate such that the plurality of terminals extend from the substrate to the printed circuit board and the encapsulant covers the printed circuit board and the heat protective layer is situated in between the substrate and the printed circuit board. The ordinary artisan would have been motivated to modify Masumoto in the manner set forth above for at least the purpose of using the printed circuit board as part of a control circuit with components (61) mounted on it (see Furukawa ¶ [0031]-[0032] ) for the further purpose of preventing delamination of the encapsulant around the printed circuit board (¶ [0004], ¶ [0038]-[0045] ).
Regarding claim 2, the power semiconductor module arrangement of claim 1, wherein the heat protective layer is arranged distant from the printed circuit board and is fully embedded in the encapsulant (see Masumoto Fig.1 shows 20& 22 fully embedded in 21)
Regarding claim 4, the power semiconductor module arrangement of claim 1, wherein the heat protective layer is formed by a cavity (cavity of 22, see Masumoto Fig. 1) filled with air.
Regarding claim 5, the power semiconductor module arrangement of claim 4, wherein the cavity is surrounded by a casing (20) comprising a material that is different from a material of the encapsulant (Masumoto ¶ [0028] explains that casing 20 has buoyancy when encapsulant 21 is filled; hence 20 is made of a material that is different from 21).
Regarding claim 8, the power semiconductor module arrangement of claim 1, wherein each of the plurality of terminal elements is arranged distant from the heat protective layer (Masumoto Fig. 1 shows terminals 11 & 13 arranged distant from 20 & 22).
Regarding claim 18, Masumoto teaches a power semiconductor module arrangement, comprising:
a housing (10);
a substrate (1 & 2 & 3 & 4 & 5) arranged inside the housing;
an encapsulant (21) at least partly filling an interior of the housing and covering the substrate; and
a heat protective layer (20 & 22; note: 22 is an air gap) arranged inside the housing above the substrate, and extending in a plane that is parallel to the substrate, wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of air is 0.0262 W/m-K) is greater than a thermal resistance of the encapsulant (as evidence by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal resistance is inversely proportional to the thermal conductivity, then air has a greater thermal resistance than epoxy), and
wherein the heat protective layer is arranged distant from the printed circuit board and is fully embedded in the encapsulant (the figures show 20 & 22 is within 21).
However, Masumoto does not teach the device to be comprised of a printed circuit board arranged inside the housing distant from and in parallel to the substrate,
wherein the encapsulant covers the printed circuit board, and
wherein the heat protective layer is in between the substrate and the printed circuit board and extends in a plan that is parallel to the substrate and the printed circuit board.
Furukawa, in the same field of invention, teaches a device (see Figs. 1, 2 or 4C or 5C) comprising of comprised of a printed circuit board (60) arranged inside the housing distant from and in parallel to the substrate (30),
wherein the encapsulant (72) covers the printed circuit board, and
wherein the heat protective layer is in between the substrate and the printed circuit board and extends in a plane (horizontal plane) that is parallel to the substrate and the printed circuit board (Masumoto in view of Furukawa teaches the heat protective layer of Masumoto to be within the first sealing layer 71 and below the second sealing layer 72; hence the heat protective layer is arranged between the substrate 30 and the printed circuit board 60)..
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Furukawa into the device of Masumoto to add a printed circuit board inside the housing, with the printed circuit board distant from and parallel to the substrate such that the encapsulant covers the printed circuit board and the heat protective layer is situated in between the substrate and the printed circuit board. The ordinary artisan would have been motivated to modify Masumoto in the manner set forth above for at least the purpose of using the printed circuit board as part of a control circuit with components (61) mounted on it (see Furukawa ¶ [0031]-[0032] ) for the further purpose of preventing delamination of the encapsulant around the printed circuit board (¶ [0004], ¶ [0038]-[0045] ).
Regarding claim 19, Masumoto teaches a power semiconductor module arrangement, comprising:
a housing (10);
a substrate (1 & 2 & 3 & 4 & 5) arranged inside the housing;
an encapsulant (21) at least partly filling an interior of the housing and covering the substrate; and
a heat protective layer (20 & 22; note: 22 is an air gap) arranged inside the housing above the substrate, and extending in a plane that is parallel to the substrate,
wherein a thermal resistance of the heat protective layer (as evidenced by Matweb, the thermal conductivity of air is 0.0262 W/m-K) is greater than a thermal resistance of the encapsulant (as evidence by Matweb, the thermal conductivity of epoxy is 0.167-0.795 W/m-K; since the thermal resistance is inversely proportional to the thermal conductivity, then air has a greater thermal resistance than epoxy),
wherein the heat protective layer is formed by a cavity filled with air (¶ [0028] ), and wherein the cavity is surrounded by a casing (20) comprising a material that is different from a material of the encapsulant (¶ [0028] explains that casing 20 has buoyancy when encapsulant 21 is filled; hence 20 is made of a material that is different from 21).
However, Masumoto does not teach the device to be comprised of a printed circuit board arranged inside the housing distant from and in parallel to the substrate,
wherein the encapsulant covers the printed circuit board, and
wherein the heat protective layer is in between the substrate and the printed circuit board and extends in a plan that is parallel to the substrate and the printed circuit board.
Furukawa, in the same field of invention, teaches a device (see Figs. 1, 2 or 4C or 5C) comprising of comprised of a printed circuit board (60) arranged inside the housing distant from and in parallel to the substrate (30),
wherein the encapsulant (70) covers the printed circuit board, and
wherein the heat protective layer is in between the substrate and the printed circuit board and extends in a plane (horizontal plane) that is parallel to the substrate and the printed circuit board (Masumoto in view of Furukawa teaches the heat protective layer of Masumoto to be within the first sealing layer 71 and below the second sealing layer 72; hence the heat protective layer is arranged between the substrate 30 and the printed circuit board 60)..
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Furukawa into the device of Masumoto to add a printed circuit board inside the housing, with the printed circuit board distant from and parallel to the substrate such that the encapsulant covers the printed circuit board and the heat protective layer is situated in between the substrate and the printed circuit board. The ordinary artisan would have been motivated to modify Masumoto in the manner set forth above for at least the purpose of using the printed circuit board as part of a control circuit with components (61) mounted on it (see Furukawa ¶ [0031]-[0032] ) for the further purpose of preventing delamination of the encapsulant around the printed circuit board (¶ [0004], ¶ [0038]-[0045] ).
Allowable Subject Matter
Claims 6-7 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 6-7 and 20-21, no other prior art is found to anticipate or render obvious the power semiconductor module arrangement of claims 4 and/or 19, wherein the cavity is partitioned into a plurality of separate chambers by a plurality of dividing walls.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
1 MPEP 2111.01 (I)
2 Bound: to mark or form limits of. https://dictionary.cambridge.org/dictionary/english/bound
3 MPEP 2111.01 (I)
4 https://dictionary.cambridge.org/dictionary/english/and-or
5 See page 7 of the non-final rejection mailed on May 12, 2026.
6 MPEP 2143 (I) (B)
7 See Page 9 of the Non-Final Rejection mailed on May 12, 2026.
8 MPEP 2143 (I) (C)
9 MPEP 2141.03 (I). KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
10 ¶ [0021] : “Although not shown in the drawing, the busbar can be electrically connected to the power terminal 10 for the drain electrode by tightening a bolt, passing through the hole 10e of the busbar mounting portion 10a of the power terminal 10 and the hole of the busbar, into the nut 13a not shown in the drawing”
11 The examiner apologizes for the typographical error in naming the US PG-PUB 2020/0286799 as “Matsumoto” instead of “Masumoto.” This office action has corrected the typographical error in this office action.
12 MPEP 2111.01 (I)
13 Embed: firmly attached within something or under a surface. https://dictionary.cambridge.org/dictionary/english/embedded
14 Claim 19 requires “wherein the cavity is surrounded by a casing.”
15 MPEP 2111.01 (I)
16 Surround: the area or border around something. https://dictionary.cambridge.org/dictionary/english/surround
Prosecution Insights