DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This communication is responsive to application filed on 01/27/2023.
Claims 1-20 are presented for examination.
Claims 9-12 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/01/2026.
Claims 1-8, and 13-20 are present for examination as of 04/01/2026.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 02/06/2023, 10/27/2023 and 05/27/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1, and 13 are objected to because of the following informalities: all the variables should be defined. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5, and 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1 (Does this claim fall within at least one statutory category?):
Claims 1-8 are directed to a method.
Claims 13-20 are directed to a system.
Therefore, claims 1-8, and 13-20 fall into at least one of the four statutory categories.
Step 2A, Prong 1: ((a) identify the specific limitation(s) in the claim that recites an abstract idea: and (b) determine whether the identified limitation(s) falls within at least one of the groups of abstract ideas enumerates in MPEP 2106.04(a)(2)):
Claim 1:
A method of generating waveforms associated with signals of a circuit design in a hardware emulation system, the method comprising:
capturing, using at least a first logic block disposed in the hardware emulation system, values of input signals of the circuit design at each k*d emulation cycle, wherein k and d are integers and wherein k > 0 and d > 0 [mathematical concept];
capturing, using the at least first logic block and at each (k*d+i) emulation cycle, value of each input signal whose value is determined to have changed relative to the signal's value at a previous emulation cycle, wherein 0 < i < d [mathematical concept];
capturing, using at least a second logic block disposed in the hardware emulation system, output values of a plurality of sequential elements of the circuit design at each k*w *d emulation cycle, wherein w is an integer greater than zero; capturing, using the at least second logic block and at each (k*w *d +j*d) emulation cycle, output value of each sequential element that is determined to have changed relative to the sequential element's output value at cycle (k*w *d +(-1)*d), wherein j is an integer and wherein 0 <j< w [mathematical concept]; and
generating, by a processing device, waveforms for the signals of the circuit design based on the captured values of the input signals and captured values of the plurality of sequential elements [insignificant post solution, data output].
Step 2A, Prong 2 (1. Identifying whether there are any additional elements recited in the claim beyond the judicial exception; and 2. Evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application): The claim is directed to the judicial exception.
Claim 1 recites additional element of “hardware emulation system”, “processor”, and “generating”. The additional elements of “hardware emulation system” and “processor” recited at a high level of generality (e.g. a generic computer element for performing a generic computer functions) such that it amounts to no more than mere application of the judicial exception using generic computer component(s). In addition, the additional element of “generating” is insignificant post solution, data output. Accordingly, the additional element(s) of each of this claim does not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Step 2B: (Does the claim recite additional elements that amount to significantly more than the judicial exception? No): As discussed above with respect to the integration of the abstract into a practical application, the additional element of “processor” amount to no more than mere instructions to apply the judicial exception using generic computer component(s). Further, the additional element of “hardware emulation system” is well-known, routine or conventional (Applicant specification, [0003] Prior to manufacturing an IC, the IC netlist is verified using a software simulation and/or a hardware emulation system. A hardware emulation system often includes a multitude of programmable logic devices, such as field programmable gate arrays (FPGAs), to which the various components of a circuit design are mapped) Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In addition, as discussed above with respect to the integration of the abstract into a practical application, the additional elements of “generating” in insignificant post-solutions (i.e. mere data output). At most the additional element is not found to including anything more than mere data output. See MPEP 2106.04(d) referencing MPEP 2106.05(g), example (iii)- presenting offers to potential customers.
As per claim 2, the claim falls into “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion) and/or mathematical concepts”.
As per claim 3, the claim falls into “mental process i.e. concepts performed with pen and paper (including an observation, evaluation judgement, opinion) and/or mathematical concepts”.
As per claim 5, the claim falls into “a generic computer element for performing a generic computer functions”.
As per claim 17, the claim falls into “a generic computer element for performing a generic computer functions”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, and 20 recite the limitation "the computer simulation". There is insufficient antecedent basis for this limitation in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Elmufdi et al (US Publication No. 2021/0240897 A1) discloses [0007] In accordance with one embodiment of the present disclosure, a method of storing data during verification of a circuit design by a hardware emulation system, includes, in part, receiving, once in every N emulation clock cycles, P sets of register data each set including M register bits associated with the circuit design. The method further includes, in part, storing the M register bits of each set in P shift registers during M cycles of a capture clock, and shifting out the stored bits during M*P cycles of the capture clock, where (M+1)*P is less than or equal to N; [0008] In accordance with one embodiment of the present disclosure, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to receive, once in every N emulation clock cycles, P sets of register data each set including M register bits associated with the circuit design. The instructions further cause the processor to store the M register bits of each set in P shift registers during M cycles of a capture clock. The instructions further cause the processor to shift out the stored bits during M*P cycles of the capture clock, where (M+1)*P is less than or equal to N; ; [0009] A circuit, in accordance with one embodiment of the present disclosure, includes, in part P shift registers each configured to receive, once in every N emulation clock cycles, P sets of register data each set comprising M register bits. Each of the P shift registers is further configured to store the M register bits during M cycles of a capture clock, and shift out the stored bits during M*P cycles of the capture clock, where (M+1)*P is less than or equal to N.
Chou et al (US Publication No. 2011/0041105 A1) discloses [0007] A wide range of solutions is available for circuit design verification. For the proof of concept, a software model might be enough. For the development of a high quality hardware, advanced verification techniques and processes are required. Oftentimes, it is convenient for a user to peek into signals during a hardware emulation cycle, for example, when the hardware emulation system detects an error while the testbench continues to run on the host system. In a co-simulation environment, a user can interrupt a hardware emulation cycle and trace a source of the error in a debugging process. For faster signal data exchange between the testbench and the user design, high-bandwidth and low latency data channels are required; [0008] A co-simulation environment of a hardware emulation system provides a user with a capability to interrupt hardware emulation at an opportune time to debug the user's design. A host system typically runs a testbench with software variables, breakpoints, and other variables interacting with the user design under test (DUT). The hardware emulation system runs at or near the speed of the real hardware while the simulation speed is orders of magnitude slower. Because of the vast amount of data to be exchanged between the host system and the hardware emulation system for a given emulation cycle, the communication therebetween is critical to provide a meaningful debugging environment.
Coudert et al (US Patent No. 11, 023, 635 B1) discloses A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory (Abstract).
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Krupnova et al (US Publication No. 2015/0040086 A1) discloses [0011] According to one embodiment, the input trace includes a multitude of input signals captured during the predetermined number of cycles. According to one embodiment, the first prototype and the second prototype are substantially identical to one another; [0028] FIG. 2A depicts a simplified design state capture system 200 to capture the design state depicted in FIG. 1, in accordance with one embodiment of the present invention. Design state capture system 200A includes two prototype platforms P1, P2 respectively 210, 220, input 230, and buffer 240. Input 230 is directly coupled to buffer 240 and prototype platform P2. Input 230 may include a multitude of signals such as external real time peripheral interfaces such as USB, Ethernet, and the like, and feed into the circuit design being verified. Buffer 240 is coupled between input 230 and prototype platform P1. Buffer 240 may be configured to capture all primary input signals between times T0 and T1, called an input trace, via high speed memory. The input trace may include a multitude of signals, which may span for example, millions of cycles between times T0 and T1. The same input appears at prototype platforms P1, P2, except the input to prototype platform P1 is delayed behind the input to prototype platforms P2. Thus, prototype platform P1 is configured to run (T1-T0) cycles behind prototype platform P2. The number of (T1-T0) cycles and the depth of the memory in buffer 240 is predetermined, i.e. adjusted by the designer to properly recreate conditions leading to the verification error of interest.
However, none of the cited prior art references of record fully anticipate or render obvious the independent claims in particular the limitation of: “capturing, using at least a second logic block disposed in the hardware emulation system, output values of a plurality of sequential elements of the circuit design at each k*w *d emulation cycle, wherein w is an integer greater than zero; capturing, using the at least second logic block and at each (k*w *d +j*d) emulation cycle, output value of each sequential element that is determined to have changed relative to the sequential element's output value at cycle (k*w *d + (-1) *d), wherein j is an integer and wherein 0 < j < w” as recited in claims 1, and 13.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIBROM K GEBRESILASSIE whose telephone number is (571)272-8571. The examiner can normally be reached M-F 9:00 AM-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen can be reached at 571 272 3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KIBROM K. GEBRESILASSIE
Primary Examiner
Art Unit 2189
/KIBROM K GEBRESILASSIE/Primary Examiner, Art Unit 2189 06/12/2026
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