DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/31/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 through 10 is objected to because of the following informalities:
Claim 1 recites “wherein the second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die” in lines line 23 through 26. The examiner suggests, “the upper semiconductor die, and are electrically connected”. Appropriate correction is required.
Claims 2 through 10 depend from and incorporate claim 1
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 18 recites “an inter-stack bump between the memory stacks, wherein the inter-stack bump electrically connects the upper common pad of the upper semiconductor die of the upper semiconductor die stack disposed at a lower position of each of the memory stacks to the lower common pad of the lower semiconductor die of the semiconductor die stack disposed at an upper position of each the memory stack.”
However, the specification (US pgpug 2024/0071967 paragraph 58) and the drawings (fig 7c) do not teach an inter stack bump between the memory stacks (300c), but rather between the semiconductor die stacks (100c) (see also independent claim 11).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 through 15 and 18 through 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the upper semiconductor die tack" in line 41. There is insufficient antecedent basis for this limitation in the claim. The examiner suggests “the upper semiconductor die stack”.
Claim 18 recites the limitation "the upper semiconductor die stack" in lines 4 and 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 is unclear and ambiguous because, claim 18 recites “an inter-stack bump between the memory stacks, wherein the inter-stack bump electrically connects the upper common pad of the upper semiconductor die of the upper semiconductor die stack disposed at a lower position of each of the memory stacks to the lower common pad of the lower semiconductor die of the semiconductor die stack disposed at an upper position of each the memory stack.”
However, the specification (US pgpug 2024/0071967 paragraph 58) and the drawings (fig 7c) do not show an inter stack bump between the memory stacks (300c), but rather between the semiconductor die stacks (100c). Therefore, the inter-stack bump will be interpreted as being between semiconductor die stacks, rather than between memory stacks.
Claim 19 recites the limitation "the lower position" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the upper position" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the inter-stack bump" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites “the first and second lower bonding pads of the upper semiconductor die” in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim, the precedent first and second lower bonding pads were located in the lower semiconductor die.
Claim 19 recites the limitation "the lower position" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the upper position" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8, and 9 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen (US 2015/0279888)
Regarding claim 1.
Chen teaches a semiconductor die stack comprising: a lower semiconductor die (fig 9: 112[para 0039]) and an upper semiconductor die (fig 9:212[para 0039] stacked in a face-to-face form (fig 9), wherein the upper semiconductor die (fig 9:212[para 0039]) includes: a first upper bonding pad (fig. 9: 234:224b; [para 0033]) disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die (fig 9:212[para 0039]); and a second upper bonding pad (fig 9:234b[para 0033]) note figure 9 comprises a numerical typo for the purpose of examination pad 234 in figure 9 will be understood to be equivalent to pad 224 in the specification) disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die (fig 9:212[para 0039]), the first edge side and the second edge side of the upper semiconductor die (fig 9:212[para 0039]) being opposite to each other (fig 9), wherein the lower semiconductor die (fig 9:112[para 0039]) includes: a first lower bonding pad (fig 9:124a[para 0034]) disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die (fig 9:112[para 0039]); and a second lower bonding pad (fig 9:124b[para 0025]) disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die (fig 9:212 [para 0039]), the first edge side and the second edge side of the lower semiconductor die (fig 9:112[para 0039]) being opposite to each other, wherein the second upper bonding pad (fig 9:234b[para 0034]) and the first lower bonding pad (fig 9:124a) are vertically aligned and directly bonded to each other, and wherein the second upper bonding pad (fig 9:234b[para 0033]) and the first lower bonding pad are not electrically connected (dummy) to an upper electrical circuit (fig 9:220[para 0029]) in the upper semiconductor die (fig 9:212[para 0039]), and electrically connected (active) to a lower electrical circuit (fig 9:120[para 0026]) in the lower semiconductor die (fig 9:112[para 0039]).
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Regarding claim 2, Chen teaches the semiconductor die stack of claim 1.
Further, Chen teaches the upper semiconductor die (fig 9:212[para 0039]) further comprises an upper common pad region disposed in a central region of a front surface of the upper semiconductor die (fig 9:212[para 0039]), the lower semiconductor die (fig 9:112[para 0039]) further comprises a lower common pad region disposed in a central region of a front surface of the lower semiconductor die (fig 9:112[para 0039]), and an upper common pad (fig 9: 224a[para 0033]) in the upper common pad region and a lower common pad (fig 9:124a[para 0033]) in the lower common pad region are bonded to each other ([para 0035]).
Regarding claim 8, Chen teaches the structure of claim 1.
Further, Chen teaches the upper semiconductor die (fig 7:212:[para 0030]) further comprises an upper bonding insulating layer (fig 7:226[para 0030]) disposed on the front surface of the upper semiconductor die (fig 7:212[para 0030], the upper bonding insulating layer (fig 7:226[para 0030] surrounding side surfaces of the first and second upper bonding pads (fig 7:224a,224b[para 0030]), the lower semiconductor die (fig 3:112[para 0020]) further comprises a lower bonding insulating layer (fig 3:126[para 0022]) disposed on the front surface of the lower semiconductor die (fig 3:112[para 0022]), the lower bonding insulating layer (fig 3:126[para 0022]) surrounding side surfaces of the first and second lower bonding pads (fig 3:126[para 0022]), and the upper bonding insulating layer (fig 8:226[para 0036]) and the lower bonding insulating layer (fig 8:126[para 0036]) are directly bonded with each other (fig 8[para 0036]).
Regarding claim 9, Chen teaches the structure of claim 1.
Chen further teaches the first edge side of the upper semiconductor die (fig 9:212[para 0039]) and the second edge side of the lower semiconductor die (fig 9:112[para 0039]) are vertically aligned with each other, and wherein the second edge side of the upper semiconductor die (fig 9:212[para 0039]) and the first edge side of the lower semiconductor die (fig 9:112[para 0039]) are vertically aligned with each other (see annotated fig 9 above).
Claim(s) 1, 6, and 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Koyanagi (US 2019/0385984).
Regarding claim 1.
Kouanagi teaches a semiconductor die stack comprising (fig 21:CS[para 0128]): a lower semiconductor die (fig 21:CC0[para 0187]) and an upper semiconductor die (fig 21:CC1[para 0187]) stacked in a face-to-face form, wherein the upper semiconductor die (fig 20:cc1[para 0187] includes: a first upper bonding pad (fig 20:64L-3[para 0187]) disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die (fig 20:cc1[para 0187]); and a second upper bonding pad (fig 20:64R-3[para 0187]) disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die (fig 20:cc1[para 0187]), the first edge side and the second edge side of the upper semiconductor die (fig 20:cc1[para 0187]) being opposite to each other, wherein the lower semiconductor die (fig 19:cc0[para 0187]) includes: a first lower bonding pad (fig 19:64L-3[para 0187]) disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die (fig 19:cc0[para 0187]); and a second lower bonding pad (fig 19:64R-3[para 0187]) disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die (fig 19:cc0[para 0187]), the first edge side and the second edge side of the lower semiconductor die (fig 19:cc0[para 0187]) being opposite to each other, wherein the second upper bonding pad (fig 19-21: 64R-3[para 0187]) and the first lower bonding pad (fig 19-21:64L-3[para 0187]) are vertically aligned and directly bonded to each other, and wherein the second upper bonding pad (fig 19-21:64R-3[para 0187]) and the first lower bonding pad (fig 19-21:64L-3[para 0187]) are not electrically connected to an upper electrical circuit in the upper semiconductor die (fig 21:cc1[para 0187]), and electrically connected to a lower electrical circuit (fig 19:67[para 0187]) in the lower semiconductor die (fig 19,21:cc0[para 0187]).
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Regarding claim 6, Koyanagi teaches the semiconductor die stack of claim 1, Koyanagi further teaches the first upper bonding pad (fig 20,21:64L-3[para 0187]) is electrically connected to an upper electrical circuit (fig 20,21:62[para 0187]) in the upper semiconductor die (fig 21:cc1[para 0187]) and is not electrically connected to a lower electrical circuit in the lower semiconductor die (fig 21:cc0[para 0187]) (see annotated figure above).
Regarding claim 7, Koyanagi teaches the semiconductor die stack of claim 1, Koyanagi further teaches the first upper bonding pad (fig 20:64L-3[para 0187]) is electrically connected to an upper electrical circuit (fig 20,21:67[para 0187]) in the upper semiconductor die (fig 21:cc1[para 0187]) and is not electrically connected to a lower electrical circuit in the lower semiconductor die (fig 21:cc0[para 0187]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Chen (US 2015/0279888) as applied to claim 2 and further in view of Bartley (US 2012/0038057)
Regarding claim 3, Chen teaches the structure of claim 2.
Further, Chen teaches the upper semiconductor die (fig 9:212[para 0039]) further comprises an upper top metal pattern (fig 9:238[para 0031]), […]and wherein the lower semiconductor die (fig 9:112[para 0039]) further comprises a lower top metal pattern (fig 3,9:132[para 0023]), […]
Chen does not teach a back side pad or through via.
Bartley teaches
an upper common back-side pad (fig 4:22[para 0048]), and an upper common through-via (fig 4:48[para 0048]) disposed to be vertically aligned with the upper common pad (fig 4:22[para 0048]),a lower common back-side pad (fig 4:22[para 0048]), and a lower common through-via (fig 4:48[para 0048]) disposed to be vertically aligned with the lower common pad (fig 4:22[para 0048]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide backside pads and through vias in order to allow stacking of additional dies thereby increase the total die capacity.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Chen (US 2015/0279888) as applied to claim 2 and further in view of Lee (US 2014/0175439)
Regarding claim 4, Chen teaches the structure of claim 2.
Chen does not teach the common pad is a test pad
Lee teaches the upper common pad (fig 1,2:120[para 0010,0011]) and the lower common pad are test pads (fig 1,2:120[para 0010,0011]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the common pads to be test pads in order to permit the performance of normal test operations (Lee [para 0008])
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Chen (US 2015/0279888) as applied to claim 1 and further in view of Bartley (US 2012/0038057)
Regarding claim 5, Chen teaches the structure of claim 2.
Chen teaches the upper semiconductor die (fig 9:212[para 0039]) further includes: a first upper top metal pattern (fig 9:238[para 0031]), […]; and a second upper top metal pattern (fig 3,9:132[para 0032]) […]
Chen does not teach backside pads and through vias.
Bartley teaches
a first upper back-side pad (fig 4:22[para 0048]), and a first upper through-via (fig 4:48[para 0048] to be vertically aligned with the first bonding pad (fig 4:22[para 0048]) in the first upper bonding pad regiona second upper back-side pad (fig 4:22[para 0048]), and a second upper through-via (fig 4:[para 0048]) to be vertically aligned with the second bonding pad (fig 4:22[para 0048]) in the second upper bonding pad region.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide backside pads and through vias in order to allow stacking of additional dies thereby increase the total die capacity.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Chen (US 2015/0279888) as applied to claim 1 and further in view of Kim (US 2018/0006006)
Regarding claim 10, Chen teaches the structure of claim 1.
Chen does not teach test pads.
Kim teaches the first and second upper bonding pads (fig 8,9:[para 0052,0053]) and the first and second lower bonding pads are test pads (fig 8,9[para 0052,0053]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pads to be testing pads in order to evaluate the normal or defective operation of the die (Kim [para 0053])
Claim(s) 16, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koyanagi (US 2019/0385984) in view of Kim (US 2020/0111764).
Regarding claim 16.
Koyanagi teaches a high bandwidth memory (fig 21[para 0183]) […]
a semiconductor die stack (fig 21:CS[para 0128]) […], wherein the semiconductor die stack (fig 21:CS[para 0128]) includes an upper semiconductor die (fig 21:CC1[para 0206])) and a lower semiconductor die (fig 21:CC0[para 0206]) bonded in a face-to-face form (fig 21[para 0171]), wherein the upper semiconductor die (fig 20:cc1[para 0187]) includes: a first upper bonding pad (fig 20:64L-3[para 0187]) disposed in a first upper bonding pad region adjacent to a first edge side of the upper semiconductor die (fig 21:CC1[para 0187]); and a second upper bonding pad (fig 20:[64R-3[para 0187]) disposed in a second upper bonding pad region adjacent to a second edge side of the upper semiconductor die (fig 20:cc1[para 0187]), wherein the lower semiconductor die (fig 19:cc0[para 0187]) includes: a first lower bonding pad (fig 19:64l-3[para 0187]) disposed in a first lower bonding pad region adjacent to a first edge side of the lower semiconductor die (fig 19:cc0[para 0187]); and a second lower bonding pad (fig 19:64R-3[para 0187]) disposed in a second lower bonding pad region adjacent to a second edge side of the lower semiconductor die (fig 19:cc0[para 0187]), wherein: the first upper bonding pad (fig 21:64L-3[para 0187]) and the second lower bonding pad (fig 21:64R-3[para 01987]) are vertically aligned to be directly bonded with each other, the second upper bonding pad(fig 21:64R-3[para 0187]) and the first lower bonding pad (fig 21:64L-3[para 0187]) are vertically aligned to be directly bonded with each other, the first upper bonding pad (fig 21:64L-3[para 0187]) and the second lower bonding pad (fig 64R-3[para 0187]) are electrically connected to an upper electrical circuit (fig 20:67[para 0202]) in the upper semiconductor die (fig 20:cc1[para 0202]), and are not electrically connected to a lower electrical circuit in the lower semiconductor die (fig 21), and the second upper bonding pad (fig 21:64R-3[para 0187]) and the first lower bonding pad (fig 20:64L-3[para 0187]) are not electrically connected to the upper electrical circuit in the upper semiconductor die (fig 20:cc1[para 0187]) and are electrically connected to the lower electrical circuit (fig 21:67[para 0187]) in the lower semiconductor die (fig 21:cc0[para 0187]).
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Koyanagi does not teach an interposer and processing unit.
Kim teaches a high bandwidth memory (fig 2:100[para 0051]) comprising: an interposer fig 2:20[para 0051]); and a plurality of memory stacks (fig 2:60a,60b[para 0056]) and a processing unit (fig 2:30[para 0056]) mounted on the interposer (fig 2:100[para 0051]), wherein each of the plurality of memory stacks (fig 2:60a,60b[para 0056]) includes: a base die (fig 2:50a,50b:[para 0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a processing unit and interposed for the memory structure in order to enable the high speed transfer of data from memory cell to processing cells and back to memory to thereby increase processing speed.
Regarding claim 17, Koyanagi in view of Kim teaches the high bandwidth memory of claim 16,
Koyanagi further teaches: the upper semiconductor die (fig 20:cc1[para 0187]) further includes an upper common pad (fig 20:64R-1[para 0187]) in an upper common pad region, the lower semiconductor die (fig 19:cc0[para 0187]) further includes a lower common pad (fig 19:64L-1[para 0187]) in a lower common pad region, and the upper common pad (fig 20:64R-1[para 0187]) and the lower common pad (fig 19:64L-1[para 0187]) are directly bonded with each other (fig 21[para 0206]).
Regarding claim 18, Koyanagi in view of Kim teaches the high bandwidth memory of claim 17,
Koyanagi further teaches an inter-stack bump (fig 19-21:63R-1,63L-1[para 0187]) between the [semiconductor die] stacks, wherein the inter-stack bump (fig 19-21:63r-1[para 0207]) electrically connects (fig 19-20:69[para 0189])) the upper common pad (fig 20:64L-1[para 0187]) of the upper semiconductor die (CC1) of the upper semiconductor die stack disposed at a lower position of each of the memory stacks to the lower common pad (fig19:64R-1) of the lower semiconductor die (CC2) of the semiconductor die stack disposed at an upper position of each the memory stack (fig 19[para 0185]).
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Allowable Subject Matter
Claims 11 through 15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 19 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art does not teach the upper common pad of a lower semiconductor die stack disposed at a lower position of the semiconductor die stacks and the lower common pad of an upper semiconductor die stack disposed at an upper position of the semiconductor die stacks are electrically connected with each other through an inter-stack bump, and the first upper bonding pad of the lower semiconductor die stack disposed at the lower position of the semiconductor die stacks and the second lower bonding pad of the upper semiconductor die tack disposed at the upper position of the semiconductor die stacks are not electrically connected with each other in combination with the other elements of the claim..
Regarding claim 19, the prior art does not teach the first and second upper bonding pads of the upper semiconductor die of the semiconductor die stack disposed at the lower position of each of the memory stacks are not electrically connected with the first and second lower bonding pads of the lower semiconductor die of the semiconductor die stack disposed at the upper position of each the memory stack in combination with other elements of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 14, 2026