Prosecution Insights
Last updated: July 17, 2026
Application No. 18/103,629

SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §103§112
Filed
Jan 31, 2023
Priority
Feb 04, 2022 — RE 10-2022-0015072
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
727 granted / 1071 resolved
At TC average
Strong +30% interview lift
Without
With
+29.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
80 currently pending
Career history
1176
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
76.9%
+36.9% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1071 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to amendment filed 4/8/2026. Claims 1-20 are pending. Claims 1, 11, 15-16, and 20 have been amended. Claims 21-25 have been canceled. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 11-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 11 reciting “an insulating spacer … having a round upper outer fillet joining a sidewall of the insulating spacer and a top surface of the insulating spacer” renders the claim indefinite. Applicant describes the insulating spacer 120 in FIG. 2C as having “a round sidewall 120R” to which the claimed “round upper outer fillet” is understood to refer to. The rounded sidewall 120R of the “fillet” connects a vertical sidewall of the insulating spacer 20 to a vertical sidewall of the semiconductor layer 140. However, it is unclear what would constitute “a top surface” of the insulating spacer. The entirety of the fillet is rounded which joins a vertical sidewall of the insulating spacer 20. However, there is no separate insulating spacer “top surface” to which the “fillet” joins. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 16-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2009/0101926 A1 in view of Kao et al. US 2010/0193811 A1 (Kao). PNG media_image1.png 590 486 media_image1.png Greyscale In re claim 1, Lee discloses (e.g. FIGs. 7 & 9) a semiconductor light-emitting device, comprising: a first conductivity-type semiconductor layer 120 including a lower portion and an upper portion 122 on the lower portion, the upper portion including rods 122 spaced apart from each other; active layers 130 on upper surfaces of the rods 122, respectively; second conductivity-type semiconductor layers 140 on upper surfaces of the active layers 130, respectively; an insulating spacer 150 extending conformally between the rods 122, the insulating spacer 150 surrounding all sidewalls of each of the active layers 130, and covering portions of sidewalls of each of the second conductivity-type semiconductor layers 140; a first electrode layer 172 in contact with the lower portion of the first conductivity- type semiconductor layer 120; and a second electrode layer 160 filling an inner space above the insulating spacer and in contact with the second conductivity-type semiconductor layers 140, wherein the rods 122 are regularly distributed under the entirety of the second electrode layer 160 with a constant spacing between adjacent rods 122 (see FIGs. 3, 11, & 13, grooves 152 with a predetermined interval/period or irregular interval, ¶ 49,64,66). Lee discloses the insulating spacer 150 fills up the grooves 152. However, Lee does not explicitly disclose the second electrode layer is filing an inner space of the insulating spacer 150. PNG media_image2.png 418 730 media_image2.png Greyscale However, Kao discloses (e.g. FIGs. 4A-4B) a semiconductor light-emitting device, comprising: a first conductivity-type semiconductor layer 74 including a lower portion and an upper portion on the lower portion, the upper portion including rods (protruding pillars) spaced apart from each other; active layers 76 on upper surfaces of the rods, respectively; second conductivity-type semiconductor layers 78 on upper surfaces of the active layers, respectively; an insulating spacer 69 extending conformally between the rods, the insulating spacer 69 surrounding all sidewalls of each of the active layers 76, and covering portions of sidewalls of each of the second conductivity-type semiconductor layers 78; a first electrode layer 72 in contact with the lower portion of the first conductivity- type semiconductor layer; and a second electrode layer 68 filling an inner space of the insulating spacer 69 and in contact with the second conductivity-type semiconductor layers 78. Kao discloses the insulating layer 32 can fills the gaps between the pillars as shown in FIGs. 2A-2D with the second electrode layer 34 sitting on top. Kao further discloses the gaps between pillars can be conformally coated with the insulating layer 69 forming an inner space within the insulating spacer (see FIG. 5C) that is further filled with the second electrode layer 68 as shown in FIGs. 4A-4B. Kao teaches the gaps may be filled with the insulating layer 32 or conformally coated with the insulating spacer 69 to allow the second electrode to fills in the inner space of the insulating spacer to ensure uniform layer coating and obtain a light-emitting device with improved light extraction efficiency (¶ 14). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Lee’s light-emitting device by modifying the filled insulating spacer 150 in the groove 152 by forming a conformal insulating coating followed by filling the inner space of the insulating spacer with the second electrode layer as taught by Kao to obtain uniformly coated layers and a light-emitting device with high light extraction efficiency. In re claim 2, Lee discloses (e.g. FIGs. 7 & 9) wherein a level of an uppermost surface of the insulating spacer 150 is higher in a vertical direction than a level of an uppermost surface of each of the active layers 130. Kao discloses (e.g. FIGs. 4A-4B) wherein a level of an uppermost surface of the insulating spacer 69 is higher in a vertical direction than a level of an uppermost surface of each of the active layers 76. In re claim 3, Lee discloses (e.g. FIGs. 7 & 9) wherein the lower portion of the first conductivity-type semiconductor layer 120 has a flat plate shape in contact with lower surfaces of the rods 122. Kao discloses (e.g. FIGs. 4A-4B) wherein the lower portion of the first conductivity-type semiconductor layer 74 has a flat plate shape in contact with lower surfaces of the rods. In re claim 4, Lee discloses (e.g. FIGs. 7 & 9) wherein the second electrode layer 160 is in contact with an upper surface of each of the second conductivity-type semiconductor layers 140 and a portion of a side surface of each of the second conductivity-type semiconductor layers 140 (upper ends of 140 exposed). Kao discloses (e.g. FIGs. 4A-4B) wherein the second electrode layer 68 is in contact with an upper surface of each of the second conductivity-type semiconductor layers 78 and a portion of a side surface of each of the second conductivity-type semiconductor layers 78 (electrode 68 is in thermal contact with side surface of 78 and is indirectly electrically contacting side surface of 78). Furthermore, Kao discloses side surface of 78 are not necessary completely coated with insulating layer 69 (¶ 45). Therefore, portion of side surfaces of 78 that is exposed from insulating layer 69 would be contacting the subsequently deposited electrode layer 68. In re claim 5, Lee discloses (e.g. FIGs. 7 & 9) wherein, when viewed from a side cross-section, the second electrode layer 160 has a concave-convex shape. Kao discloses (e.g. FIGs. 4A-4B) wherein, when viewed from a side cross-section, the second electrode layer 68 has a concave-convex shape. In re claim 6, Lee discloses (e.g. FIG. 7 & 9) wherein the first conductivity-type semiconductor layer 120 includes n-type gallium nitride (¶ 25), the second conductivity-type semiconductor layer 140 includes p-type gallium nitride (¶ 28), and each of the active layers 130 includes a quantum well layer and a quantum barrier layer (¶ 40). In re claim 16, Lee discloses (e.g. FIGs. 7 & 9) a semiconductor light-emitting device, comprising: a sapphire substrate 110 (Al2O3, ¶ 23); an undoped gallium nitride layer 115 (or buffer above 115 not shown, ¶ 24) on the sapphire substrate; an n-type gallium nitride layer 120 (¶ 25) including rods 122 (FIG. 4) spaced apart from each other, the rods 122 being in an upper portion of the n-type gallium nitride layer 120; active layers 130 on upper surfaces of the rods; p-type gallium nitride layers 140 (¶ 28) on upper surfaces of the active layers 130, respectively; an insulating spacer 150 extending conformally between the rods 122, the insulating spacer 150 surrounding all sidewalls of each of the active layers 130, and covering portions of sidewalls of each of the p-type gallium nitride layers 140; an n-electrode layer 172 in contact with a lower portion of the n-type gallium nitride layer 120; and a p-electrode layer 160 filling an inner space above the insulating spacer and in contact with the p-type gallium nitride layers 140, wherein the rods 122 are regularly distributed under the entirety of the p-electrode layer 160 with a constant spacing between adjacent rods 122 (see FIGs. 3, 11, & 13, grooves 152 with a predetermined interval/period or irregular interval, ¶ 49,64,66). Lee discloses the insulating spacer 150 fills up the grooves 152. However, Lee does not explicitly disclose the second electrode layer is filing an inner space of the insulating spacer 150. Kao discloses (e.g. FIGs. 4A-4B) a semiconductor light-emitting device, comprising: a substrate 60; a first conductivity-type semiconductor nitride layer 74 including rods (protruding pillars) spaced apart from each other, the rods being in an upper portion of the first conductivity-type semiconductor nitride layer 74; active layers 76 on upper surfaces of the rods; a second conductivity-type semiconductor nitride layers 78 on upper surfaces of the active layers 76, respectively; an insulating spacer 69 extending conformally between the rods (protruding pillars of 64), the insulating spacer 69 surrounding all sidewalls of each of the active layers 76, and covering portions of sidewalls of each of the second conductivity-type semiconductor nitride layers 78; a first electrode layer 72 in contact with a lower portion of the first conductivity-type semiconductor nitride layer; and a second electrode layer 68 filling an inner space of the insulating spacer 69 and in contact with the second conductivity-type semiconductor nitride layers 78. Kao discloses the insulating layer 32 can fills the gaps between the pillars as shown in FIGs. 2A-2D with the second electrode layer 34 sitting on top. Kao further discloses the gaps between pillars can be conformally coated with the insulating layer 69 forming an inner space within the insulating spacer (see FIG. 5C) that is further filled with the second electrode layer 68 as shown in FIGs. 4A-4B. Kao teaches the gaps may be filled with the insulating layer 32 or conformally coated with the insulating spacer 69 to allow the second electrode to fills in the inner space of the insulating spacer to ensure uniform layer coating and obtain a light-emitting device with improved light extraction efficiency (¶ 14). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Lee’s light-emitting device by modifying the filled insulating spacer 150 in the groove 152 by forming a conformal insulating coating followed by filling the inner space of the insulating spacer with the second electrode layer as taught by Kao to obtain uniformly coated layers and a light-emitting device with high light extraction efficiency. In re claim 17, Kao discloses (e.g. FIGs. 7 & 9) wherein: a vertical level of an uppermost surface of the insulating spacer 150 is higher than a vertical level of each of the upper surfaces of the rods 122, the vertical level of the uppermost surface of the insulating spacer 150 is higher than a vertical level of each of the upper surfaces of the active layers 130, and the vertical level of the uppermost surface of the insulating spacer 150 is lower than a vertical level of an upper surface of each of the second conductivity-type semiconductor nitride layers 140 (upper portion of 140 exposed from insulating spacer 150). Kao discloses (e.g. FIGs. 4A-4B) wherein: a vertical level of an uppermost surface of the insulating spacer 69 is higher than a vertical level of each of the upper surfaces of the rods (protruding pillars of layer 74), the vertical level of the uppermost surface of the insulating spacer 69 is higher than a vertical level of each of the upper surfaces of the active layers 76, and the vertical level of the uppermost surface of the insulating spacer 69 is lower than a vertical level of an upper surface of each of the second conductivity-type semiconductor nitride layers 78 (side surface of 78 are not necessary completely coated with insulating layer 69, ¶ 45; therefore, portion of side surfaces of 78 that is exposed from insulating layer 69 with the upper most surface of insulating layer 69 lower than the upper surface of 78). In re claim 18, Lee discloses (e.g. FIGs. 7 & 9) wherein: each of the active layers 130 has a structure in which a quantum well layer and a quantum barrier layer are alternately disposed (InGaN/GaN, ¶ 40), the quantum well layer includes an indium gallium nitride layer (InGaN), and the quantum barrier layer includes a gallium nitride layer (GaN) or an indium aluminum gallium nitride layer. In re claim 20, Lee discloses (FIGs. 5, 11 & 13) wherein, when viewed from a side cross-section (see cross-sections shown in FIGs. 5, 11 & 13) that is perpendicular to a vertical direction (no specific “vertical direction” claimed that would distinguish over a longitudinal direction as shown in FIGs. 5, 11 & 13 to which the cross-sectional views are perpendicular to), an upper outer wall of the insulating spacers 150 is a rounded sidewall (see FIGs. 5, 11 & 13 showing rounded sidewall of 150,150A,150C due to the wave or circular patterns), and each of the active layers 130 and each of the p-type gallium nitride layers 140 has substantially a same area. Claims 7-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Kao as applied to claims 1 and 16 above, and further in view of Nagawa et al. US 2020/0274330 A1 (Nagawa). In re claim 7, Lee discloses (e.g. FIG. 13) the rods 122 (having same shape as 140) are cylindrical shape with circular cross-sections. Lee further discloses the arrangement of pillars rods increase light emitting area (¶ 31). Lee does not explicitly disclose the dimensions of the rods. PNG media_image3.png 710 820 media_image3.png Greyscale Nagawa discloses a semiconductor light-emitting device (FIG. 8), comprising light-emitting nanorods 30, wherein a distance between the rods is 500 nm or larger (¶ 80), and each of the rods has a cylindrical, a quadrangular, or a hexagonal rod shape (¶ 78). Claimed distance range of about 100 nm to about 2 µm is obvious over Nagawa teaching a range of 500 nm or larger. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Lee’s rods 122 to have the claimed dimensions as taught by Nagawa as suitable for forming light-emitting structure with increased light emitting area and improved light extraction efficiency (Nagawa, ¶ 34). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kao’s pillars 64 to have the claimed dimensions as taught by Nagawa as suitable for improving light extraction. In re claim 8, Nagawa discloses (e.g. FIG. 8) wherein a height of each of the rods 30 is about 100 nm to about 10 µm (0.1 µm to 5 µm, ¶ 78), and a diameter of each of the upper surfaces of the rods is 10 nm to 500 nm (¶ 78). The claimed diameter of about 100 nm to about 10 µm is obvious over Nagawa teaching nanorods having a diameter of 10 nm to 500 nm. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 9, Lee discloses the claimed invention including insulating spacer 150 including silicon oxide, silicon nitride, or aluminum oxide (¶ 32). Lee does not explicitly disclose the thickness of the insulating spacer 150. Kao discloses the claimed invention including insulating spacer 69 conformally surrounding sidewalls of the rods 64. Kao does not explicitly disclose the thickness and material of the insulating spacer 69. Nagawa discloses a semiconductor light-emitting device (e.g. FIG. 8) comprising light-emitting nanorods 30 (¶ 78) surrounded by insulating spacer 70 extending conformally around the nanorods 30, wherein the insulating spacer 70 has a thickness of 10 nm to 100 nm (¶ 142), the insulating spacer 70 including silicon oxide, silicon nitride, or aluminum oxide (silicon oxide, ¶ 142). The claimed thickness of about 50 nm to about 1 µm is obvious over Nagawa teaching insulating film thickness of 10 nm to 100 nm. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the conformal insulating spacer taught by the combination of Lee and Kao to have at thickness of about 50 nm to about 1 µm as taught by Nagawa. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). In re claim 19, Lee discloses (e.g. FIG. 13) the rods 122 (having same shape as 140) are cylindrical shape with circular cross-sections. Lee further discloses the arrangement of pillars rods increase light emitting area (¶ 31). Kao teaches the conformal insulating spacer 69. Lee does not explicitly disclose the dimensions of the rods. Kao does not explicitly disclose the thickness of the insulating spacer. Nagawa discloses a semiconductor light-emitting device (FIG. 8), comprising light-emitting nanorods 30 (¶ 78) surrounded by insulating spacer 70 extending conformally around the nanorods 30, wherein a height of each of the rods 30 is about 100 nm to about 10 µm (0.1 µm to 5 µm, ¶ 78), a diameter of each of the upper surfaces of the rods 30 is 10 nm to 500 nm (¶ 78), a distance between the rods is 500 nm or larger (¶ 80), and a thickness of the insulating spacer 70 is 10 nm to 100 nm (¶ 142). The claimed diameter of about 100 nm to about 10 µm is obvious over Nagawa teaching nanorods having a diameter of 10 nm to 500 nm; claimed distance range of about 100 nm to about 2 µm is obvious over Nagawa teaching a range of 500 nm or larger; claimed thickness of about 50 nm to about 1 µm is obvious over Nagawa teaching insulating film thickness of 10 nm to 100 nm. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Lee’s rod 122 and Kaos’ conformal insulating spacer 69 to have the claimed dimensions as taught by Nagawa as suitable for forming light-emitting structure with increased light emitting area and improved light extraction efficiency (Nagawa, ¶ 34). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee and Kao as applied to claim 1 above, and further in view of Mi et al. US 2016/0027961 A1 (Mi). In re claim 10, Lee discloses (see FIGs. 7 & 9) the claimed invention including the insulating spacer 150 along a sidewall of each of the second conductivity-type semiconductor layers 140. Lee further discloses (see FIG. 15) the insulating spacer 155 completely covering the sidewall of each of the second conductivity-type semiconductor layers 140. Kao discloses the insulating spacer 69 completely contacts and covers sidewalls of each of the second conductivity-type semiconductor layers 78 (see FIGs. 4A-4B). Lee and Kao do not explicitly disclose a length of in a vertical direction of a sidewall of each of the second conductivity-type semiconductor layers contacting the insulating spacer is at least 50 nm. However, Mi discloses (e.g. FIG. 9) light-emitting nanowires comprising a first conductivity-type semiconductor layer (n-GaN, n-AlGaN), active layers (i-AlGaN), and second conductivity-type semiconductor layers (p-GaN, p-AlGaN), wherein p-AlGaN has a length of 100 nm and the p-GaN has a length of 30 nm (¶ 79). Thus, the second conductivity-type semiconductor layers each has a total length of 130 nm. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Lee or Kao’s second conductivity-type semiconductor layers to have a total length of, e.g. 130 nm as taught by Mi as suitable for forming light-emitting nanowire structures. As such, the insulating spacer covering the entire length of 130 nm of the vertical sidewalls of the second conductivity-type semiconductor layer which teaches the claimed range of “at least 50 nm”. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
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Prosecution Timeline

Jan 31, 2023
Application Filed
Dec 03, 2025
Non-Final Rejection (signed) — §103, §112
Jan 08, 2026
Non-Final Rejection mailed — §103, §112
Feb 25, 2026
Applicant Interview (Telephonic)
Feb 25, 2026
Examiner Interview Summary
Apr 08, 2026
Response Filed
Jun 08, 2026
Examiner Interview (Telephonic)
Jun 11, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.6%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1071 resolved cases by this examiner. Grant probability derived from career allowance rate.

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