DETAILED ACTION
This action is responsive to the following: the amendment to claims and applicant remarks made in amendment filed on March 3, 2026.
Claims 1-3, 5-8, 10-11, 21-23, and 25-32 are pending. Claims 4, 9, 12-20, and 24 were cancelled by applicant. Claims 1, 21, and 27 are independent. Claims 30-32 are new.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on March 3, 2026 has been entered. Claims 1-3, 5-8, 10-11, 21-23, and 25-32 remain pending. Claims 30-32 are new. Claims 4, 9, 12-20, and 24 were cancelled by applicant. Applicant’s amendment to the specification and claims has overcome the objections and rejections under USC 112(a) previously set forth in the final Office Action mailed on November 26, 2026.
Claim Interpretation
Independent Claims 1, 21, and 27 have been amended to include the limitation “the middle-end interconnect structure being electrically connected to the common bit line through a back-end interconnect structure.” In this case “back-end” is understood to mean that the interconnect structure was formed as part of back-end of line process when fabricating the device and does not describe anything unique structurally about the interconnect structure only when it was fabricated relative to other structures. As the claims are directed to structure and not process, the relevance of designating structures front-end/middle-end/back-end within the context of the present set of claims are therefore understood to only exist as naming conventions and not structural limitations. See MPEP 2113.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, 21-22, and 27-28 is/are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee (US 20210159231).
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Regarding independent Claim 1, Lee teaches A semiconductor device, comprising:
a memory cell including a first transistor, a second transistor, and a third transistor (Fig. 1B: T3, T2, T1);
wherein the first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively (FIG 1B: T3, T2, RWL, WWL);
wherein the first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line (FIG 1B: T3, T2, BL); and
wherein the third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively (FIG 1B: T1, T2, T3), wherein the first transistor (Fig. 2B: T3) and second transistor (Fig. 2B: T2) are configured to share a common bit line (Fig. 2B: BL) for both read and write operations through a single middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect), the middle-end interconnect structure directly connecting the one of the pair of first source/drain terminals and the one of the pair of second source/drain terminals (Fig. 6B: SD3, SD5) and the middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect) being electrically connected to the common bit line through a back-end interconnect structure (Examiner’s Markup Lee Fig. 6A: back-end interconnect); and
wherein the common bit line remains at ground voltage during the first transistor being turned on and then off to write data with a logic 0.
The statement that the common bit line remains at ground while writing data recites a process for using the memory cell but does not distinguish the structure of the semiconductor device claimed from the prior art device. See MPEP 2114(II). This limitation does not present any different structure or present any further limitations on the “memory device” that define it as something different from what is shown in Lee’s memory device.
Furthermore, the designation of interconnect structures as being “middle-end” or “back-end” are not terms that structurally distinguish interconnect structures because the terms “middle-end” and “back-end” are implications of the method of manufacturing, or when the interconnects are formed during manufacturing as opposed to actual structural distinctions. In this regard, the adjectives “middle-end” and “back-end,” as used to modify interconnects, imply process steps, making this claim a product-by-process claim. The “middle-end” and “back-end” do not imply structure. MPEP 2113.
Regarding Claim 2, Lee teaches a semiconductor device, wherein the first to third transistors each have a p-type transistor (paragraph 0040).
Regarding Claim 7, Lee teaches a semiconductor device, wherein the first transistor has an n-type transistor, and the second transistor and the third transistor each have a p-type transistor (paragraph 0040 “Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be NMOS transistors; however, example embodiments are not limited thereto, and at least one of the first transistor T1, the second transistor T3, and the third transistor T3 may be PMOS transistors.”).
Regarding Independent Claim 21, Lee teaches a semiconductor device, comprising:
a memory cell including a first transistor, a second transistor, and a third transistor (Fig. 1B: T3, T2, T1);
wherein the first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively (FIG 1B: T3, T2, RWL, WWL);
wherein the first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line (FIG 1B: T3, T2, BL);
wherein the third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals (FIG 1B: T1, T3); and
wherein the first to third transistors each have a p-type transistor (Paragraph 0040).
wherein the first to third transistors (FIG 1B: T1, T2, T3) each have a p-type transistor (paragraph 0040 “Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be NMOS transistors; however, example embodiments are not limited thereto, and at least one of the first transistor T1, the second transistor T3, and the third transistor T3 may be PMOS transistors.”), wherein the first transistor (Fig. 2B: T3) and second transistor (Fig. 2B: T2) are configured to share the common bit line for both read and write operations through a single middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect), the middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect) physically and electrically directly connecting the one of the pair of first source/drain terminals [[and]]to the one of the pair of second source/drain terminals (Fig. 6B: SD3, SD5) to the common bit line, and the middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect) being electrically connected to the common bit line through a back-end interconnect structure (Examiner’s Markup Lee Fig. 6A: back-end interconnect); and
wherein the common bit line remains at ground voltage during the first transistor being turned on and then off to write data with a logic 0.
The statement that the common bit line remains at ground while writing data recites a process for using the memory cell but does not distinguish the structure of the semiconductor device claimed from the prior art device. See MPEP 2114(II). This limitation does not present any different structure or present any further limitations on the “memory device” that define it as something different from what is shown in Lee’s memory device.
Furthermore, the designation of interconnect structures as being “middle-end” or “back-end” are not terms that structurally distinguish interconnect structures because the terms “middle-end” and “back-end” are implications of the method of manufacturing, or when the interconnects are formed during manufacturing as opposed to actual structural distinctions. In this regard, the adjectives “middle-end” and “back-end,” as used to modify interconnects, imply process steps, making this claim a product-by-process claim. The “middle-end” and “back-end” do not imply structure. MPEP 2113.
Regarding Claim 22, Lee teaches a semiconductor device, wherein a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively (FIG 1B: T1, T2).
Regarding Independent Claim 27, Lee teaches a semiconductor device, comprising:
a memory cell including a first transistor, a second transistor, and a third transistor (FIG 1B: T1, T2, T3);
wherein the first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively (FIG 1B: T3, T2, RWL, WWL);
wherein the first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line (FIG 1B: T1, T2, BL);
wherein the third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals (FIG 1B: T1, T3); and
wherein the first transistor has an n-type transistor, and the second transistor and the third transistor each have a p-type transistor (Paragraph 0040).
wherein the first to third transistors (FIG 1B: T1, T2, T3) each have a p-type transistor (paragraph 0040 “Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be NMOS transistors; however, example embodiments are not limited thereto, and at least one of the first transistor T1, the second transistor T3, and the third transistor T3 may be PMOS transistors.”), wherein the first transistor (Fig. 2B: T3) and second transistor (Fig. 2B: T2) are configured to share the common bit line for both read and write operations through a single middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect), the middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect) physically and electrically directly connecting the one of the pair of first source/drain terminals [[and]]to the one of the pair of second source/drain terminals (Fig. 6B: SD3, SD5) to the common bit line, and the middle-end interconnect structure (Examiner’s Markup Lee Fig. 6A: middle-end interconnect) being electrically connected to the common bit line through a back-end interconnect structure (Examiner’s Markup Lee Fig. 6A: back-end interconnect); and
wherein the common bit line remains at ground voltage during the first transistor being turned on and then off to write data with a logic 0.
The statement that the common bit line remains at ground while writing data recites a process for using the memory cell but does not distinguish the structure of the semiconductor device claimed from the prior art device. See MPEP 2114(II). This limitation does not present any different structure or present any further limitations on the “memory device” that define it as something different from what is shown in Lee’s memory device.
Furthermore, the designation of interconnect structures as being “middle-end” or “back-end” are not terms that structurally distinguish interconnect structures because the terms “middle-end” and “back-end” are implications of the method of manufacturing, or when the interconnects are formed during manufacturing as opposed to actual structural distinctions. In this regard, the adjectives “middle-end” and “back-end,” as used to modify interconnects, imply process steps, making this claim a product-by-process claim. The “middle-end” and “back-end” do not imply structure. MPEP 2113.
Regarding Claim 28, Lee teaches a semiconductor device, wherein a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively (FIG 1B: T2, T1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6, 8-11, 23-26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee (US 20210159231) and Kitagawa (US 20080025113 A1).
Regarding Claim 3, Lee teaches the limitations of claim 2. Lee teaches a common read and write bit line (Fig 1B: BL).
Lee, however, does not teach the specifically recited method of writing.
Kitagawa teaches a related 3T memory cell wherein, with the second transistor (Fig. 1: ST) being turned off through the second word line (Fig. 6B: RWL), the first transistor (Fig. 1: WT) is configured to be first turned on and then off through the first word line (Fig. 6C: WWL, T4) so as to write data to the third transistor (Fig. 1: AT).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have apply the teachings of Kitagawa to the teachings of Lee to provide a three transistor memory cell with the method of writing where the second transistor is turned off through the second word line and the first transistor is turned on through the first word line so as to write data from a common bit line to the gate of the third transistor, so the data state of the memory cell can be changed (or i.e., such that data can be stored to the memory).
Regarding Claim 5, Lee and Kitagawa, as combined, teach the limitations of claim 3.
Kitagawa further teaches a semiconductor device, wherein the write bit line first transitions from ground voltage to the supply voltage (Fig 6G: WBL, T3, T4) during the first transistor (Fig 1: WT) being turned on (Fig 6C: WWL, T4) and the to write the data with a logic 1.
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Regarding Claim 6, Lee teaches the limitations of claim 2.
Lee, however, does not teach the specifically recited method of reading.
Kitagawa teaches a related 3T memory cell, wherein, with the first transistor being turned off through the first word line, the second transistor is configured to be turned on through the second word line to read data from the third transistor (Fig. 3B and Fig. 3C).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kitagawa to the teachings of Lee to provide a three transistor memory cell with a known method of reading so the memory cell’s data can be retrieved.
Regarding claim 8, Lee teaches the limitations of claim 7.
Lee teaches a common read and write bit line (Fig 1B: BL).
Lee, however, does not teach the specifically recited method of writing.
Kitagawa teaches a related 3T memory cell, wherein, with the second transistor (fig 1: ST) being turned off through the second word line (Fig 6B: RWL), the first transistor (fig 1: WT) is configured to be first turned on and then off through the first word line (FIG 6C: WWL, T4) so as to write data to the third transistor (Fig 1: AT). But Kitagawa fails to teach a common bit line.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kitagawa to the teachings of Lee to provide a three transistor memory cell with where the second transistor is turned off through the second word line and the first transistor is turned on through the first word line so as to write data from a common bit line to the gate of the third transistor, so data can be written to the memory cell.
Regarding Claim 10, Lee and Kitagawa, as combined, teach the limitations of claim 8.
Kitagawa teaches a semiconductor device, wherein the write bit line first transitions from ground voltage to the supply voltage (Fig 6G: WBL, T3, T4) during the first transistor (Fig 1: WT) being turned on (Fig 6C: WWL, T4) and the to write the data with a logic 1.
Regarding Claim 11, Lee teaches the limitations of claim 7.
Lee, however, does not teach the specifically recited method of reading.
Kitagawa teaches a semiconductor device, wherein, with the first transistor being turned off through the first word line, the second transistor is configured to be turned on through the second word line to read data from the third transistor (Fig. 3B and Fig. 3C).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kitagawa to the teachings of Lee to provide a three transistor memory cell with a known method of reading so the memory cell’s data can be retrieved.
Regarding Claims 23, 25-26 and 29-32, these claims are rejected for the same reasons as claims 3, 5-6, 8, 5, 11 and 7 respectively.
Response to Arguments
Applicant's arguments filed on November have been fully considered but they are not persuasive.
Applicant’s argument deals solely with the added limitation that a back-end interconnect structure connects the middle-end interconnect structure to the common bit line. The middle-end interconnect structure is understood to be electrically connect source drain structures and the back-end interconnect structure is understood to electrically connect the middle end interconnect to the common bit line. The entire common bit lines disclosed in Lee encompass these limitations. As portions of the bit line connect source drain regions of the write and read access transistors of the memory cells and other portions of the common bit line connect the cells to each other to form a common bit line that can be driven to voltages. Thus, within the bit line exist both structures directly electrically and physically connected to one another connecting the cells to the common bit line. Therefore, the rejection under 35 USC 102(a)(1) is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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