DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the claims, filed 09/23/2025, are accepted and appreciated by the
Examiner.
Response to Arguments
Applicant’s arguments, see Remarks, filed 09/23/2025, with respect to the rejection(s) of claims under 35 U.S.C. 103 in view of Yoshino (US 20190086468 A1) and Laldin (US 20220291257 A1) have been fully considered and are persuasive in light of the amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yoshino (US 20190086468 A1) and Mayfield (US 20120169363 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 20190086468 A1) as modified by Mayfield (US 20120169363 A1).
With respect to claim 1,
Yoshino teaches,
Automated test equipment for testing a device under test (DUT), the automated test equipment comprising: (Abstract teaches “Automated test equipment can generate feed-forward temperature profile information for a device under test (DUT)”)
a test computer; (Para. [0029] teaches “the ATE 100 includes a processor (e.g., a test processor) 101 and memory 102.”)
wherein the test computer is operable to analyze the signal from the handler,
and provide, via the real-time handler interface, a synchronization signal to the handler for synchronizing an operation with the handler. (Para. [0108]. “The ATE 100 can interface with a handler 108 that provides a test platform or device interface board for the DUT 105. In embodiments, the handler 108 includes a cooling system 109 (e.g., an active thermal control, ATC, system) that can be used to cool the DUT 105 during testing.” (i.e. real-time handler interface) Para. [0031] teaches “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing.” (i.e. analyzing a signal.) Para. [0032] teaches “the processor 101 can also execute one or more applications 110 that can synchronize the junction temperature of the DUT 105 and cycles of the test pattern, and/or that can synchronize power consumption of the DUT and cycles of the test pattern, and/or that can be used to control cooling of the DUT using the cooling system 109 of the handler 108.” (i.e. Synchronization))
Yoshino does not explicitly teach,
A bidirectional dedicated real-time handler interface operable to provide a trigger signal to a handler that causes a temperature control function of the handler to execute during testing of the DUT, wherein the bidirectional dedicated real-time handler interface is operable to receive a signal from the handler.
Mayfield teaches,
A bidirectional dedicated real-time handler interface operable to provide a trigger signal to a handler that causes a temperature control function of the handler to execute during testing of the DUT, (Para. [0018] teaches “Microcontroller 111 produces a solenoid drive signal for temperature control. A pago communications interface transfers signals from microcontroller 111 to solenoid drive circuitry 121.” (i.e. the combination of the microcontroller and the communications interface is seen as A bidirectional dedicated real-time handler interface as it both receives and outputs a signal. Fig. 1 further shows a handler side 120.) Para. [0017] teaches “This invention uses the DUT thermal diodes for real time on-die temperature measurement.” (i.e. real time))
wherein the bidirectional dedicated real-time handler interface is operable to receive a signal from the handler. (Para. [0037] teaches “Handler 1100 includes test board 1110 holding plural DUTs 1113. I.sup.2C chip 1112 is connected to each DUT 1113 generating a temperature signal corresponding to a temperature sensed by thermal diodes on each DUT 1113. These temperature signals are supplied to controller box 1121. Controller box 1121 includes a microcontroller similar to microcontroller 111” (i.e. signal received by microcontroller.))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshino with a bidirectional dedicated real-time handler interface operable to provide a trigger signal to a handler that causes a temperature control function of the handler to execute during testing of the DUT, wherein the bidirectional dedicated real-time handler interface is operable to receive a signal from the handler such as that of Mayfield.
One of ordinary skill would have been motivated to modify Yoshino, because it would allow the interface to watch data from a controller and access measured data from the handler in real time and with high accuracy as seen in Para. [0017] of Mayfield.
With respect to claim 2,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the bidirectional dedicated real-time handler interface is operable to provide a test site specific signal to the handler to control the temperature control function. (Para. [0031] teaches “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing.” Para. [0032] teaches “cycles of the test pattern, and/or that can be used to control cooling of the DUT using the cooling system 109 of the handler 108.”)
With respect to claim 3,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the signal received from the handler comprises a test site specific signal. (Para. [0031] teaches “wherein the bidirectional dedicated real-time handler interface is operable to provide a test site specific signal to the handler to control the temperature control function.” Para. [0032] teaches “cycles of the test pattern, and/or that can be used to control cooling of the DUT using the cooling system 109 of the handler 108.”)
With respect to claim 4,
The automated test equipment as described in claim 1, wherein the bidirectional dedicated real-time handler interface is further operable to transmit an additional signal to the handler, the additional signal comprising at least one of: control information pertaining to a temperature control profile or to temperature regulation performed by the handler; information pertaining to a value measured by the automated test equipment; a test state parameter; and alarm information. (Para. [0057] teaches “the ATE receives signals indicative of junction temperatures of the DUT during execution of the test pattern on the DUT. In an embodiment, the signals are received by a differential sampler of the ATE, from a thermal sensor in the DUT, and the signals indicate voltage levels across the thermal sensor. The voltage levels are used to determine a temperature profile of the DUT during testing. In an embodiment, the temperature profile is stored in memory.” It is also shown that the interface 208 is transmitting that information to the ATE)
With respect to claim 5,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the test computer is further operable to modify a test flow for testing the DUT based on the signal received from the handler. (Para. [0054] teaches “In FIG. 8A, a test pattern is executed and only feedback control is used. For example, only feedback control may be used when a particular test pattern is first executed, to accumulate temperature data that can be used to identify which parts/cycles of the test pattern cause temperature surges, the magnitude of the temperature surge, and to generate a synchronized temperature profile for that test pattern.”)
With respect to claim 11,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the test computer is further operable to modify data handling of the DUT in response to receiving the signal from the handler. (Para, [0053] teaches “For example, only feedback control may be used when a particular test pattern is first executed, to accumulate temperature data that can be used to identify which parts/cycles of the test pattern cause temperature surges, the magnitude of the temperature surge, and to generate a synchronized temperature profile for that test pattern.”)
With respect to claim 12,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the test computer is further configured to log the signal received from the handler in memory. (Para. [0024] teaches “The steps are those utilizing physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.” Para. [0057] teaches “The voltage levels are used to determine a temperature profile of the DUT during testing. In an embodiment, the temperature profile is stored in memory.”)
With respect to claim 13,
Yoshino further teaches,
The automated test equipment as described in claim 1, wherein the test computer is further operable to react to the signal received from the handler in real-time. (Para. [0059] teaches “In another embodiment, real-time DUT temperature data is also provided to the cooling system.”)
With respect to claim 14,
Yoshino teaches,
A handler for testing a device under test (DUT) using an automated test equipment, the handler comprising: (Abstract teaches “Automated test equipment can generate feed-forward temperature profile information for a device under test (DUT)”)
a bidirectional real-time tester interface; (Para. [0029] teaches “In the example of FIG. 1, the ATE 100 includes a processor (e.g., a test processor) 101 and memory 102. The pin-electronics 103 deliver the test sequence to the DUT and sense the response of the DUT to this test stimulus.” Para. [0030] teaches “The ATE 100 can interface with a handler 108 that provides a test platform or device interface board for the DUT 105. In embodiments, the handler 108 includes a cooling system 109 (e.g., an active thermal control, ATC, system) that can be used to cool the DUT 105 during testing.” (i.e. ATE 100 represents a bidirectional interface as it receives and delivers signals.)
a circuit, (Para. [0029] teaches “the ATE 100 includes a processor (e.g., a test processor) 101 and memory 102.”)
wherein the real-time tester interface is operable to cause the circuit to: provide another signal to the automated test equipment via the real-time tester interface. (Para. [0031] teaches “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing.” (i.e. providing another signal.)
Yoshino does not explicitly teach,
wherein the real-time tester interface is operable to cause the circuit to: receive a trigger signal from the automated test equipment via the real-time tester interface; directly cause a temperature control function to execute in response to the received signal;
Mayfield teaches,
wherein the real-time tester interface is operable to cause the circuit to: receive a trigger signal from the automated test equipment via the real-time tester interface; (Para. [0037] teaches “Handler 1100 includes test board 1110 holding plural DUTs 1113. I.sup.2C chip 1112 is connected to each DUT 1113 generating a temperature signal corresponding to a temperature sensed by thermal diodes on each DUT 1113. These temperature signals are supplied to controller box 1121. Controller box 1121 includes a microcontroller similar to microcontroller 111” (i.e. signal received by microcontroller.))
directly cause a temperature control function to execute in response to the received signal; (Para. [0037] teaches “Controller box 1121 includes a microcontroller similar to microcontroller 111 and a solenoid drive box similar to solenoid drive circuitry 121 for each DUT. Controller box 1121 supplies PWM drive signals for the solenoids” (i.e. causing a temperature control function to execute as the drive signals control the temperature as seen in para. [0018]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshino wherein the real-time tester interface is operable to cause the circuit to: receive a trigger signal from the automated test equipment via the real-time tester interface; directly cause a temperature control function to execute in response to the received signal such as that of Mayfield.
One of ordinary skill would have been motivated to modify Yoshino, because it would allow the interface to watch data from a controller and access measured data from the handler in real time and with high accuracy as seen in Para. [0017] of Mayfield.
With respect to claim 15,
Yoshino further teaches,
The handler as described in claim 14, wherein the bidirectional real-time tester interface is further operable to cause the circuit to: receive a synchronization signal from the automated test equipment; and synchronize a function with the automated test equipment, other than the temperature control function, in response to the received synchronization signal. (Claim 18 teaches “further comprising synchronizing power consumption measurements of the DUT during execution of the test pattern on the DUT and the cycles of the test pattern.”)
With respect to claim 16,
Yoshino further teaches,
The handler as described in claim 14, wherein the bidirectional dedicated real-time tester interface is further operable to cause the circuit to: receive a test site specific signal from the automated test equipment; and control the temperature control function in response to the received test site specific signal. (Para. [0031] teaches “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing.” Para. [0032] teaches “cycles of the test pattern, and/or that can be used to control cooling of the DUT using the cooling system 109 of the handler 108.”)
With respect to claim 17,
Yoshino teaches,
A method of testing a device under test (DUT), the method comprising: (Abstract teaches “Automated test equipment can generate feed-forward temperature profile information for a device under test (DUT)”)
receiving a signal from the handler via the bidirectional real-time handler interface; (Para. [0033] teaches “block diagram illustrating the ATE 100, the DUT 105, and a device interface board (load board) 208 in embodiments according to the present invention. In the FIG. 2 embodiments, the ATE 100 includes a differential sampler 202, the DUT 105 is mounted on the load board 208 and includes a first thermal sensor 204, and the load board includes a relay 205 and a second thermal sensor 206.” Para. [0035] teaches “during testing of the DUT 105 (during execution of the test pattern 106), the ATE 100 uses a signal (e.g., voltage level) received from the first thermal sensor 204 and measured by the differential sampler 202 to determine temperature data of the DUT, specifically a temperature profile comprising junction temperatures of the DUT versus time.” (i.e. received signal from the handler the sensor from board 208.)
and analyzing the signal received from the handler. (Para. [0062] teaches “The resulting synchronized temperature profile can be used to diagnose a root cause of each temperature surge or spike that might occur. More specifically, the synchronized temperature profile can be used to determine which part of the executing test pattern caused a temperature surge so that personnel such as designers or manufacturing process engineers can determine, for example, whether the surge is due to a design flaw or to a manufacturing issue.”)
Yoshino does not explicitly teach,
transmitting a trigger signal to a handler via a bidirectional real-time handler interface to directly cause a temperature control function;
Mayfield teaches,
transmitting a trigger signal to a handler via a bidirectional real-time handler interface to directly cause a temperature control function; (Para. [0037] teaches “Controller box 1121 includes a microcontroller similar to microcontroller 111 and a solenoid drive box similar to solenoid drive circuitry 121 for each DUT. Controller box 1121 supplies PWM drive signals for the solenoids” (i.e. transmitting a trigger signal and causing a temperature control function to execute as the drive signals control the temperature as seen in para. [0018]) Fig. [0011] shows the handler.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshino with transmitting a trigger signal to a handler via a bidirectional real-time handler interface to directly cause a temperature control function such as that of Mayfield.
One of ordinary skill would have been motivated to modify Yoshino, because it would allow the interface to watch data from a controller and access measured data from the handler in real time and with high accuracy as seen in Para. [0017] of Mayfield.
With respect to claim 18,
Yoshino further teaches,
The method of claim 17, wherein the bidirectional real-time handler is dedicated, and further comprising transmitting an additional signal to the handler, the additional signal comprising at least one of: control information pertaining to a temperature control profile or to temperature regulation performed by the handler; information pertaining to a value measured by the automated test equipment; a test state parameter; and alarm information. (Para. [0057] teaches “the ATE receives signals indicative of junction temperatures of the DUT during execution of the test pattern on the DUT. In an embodiment, the signals are received by a differential sampler of the ATE, from a thermal sensor in the DUT, and the signals indicate voltage levels across the thermal sensor. The voltage levels are used to determine a temperature profile of the DUT during testing. In an embodiment, the temperature profile is stored in memory.” It is also shown that the interface 208 is transmitting that information to the ATE)
With respect to claim 19,
Yoshino further teaches,
The method of claim 17, wherein the bidirectional real-time handler is dedicated, and wherein the trigger signal comprises a test site specific signal, and wherein further the handler is configured to control the temperature control function in response to the received test site specific signal. (Para. [0031] teaches “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing.” Para. [0032] teaches “cycles of the test pattern, and/or that can be used to control cooling of the DUT using the cooling system 109 of the handler 108.”)
With respect to claim 20,
Yoshino further teaches,
The method of claim 17, wherein the bidirectional real-time handler is dedicated, and further comprising: transmitting a synchronization signal to the handler via the bidirectional real-time tester interface; and synchronizing a function with the handler, other than the temperature control function, using the synchronization signal. (Claim 18 teaches “further comprising synchronizing power consumption measurements of the DUT during execution of the test pattern on the DUT and the cycles of the test pattern.”)
Claims 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshino (US 20190086468 A1) as modified by Mayfield (US 20120169363 A1) as applied to claim 1 above, and further in view of Haefner (US 20160109485 A1).
With respect to claim 6,
The combination of Yoshino and Mayfield does not explicitly teach,
The automated test equipment as described in claim 1, wherein the test computer is further operable to operable to receive a deactivation signal from the handler.
Haefner teaches,
wherein the test computer is further operable to operable to receive a deactivation signal from the handler. (Para. [0031] teaches “The alert signal generated by the temperature monitor 222 is coupled to one or more power supplies 212 of the ATE 210 to control the operation of the one or more power supplies 212. For example, the power supply 212 of the ATE provides one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220, when the alert signal is de-asserted (e.g., logic high). When the alert signal is asserted, the power supply 212 turns off one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220. Accordingly, the alert signal advantageously turns off power during a high temperature condition to protect the ATE 110, the interface hoard 120, the DUT 130, the environmental control system the DUT handler and/or the like from damage.” (i.e. turning off voltage represents a received deactivation signal.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshino and Mayfield wherein the test computer is further operable to operable to receive a deactivation signal from the handler such as that of Haefner.
One of ordinary skill would have been motivated to modify the combination of Yoshino and Mayfield, because it would prevent the DUT from getting too hot and damaged as seen in Para. [0031] of Haefner.
With respect to claim 7,
The combination of Yoshino and Mayfield does not explicitly teach,
The automated test equipment as described in claim 6, wherein the test computer is further operable to operable to interrupt testing of the DUT in response to the deactivation signal.
Haefner teaches,
wherein the test computer is further operable to operable to receive a deactivation signal from the handler. (Para. [0031] teaches “The alert signal generated by the temperature monitor 222 is coupled to one or more power supplies 212 of the ATE 210 to control the operation of the one or more power supplies 212. For example, the power supply 212 of the ATE provides one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220, when the alert signal is de-asserted (e.g., logic high). When the alert signal is asserted, the power supply 212 turns off one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220. Accordingly, the alert signal advantageously turns off power during a high temperature condition to protect the ATE 110, the interface hoard 120, the DUT 130, the environmental control system the DUT handler and/or the like from damage.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshino and Mayfield wherein the test computer is further operable to operable to receive a deactivation signal from the handler such as that of Haefner.
One of ordinary skill would have been motivated to modify the combination of Yoshino and Mayfield, because stopping the test if the temperature was too high would prevent the DUT and testing equipment from getting damaged as seen in Para. [0031] of Haefner.
With respect to claim 8,
The combination of Yoshino and Mayfield does not explicitly teach,
The automated test equipment as described in claim 1, wherein the test computer is further operable to receive a temperature warning signal from the handler.
Haefner teaches,
wherein the test computer is further operable to receive a temperature warning signal from the handler. (Para. [0031] teaches “The alert signal generated by the temperature monitor 222 is coupled to one or more power supplies 212 of the ATE 210 to control the operation of the one or more power supplies 212. For example, the power supply 212 of the ATE provides one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220, when the alert signal is de-asserted (e.g., logic high). When the alert signal is asserted, the power supply 212 turns off one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220. Accordingly, the alert signal advantageously turns off power during a high temperature condition to protect the ATE 110, the interface hoard 120, the DUT 130, the environmental control system the DUT handler and/or the like from damage.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshino and Mayfield wherein the test computer is further operable to receive a temperature warning signal from the handler such as that of Haefner.
One of ordinary skill would have been motivated to modify the combination of Yoshino and Mayfield, because if the temperature was too high the DUT and testing equipment could get damaged as seen in Para. [0031] of Haefner.
With respect to claim 9,
The combination of Yoshino and Mayfield does not explicitly teach,
The automated test equipment as described in claim 1, wherein the test computer is further operable to interrupt testing of a test site in response to receiving a test site specific signal from the handler.
Haefner teaches,
wherein the test computer is further operable to interrupt testing of a test site in response to receiving a test site specific signal from the handler. (Para. [0031] teaches “The alert signal generated by the temperature monitor 222 is coupled to one or more power supplies 212 of the ATE 210 to control the operation of the one or more power supplies 212. For example, the power supply 212 of the ATE provides one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220, when the alert signal is de-asserted (e.g., logic high). When the alert signal is asserted, the power supply 212 turns off one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220. Accordingly, the alert signal advantageously turns off power during a high temperature condition to protect the ATE 110, the interface hoard 120, the DUT 130, the environmental control system the DUT handler and/or the like from damage.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshino and Mayfield wherein the test computer is further operable to interrupt testing of a test site in response to receiving a test site specific signal from the handler such as that of Haefner.
One of ordinary skill would have been motivated to modify the combination of Yoshino and Mayfield, because stopping the test if the temperature was too high would prevent the DUT and testing equipment from getting damaged as seen in Para. [0031] of Haefner.
With respect to claim 10,
The combination of Yoshino and Mayfield does not explicitly teach,
The automated test equipment as described in claim 1, wherein the test computer is further operable to deactivate a power supply of the DUT in response to receiving the signal from the handler.
Haefner teaches,
wherein the test computer is further operable to deactivate a power supply of the DUT in response to receiving the signal from the handler. (Para. [0031] teaches “The alert signal generated by the temperature monitor 222 is coupled to one or more power supplies 212 of the ATE 210 to control the operation of the one or more power supplies 212. For example, the power supply 212 of the ATE provides one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220, when the alert signal is de-asserted (e.g., logic high). When the alert signal is asserted, the power supply 212 turns off one or more supply potential voltages to one or more functional circuit blocks of the ATE 210, the DUT 230 through the interface board 220, and/or the one or more functional circuit blocks of the interface board 220. Accordingly, the alert signal advantageously turns off power during a high temperature condition to protect the ATE 110, the interface hoard 120, the DUT 130, the environmental control system the DUT handler and/or the like from damage.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Yoshino and Mayfield wherein the test computer is further operable to deactivate a power supply of the DUT in response to receiving the signal from the handler such as that of Haefner.
One of ordinary skill would have been motivated to modify the combination of Yoshino and Mayfield, because disconnecting the power source would prevent the DUT and testing equipment from getting damaged as seen in Para. [0031] of Haefner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to JOSHUA L FORRISTALL whose telephone number is 703-756-4554. The examiner
can normally be reached Monday-Friday 8:30 AM- 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use
the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached on 571-270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or
571-272-1000.
/JOSHUA L FORRISTALL/Examiner, Art Unit 2863
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2863