DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 02/02/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of SN18104149 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/11/2026, 03/16/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
The amendments filed on 01/02/2026 with respect to claims 1, 10 and 19-20 have been considered and are made of record.
During the interview, the Examiner indicated that Yoshino may not explicitly teach certain aspect of the claimed “trigger signal”, particularly with respect to generation in response to the test execution state during execution of the test program. However, upon further review of Yoshino, the Examiner finds that Yoshino does, in fact still teach or suggest the disputed limitations as applied to the rejection of amended claim 1 below.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 as being anticipated by Yoshino (U.S. Publication 20190086468).
Regarding claim 1, Yoshino discloses Automated test equipment for testing a device under test (DUT), the automated test equipment comprising: a test computer (101,102 / just the processor and memory); operable to execute a test flow for testing the DUT ([0031] teaches “the processor 101 is configured to provide signals… based on a sequence of instructions… that define a test program 106.. test vectors that make up a test pattern” thereby executing a test flow for testing the DUT);
and a real-time handler interface coupled to a handler (Figure 1), (Paragraphs [0029], [0030] /note pin-electronics 103 and any other features part of the interface between the ATE and the handler), wherein the real-time handler interface is operable to:
transmit a trigger signal from the test computer to the handler to trigger a temperature control function of the handler during execution of the test flow (Claim 10), (Paragraph [0050] /note the feed-forward signal is the trigger signal which triggers temperature control by the handler, [0048] teaches that the handler cooling system performs temperature control while a test pattern is being executed. The feed-forward temperature profile constitutes a trigger signal because it is provided from the test computer to the handler and is used by the handler cooling system to perform temperature control, including initiating and adjusting cooling, and such temperature control occurs during execution of the test flow); and
transmit a synchronization signal from the test computer to the handler to synchronize a DUT temperature measurement function of the test flow executed by the handler in real-time ([0037] teaches that power consumption measurements and temperature control measurements are synchronized with cycles of the test patters, thereby providing time aligned measurement information corresponding to execution of the test flow, [0048] teaches that junction temperature measurement are provided to the handle in real time during execution of the test pattern for use in temperature control. The synchronized measurements constitute a synchronization signal because they are transmitted from the test computer to the handle and provide time aligned information corresponding to cycles of the test pattern, thereby synchronizing operation of the handle with execution of the test flow and the provision of junction temperature measurements during execution corresponds to a DUT temperature measurement function of the test flow executed by the handle in real time).
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Regarding claims 2, 11, Yoshino further discloses wherein the real-time handler interface is further operable to perform an active synchronization with the handler based on the synchronization signal, and wherein the active synchronization is free of any wait insertions ([0050-0052] “the cooling system 109 accepts both the feed-forward temperature profile information and real-time temperature measurement data, in order to respond to both the anticipated thermal profile as described above and real-time device-specific thermal data. The feed-forward temperature profile aligns the cooling system 109 to the expected device (DUT) temperature. Because the cooling system 109 is pre-aligned to the expected device temperature based on the feed-forward temperature profile, the real-time adjustments become fine-tuning steps that are inherently faster and more accurate. The power consumption measurements synchronized with cycles of the test pattern can also be used to further enhance thermal control during testing” this will avoid any wait and continues processing).
Regarding claims 3, 12, Yoshino further discloses wherein the real-time handler interface is operable to transmit calibration timing information to the handler, and wherein the handler is operable to perform calibration of the handler based on the calibration timing information ([0043] “in the calibration phase, junction temperature is measured by the second thermal sensor 206. The second thermal sensor 206 is optimized for thermal measurement and receives or measures the voltage level of the first thermal sensor 204. At the same time, the voltage level of the first thermal sensor 204 is measured by the digital sampler 202. The two voltage level values are used to determine a calibration factor that can be subsequently used for the measurement of junction temperature with the first thermal sensor 204. To minimize any noise-induced errors, the temperature of the DUT 105 is stabilized before taking these two measurements, with the inclusion of a low-pass-filter 604”).
Regarding claims 4, 13, Yoshino further discloses wherein the real-time handler interface is further operable to transmit another signal indicating that the DUT is powered or biased in a predetermined manner ([0037] “the ATE 100 synchronizes the temperature profile and the cycles of the test pattern 106 to produce a profile 210 of junction temperature versus cycle. The profile 210 may be referred to herein as a synchronized temperature profile. In an embodiment, power consumption measurements of the DUT 105 during execution of the test pattern 106 on the DUT and the cycles of the test pattern are also synchronized”).
Regarding claims 5, 14, Yoshino further discloses wherein the real-time handler interface is further operable to transmit another signal when a predetermined test condition is satisfied ([0048] “during execution of a test pattern on the DUT 105, the junction temperatures determined by the second thermal sensor 206 are fed to the cooling (e.g., ATC) system 109. That is, the handler 108 receives direct junction temperature readings in real time as feedback data that can be used to adjust the degree of cooling provided by the cooling system 109 while a test pattern is being executed. For example, if the feedback data indicates that the junction temperature is increasing during testing, then the cooling system 109 can increase the degree of cooling”).
Regarding claims 6, 15, Yoshino further discloses wherein the real-time handler interface is further operable to provide the synchronization signal to the handler to trigger a temperature measurement by the handler ([0048] “during execution of a test pattern on the DUT 105, the junction temperatures determined by the second thermal sensor 206 are fed to the cooling (e.g., ATC) system 109. That is, the handler 108 receives direct junction temperature readings in real time as feedback data that can be used to adjust the degree of cooling provided by the cooling system 109 while a test pattern is being executed. For example, if the feedback data indicates that the junction temperature is increasing during testing, then the cooling system 109 can increase the degree of cooling”).
Regarding claims 7, 16, Yoshino further discloses wherein the handler is operable to perform a thermal diode calibration according to the synchronization signal, and wherein the thermal diode calibration comprises a delta temperature measurement, and wherein further the real-time handler interface is further operable to transmit real- time measurement timing information to the handler for performing the thermal diode calibration ([0032-0035]).
Regarding claims 8, 17, Yoshino further discloses wherein the synchronization signal comprises time information for performing a measurement by the handler ([0035-0038] synchronized signal inherently a periodic signal effectively coordinating their operations in time and frequency).
Regarding claims 9, 18, Yoshino further discloses wherein the synchronization signal comprises at least one of: test state information; and device state information ([0031] “The processor 101 is configured to provide signals to the DUT 105 on the basis of a sequence of instructions that define and implement a test program 106 that can, for example, be stored or buffered in the memory 102. The instructions define test vectors that make up a test pattern. The processor 101 is configured to map a test vector into a set (waveform) of signal states or signal transitions (cycles) that are executed on or by the DUT 105 during testing. A cycle may correspond to a single test vector”).
Regarding claim 10, the structure recited is intrinsic to the method recited in claim 1, as disclosed by Yoshino (U.S. Publication 20190086468) as the recited structure will be used during the normal operation, as discussed above with regard to claim 1, Yoshina further discloses an handler for testing a device under test (fig. 1 (100, 108)), a circuit (the ATE 100 includes processer 101 and memory 102 fig. 1).
Regarding claim 19, the method recited is intrinsic to the apparatus recited in claim 1, as disclosed by Yoshino (U.S. Publication 20190086468) as the recited method steps will be performed during the normal operation of the apparatus, as discussed above with regard to claim 1.
Regarding claim 20, the method recited is intrinsic to the apparatus recited in claim 10, as disclosed by Yoshino (U.S. Publication 20190086468) as the recited method steps will be performed during the normal operation of the apparatus, as discussed above with regard to claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAQI R NASIR whose telephone number is (571)270-1425. The examiner can normally be reached 9AM-5PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAQI R NASIR/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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