DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/9/2026 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities.
The Examiner suggests the following amendment to correct an apparent typographic error:
“…a third raised section formed of a second material that is different from the first material…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 27, the phrase "such that" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
As used in claim 27, the phrase “such that” appears to be a result of the preceding arrangement configuration of claim elements, rather than further limiting the claimed subject matter.
For the purpose of compact prosecution, the Examiner has interpreted claim 27 to be consistent with the cited prior art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7 9-12, 22-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sheck (Patent No. US 5,311,061 A).
Regarding claim 1, Sheck teaches a semiconductor wafer (40), comprising:
a front surface (fig. 21);
a plurality of active component positions (col. 4 line 66: IC component regions formed on 40); and
at least one composite alignment mark (col. 6 lines 16-17: alignment key 10) arranged on the front surface (fig. 4-4: 10 formed on front surface of 40) and indicating a unique orientation of the semiconductor wafer (col. 3 lines 27-28: alignment keys enable determination of rotational orientation);
wherein the at least one composite alignment mark comprises a first portion (col. 3 line 65: metal layer 14) that comprises a first raised section and a second raised section formed of a first material (fig. 4-4: metal layer 14 includes a plurality of sections raised above surface of 40), and a second portion (col. 5 line 67 through col. 6 line 1: passivation layer 44 and/or 16) that is positioned laterally adjacent the first portion and that comprises a third raised section formed of a second material that is different form the first material (fig. 4-4: passivation layer 44/16 comprises at least one section positioned laterally adjacent to 14 and raised above surface of 40),
wherein the second raised section laterally surrounds and is spaced apart from the first raised section (fig. 4-4: 44/16 laterally surrounds and is spaced apart from at least a first portion of 14),
wherein the third raised section covers regions of the front surface between the first raised section and the second raised section (fig. 4-4: 44/16 covers front surface regions of 40 between portions of 14).
Regarding claim 2, Sheck teaches the semiconductor wafer of claim 1, wherein the first and second portions have complementary shapes (fig. 4-4: 44 fills gaps between sections of 14, meeting the broadest reasonable interpretation of “complementary shapes”).
Regarding claim 3, Sheck teaches the semiconductor wafer of claim 1, wherein the at least one composite alignment mark is rotationally asymmetric (col. 3 lines 27-28 & figs. 1, 3, 4-4: alignment keys configured to identify rotational orientation of the semiconductor wafer).
Regarding claim 5, Sheck teaches the semiconductor wafer of claim 1, wherein the second portion is contiguous with the first portion (fig. 4-4: 44/16 contiguous with portions of 14).
Regarding claim 6, Sheck teaches the semiconductor wafer of claim 1, wherein the second portion overlaps the first portion (fig. 4-4: 44/16 overlaps sidewalls and/or top surface of 14).
Regarding claim 7, Sheck teaches the semiconductor wafer of claim 1, wherein the second portion is spaced apart a distance from the first portion (figs. 1, 4-4: at least a portion of 44/16 spaced apart from at least one portion of 14).
Regarding claim 9, Sheck teaches the semiconductor wafer of claim 1, wherein the first material comprises a metal or alloy (col. 3 lines 55-56: 14 comprises metal).
Regarding claim 10, Sheck teaches the semiconductor wafer of claim 1, wherein the first material comprises Al or comprises Cu or is formed of an AlCu alloy or comprises Au, W, a W alloy, Ti or TiN (col. 4 lines 49-51, col. 5 lines 32-33: 14 comprises Al or Al with copper).
Regarding claim 11, Sheck teaches the semiconductor wafer of claim 1, wherein the second material comprises an electrically insulating material (col. 5 lines 59-63: 44 comprises electrically insulating material).
Regarding claim 12, Sheck teaches the semiconductor wafer of claim 11, wherein the electrically insulating material comprises an imide or an epoxy or a nitride or an oxide or a multilayer structure comprising a nitride layer and an oxide layer (col. 5 lines 59-63: 44 comprises electrically insulating material of silicon nitride or silicon oxide).
Regarding claim 22, Sheck teaches the semiconductor wafer of claim 1, wherein the second raised section has a form of a closed border or frame having a square or rectangular form (fig. 1: second/outer portion of 14 includes a substantially rectangular shape), with sections extending in a first longitudinal direction that are connected by sections extending in a second longitudinal direction transverse to the first longitudinal direction (fig: boundary of outer portion of 14 includes interconnected horizontal and vertical sections).
Regarding claim 23, Sheck teaches the semiconductor wafer of claim 22, wherein the sections of the frame have substantially the same width and height on all four sides of the frame (figs. 1, 4-4: boundaries of outer portion of 14 have substantially equal width and height).
Regarding claim 24, Sheck teaches the semiconductor wafer of claim 1, wherein the second portion of the at least one composite alignment mark further comprises a fourth raised section (16) formed of the second material (col. 5 line 67 through col. 6 lines 1), and wherein the fourth raised section laterally surrounds the second raised section (fig. 4-4: 16 surrounds 14).
Regarding claim 25, Sheck teaches the semiconductor wafer of claim 24, wherein the fourth raised section has a form of a closed border or frame having a square or rectangular form (fig. 1: 16 has a closed border with a substantially rectangular shape), with sections extending in a first longitudinal direction that are connected by sections extending in a second longitudinal direction transverse to the first longitudinal direction (fig. 1: 16 includes horizontal and vertical connected portions).
Regarding claim 26, Sheck teaches the semiconductor wafer of claim 25, wherein the sections of the frame have substantially the same width and height on all four sides of the frame (figs. 1, 4-4: 16 includes equivalent heights on all sides).
Regarding claim 27, Sheck teaches the semiconductor wafer of claim 24, wherein the second portion of the at least one composite alignment mark (44/16) is spaced apart from the first portion of the at least one composite alignment mark by a gap (fig. 4-4: at least portion 16 spaced apart from 14), such that side faces of the first and second raised sections are spaced apart from side faces of the third and fourth raised sections (not given patentable weight; see 35 USC §112(b) rejection above).
Regarding claim 28, Sheck teaches the semiconductor wafer of claim 1, wherein the first raised section (center portion of 14) is rotationally asymmetric about an axis which extends substantially perpendicular to the front surface and indicates the unique orientation of the semiconductor wafer (fig. 1: 14 includes a non-symmetric shape, and is therefore rotationally asymmetric about an axis perpendicular to surface of 40), and
wherein the third raised section (14) has a rotationally asymmetric shape that is complementary or inverse of the first raised section and indicates the unique orientation of the semiconductor wafer (figs. 1, 4-4: 44 has a shape complimentary to 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (PG Pub. No. US 2005/0263855 A1) in view of Chen et al. (PG Pub. No. US 2009/0294995 A1).
Regarding claim 1, Fu teaches a semiconductor wafer (¶ 0016: 110), comprising:
a front surface (figs. 1-2: upper surface);
a plurality of active component positions (¶ 0013: plurality of integrated circuit regions 120); and
at least one composite alignment mark (¶ 0014: pattern 140, including registration mark 160) arranged on the front surface and indicating a unique orientation of the semiconductor wafer (¶ 0018 & fig. 1);
wherein the at least one composite alignment mark comprises a first portion that comprises a first section (¶ 0016: 160) and a second section formed of a first material (¶ 0014 & fig. 1: outline/boundary of 142, comprising at least a portion of 150), and a second portion (¶ 0014: 142) that is positioned laterally adjacent the first portion (fig. 1: 142 arranged laterally adjacent to 160) and that comprises a third section formed of a second material (¶ 0021 & fig. 2: 142 comprises at least one material),
wherein the second section laterally surrounds and is spaced apart from the first section (fig. 1: boundary/outline surrounds 160),
wherein the third section covers regions of the front surface between the first section and the second section (fig. 1: 142 covers upper surface of 110 between 160 and outline/boundary of 142).
Fu does not explicitly teach the first, second and third sections are raised, or the second material is different from the first material.
Chen teaches a composite alignment mark (¶ 0012: overlay mark) including first and second raised sections of a first material (¶ 0031 & figs. 1B, 2C among others: 114), the first raised section laterally surrounding and spaced apart from the first raised section (fig. 2C: outer portion of 114 surrounds inner portion of 114), and a third raised section (fig. 2C: 108a/110a and/or 120; since 108a/110a include an upper surface above top surface of substrate 100, the broadest reasonable interpretation of ‘raised section’ is met) formed of a second material different from the first material (¶¶ 0030-0031: 108a/110a and/or 120 comprises different material than 114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first, second and third sections of Fu with raised sections of different material, as a means to optimize alignment accuracy of a lithography process (Chen, ¶ 0035).
PNG
media_image1.png
460
564
media_image1.png
Greyscale
PNG
media_image2.png
358
428
media_image2.png
Greyscale
Regarding claim 2, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the first and second portions have complementary shapes (Chen, fig. 1B among others: 114 includes a plurality of concentric shapes).
PNG
media_image3.png
255
386
media_image3.png
Greyscale
Regarding claim 3, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the at least one composite alignment mark is rotationally asymmetric (Fu, figs. 1, 4a-4g: mark configured to be asymmetric with respect to origin of region 120 and/or die 100 and/or substrate 110).
Regarding claim 5, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second portion is contiguous with the first portion (Fu, fig. 1: 142 contiguous with boundary/outline of 142).
Regarding claim 6, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second portion overlaps the first portion (Fu, fig. 1: 142 overlaps outline/boundary of 142).
Regarding claim 7, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second portion is spaced apart a distance from the first portion (Chen, fig. 2C: 120 spaced apart from 114).
Regarding claim 8, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein at least one composite alignment mark is positioned in an inactive portion of the semiconductor wafer outside of the plurality of active component positions and/or in a scribe line region that is adjacent one of the active component positions and/or in a dummy component position (Fu, ¶ 0014: 140 positioned in die-corner-circuit-forbidden (DCCF) region 130).
Regarding claim 9, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the first material comprises a metal or alloy (Fu, ¶ 0017: boundary of 142 includes portion of seal ring 150, which comprises metal such as 182.184.186).
Regarding claim 10, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the first material comprises Al or comprises Cu or is formed of an AICu alloy or comprises Au, W, a W alloy, Ti or TiN (Fu, ¶ 0017: boundary of 142 comprises copper, tungsten, titanium nitride etc.).
Regarding claim 11, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second material comprises an electrically insulating material (Fu, ¶ 0025: 142 includes fill dielectric; and/or Chen, ¶ 0030: 108a/110a comprise insulating material).
Regarding claim 22, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second raised section has a form of a closed border or frame having a square or rectangular form (Chen, fig. 1B: 108a/110a includes a square form), with sections extending in a first longitudinal direction that are connected by sections extending in a second longitudinal direction transverse to the first longitudinal direction (108a sections extend in 1st longitudinal direction transverse to 2nd longitudinal direction of 110a sections).
Regarding claim 23, Fu in view of Chen teaches the semiconductor wafer of claim 22, wherein the sections of the frame have substantially the same width and height on all four sides of the frame (Chen, fig. 2C: 108a/110a have same widths and heights).
Regarding claim 24, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the second portion of the at least one composite alignment mark further comprises a fourth raised section formed of the second material, and wherein the fourth raised section laterally surrounds the second raised section (Chen, figs. 1B, 2C: 104a/106a, including a top surface elevated with respect to surface of 100, formed of same material as 108a/110a and laterally surrounds middle portion of 114).
PNG
media_image4.png
364
429
media_image4.png
Greyscale
Regarding claim 25, Fu in view of Chen teaches the semiconductor wafer of claim 24, wherein the fourth raised section has a form of a closed border or frame having a square or rectangular form (Chen, fig. 1B: 104a/106a has a form of a closed square), with sections extending in a first longitudinal direction that are connected by sections extending in a second longitudinal direction transverse to the first longitudinal direction (Chen, fig. 1B: 104a and 106a extending in 1st and 2nd longitudinal directions).
Regarding claim 26, Fu in view of Chen teaches the semiconductor wafer of claim 25, wherein the sections of the frame have substantially the same width and height on all four sides of the frame (Chen, fig. 2C: 104a/106a have substantially the same width and height with respect to surface of 100).
Regarding claim 28, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the first raised section is rotationally asymmetric about an axis which extends substantially perpendicular to the front surface and indicates the unique orientation of the semiconductor wafer (Fu, figs. 1, 3i: intermediate portion, as modified to include the raised profile of Chen, rotationally asymmetric with respect to surface of 100), and
wherein the third raised section has a rotationally asymmetric shape that is complementary or inverse of the first raised section and indicates the unique orientation of the semiconductor wafer (Fu, fig. 3i: central portion, as modified to include the raised profile of Chen, includes a shape complimentary to intermediate portion and rotationally asymmetric with respect to surface of 100).
PNG
media_image5.png
273
300
media_image5.png
Greyscale
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Fu in view of Chen as applied to claim 11 above, and further in view of Ghosh et al. (PG Pub. No. US 2019/0244911 A1).
Regarding claim 12, Fu in view of Chen teaches the semiconductor wafer of claim 11, comprising an electrically insulating material (Fu, ¶ 0017: fill dielectric of 142, and/or Chen, ¶ 0030: insulating material of 108a/110a).
Fu in view of Chen does not teach wherein the electrically insulating material comprises an imide or an epoxy or a nitride or an oxide or a multilayer structure comprising a nitride layer and an oxide layer.
Ghosh teaches a semiconductor wafer (¶ 0032: 100) including a second material (¶ 0036: 104) arranged between first and second portions of a first material (¶ 0048 & figs. 6, 8: 104 arranged between metal patterns 108a/108b/108c/108d), the electrically insulating material comprises an imide or an epoxy or a nitride or an oxide or a multilayer structure comprising a nitride layer and an oxide layer (¶ 0038: in at least one embodiment, 104 comprises oxide material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the electrically insulating material of Fu in view of Chen to comprise oxide material, as a means to electrically isolate alignment patterns from various devices, such as transistors (Ghosh, ¶ 0005).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, selecting the material of Ghosh for the electrically insulating structure of Fu and/or Chen would a matter of obvious design choice.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fu in view of Chen as applied to claim 1 above, and further in view of Roh (PG Pub. No. US 2020/0271979 A1).
Regarding claim 13, Fu in view of Chen teaches the semiconductor wafer of claim 1, wherein the active component positions each comprise a transistor device (Fu, ¶ 0033) and the second portion is formed in an electrically insulating layer (Fu, ¶ 0016) arranged on the front surface of the active component positions of the semiconductor wafer (Fu, fig. 1: 160 formed on upper surface of 110 adjacent to region 120).
Fu in view of Chen further teaches dummy metal pattern 140 in the DCCF region 130 may be fabricated simultaneously with the multilayer interconnects in the integrated circuit region 120 (Fu, ¶¶ 0017, 0024).
Fu in view Chen does not teach the first portion is formed in a same electrically conductive layer as a layer of a source pad and/or a gate pad.
Roh teaches a first portion of an alignment mark is formed in a same electrically conductive layer as a layer of a source pad and/or a gate pad (¶ 0111: AM formed from gate and/or pad wiring).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first portion of Fu in view Chen in a same electrically conductive layer as a layer of a source pad and/or a gate pad, as a means to optimize manufacturing efficiency by minimizing the number of process steps, such as layer formation and/or patterning.
Claims 8 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Sheck in view of Ohara (PG Pub. No. US 2009/0194842 A1).
Regarding claim 8, Sheck teaches the semiconductor wafer of claim 1, comprising at least one composite alignment mark (10).
Sheck does not teach wherein at least one composite alignment mark is positioned in an inactive portion of the semiconductor wafer outside of the plurality of active component positions and/or in a scribe line region that is adjacent one of the active component positions and/or in a dummy component position.
Ohara teaches an alignment mark (¶ 0092: 311) positioned in a scribe line region of a semiconductor wafer (¶ 0089 & fig. 21: 311 positioned in dicing line region 310 of a substrate) that is adjacent to active component positions (¶ 0090 & fig. 21: 310 adjacent to positions of active chips 300).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to position the composite alignment marks of Sheck in an inactive portion or a scribe line region of the semiconductor wafer, as a means to effectively use active areas on the substrate without a waste (Ohara, ¶ 0092), improving manufacturing efficiency and/or reducing manufacturing cost.
Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70. In the instant case, the placement of Sheck’s composite alignment mark adjacent to active areas on the substrate represents a mere rearrangement of parts, and involves only routine skill.
Regarding claim 29, Sheck teaches a semiconductor wafer (col. 4 line 34: 40), comprising:
a front surface (fig. 4-4: top surface of 40);
a plurality of active component positions (col. 4 lines 65-66: many components of an IC device have been formed on substrate 40); and
a composite alignment mark (col. 6 lines 16-17: alignment key 10) arranged on the front surface (fig. 4-4: 10 arranged on top surface of 40) and indicating a unique orientation of the semiconductor wafer (col. 3 lines 27-28: alignment keys enable determination of rotational orientation);
wherein the composite alignment mark comprises a first portion that comprises at least one raised section formed of a first material (col. 3 line 65 & fig. 4-4: metal layer 14 includes at least one portion raised with respect to surface of 40) and a second portion that is positioned laterally adjacent the first portion and that comprises at least one raised section formed of a second material that is different form the first material (col. 5 line 55 & fig. 4-4: passivation layer 44 positioned laterally adjacent to 14 and comprises at least one portion raised with respect to surface of 44).
Sheck does not teach wherein the composite alignment mark is positioned in a scribe line region of the semiconductor wafer that is adjacent one of the active component positions.
Ohara teaches an alignment mark (¶ 0092: 311) positioned in a scribe line region of a semiconductor wafer (¶ 0089 & fig. 21: 311 positioned in dicing line region 310 of a substrate) that is adjacent to active component positions (¶ 0090 & fig. 21: 310 adjacent to positions of active chips 300).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to position the composite alignment marks of Sheck in a scribe line region of the semiconductor wafer, as a means to effectively use active areas on the substrate without a waste (Ohara, ¶ 0092), improving manufacturing efficiency and/or reducing manufacturing cost.
Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70. In the instant case, the placement of Sheck’s composite alignment mark adjacent to active areas on the substrate represents a mere rearrangement of parts, and involves only routine skill.
Allowable Subject Matter
Claims 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“the first raised section includes a first leg extending in a first longitudinal direction, a second leg extending substantially orthogonal to the first leg in a second longitudinal direction and intersecting the first leg to form a cross, and a third leg extending from a distal end of the first leg on one side only in the second longitudinal direction and substantially parallel to the second leg” as recited in claim 20.
Claim 21 depends on claim 20, and is allowable for implicitly including the subject matter above.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-13 and 22-29 have been considered but are moot because the new ground of rejection does not rely on any interpretation of reference(s) applied in the prior rejection of record for any teaching or matter specifically challenged in the argument, and/or any newly cited prior art references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights