Prosecution Insights
Last updated: October 25, 2026
Application No. 18/104,483

SEMICONDUCTOR WAFER AND METHOD FOR FABRICATING A SEMICONDUCTOR WAFER

Final Rejection §103
Filed
Feb 01, 2023
Priority
Mar 02, 2022 — EU 22159808.9
Examiner
TURNER, BRIAN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
4 (Final)
83%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
647 granted / 776 resolved
+15.4% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
50 currently pending
Career history
835
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
61.3%
+21.3% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 776 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 29 is rejected under 35 U.S.C. 103 as being unpatentable over Sheck (Patent No. US 5,311,061 A) in view of Ohara (PG Pub. No. US 2009/0194842 A1). Regarding claim 29, Sheck teaches a semiconductor wafer (col. 4 line 34: 40), comprising: a front surface (fig. 4-4: top surface of 40); a plurality of active component positions (col. 4 lines 65-66: many components of an IC device have been formed on substrate 40); and a composite alignment mark (col. 6 lines 16-17: alignment key 10) arranged on the front surface (fig. 4-4: 10 arranged on top surface of 40) and indicating a unique orientation of the semiconductor wafer (col. 3 lines 27-28: alignment keys enable determination of rotational orientation); wherein the composite alignment mark comprises a first portion that comprises at least one raised section formed of a first material (col. 3 line 65 & fig. 4-4: metal layer 14 includes at least one portion raised with respect to surface of 40) and a second portion that is positioned laterally adjacent the first portion and that comprises at least one raised section formed of a second material that is different from the first material (col. 5 line 55 & fig. 4-4: passivation layer 44 positioned laterally adjacent to 14 and comprises at least one portion raised with respect to surface of 44). Sheck does not teach wherein the composite alignment mark is positioned in a scribe line region of the semiconductor wafer that is adjacent one of the active component positions. Ohara teaches an alignment mark (¶ 0092: 311) positioned in a scribe line region of a semiconductor wafer (¶ 0089 & fig. 21: 311 positioned in dicing line region 310 of a substrate) that is adjacent to active component positions (¶ 0090 & fig. 21: 310 adjacent to positions of active chips 300). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to position the composite alignment marks of Sheck in a scribe line region of the semiconductor wafer, as a means to effectively use active areas on the substrate without a waste (Ohara, ¶ 0092), improving manufacturing efficiency and/or reducing manufacturing cost. Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70. In the instant case, the placement of Sheck’s composite alignment mark adjacent to active areas on the substrate represents a mere rearrangement of parts, and involves only routine skill. Allowable Subject Matter Claims 1-3, 5-13 and 20-28 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations stating: “at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer; wherein the at least one composite alignment mark comprises a first portion that comprises a first raised section and a second raised section formed of a first material, and a second portion that is positioned laterally adjacent the first portion and that comprises a third raised section formed of a second material that is different from the first material, wherein the second raised section laterally surrounds and is spaced apart from the first raised section, wherein the third raised section covers regions of the front surface between the first raised section and the second raised section” as recited in claim 1. Sheck (US 5,311,061 A) teaches a composite alignment mark (10) on a front surface of a semiconductor wafer (col. 3 lines 27-28), the composite alignment mark including a plurality of raised portions (14, 16, 44) comprising different materials. However, metal layer 14 is a single contiguous layer with two slots 11 and 12 formed therein. No section of metal layer 14 laterally surrounds and is spaced apart from another section of metal layer 14. Therefore, Sheck fails to teach the limitation of “the second raised section laterally surrounds and is spaced apart from the first raised section” as recited in claim 1. Miao et al. (PG Pub. No. US 2015/0035161 A1) teaches a semiconductor wafer (40) including an alignment mark (43) disposed in a scribe region (fig. 4: 43 arranged in scribe region 49X/49Y), and further teaches an embodiment (figs. 13A-13B) in which a scribe region (130) includes a scribe line (139) adjacent to a raised pattern (1205). However, Miao fails to teach an alignment mark with first and second raised sections laterally spaced apart and comprising different materials. Claims 2-3 and 5-28 depend on claim 1, and are allowed for implicitly including the allowable subject matter above. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant’s arguments, see page 7, filed 8/4/2026, with respect to the 35 USC § 112 rejection of claim 27 and formal claim objection to claim 29 have been fully considered and are persuasive. Accordingly, the 35 USC § 112 rejection and formal claim objection have been withdrawn. Applicant's arguments with respect to the 35 USC § 103 rejection of claim 29 have been fully considered but they are not persuasive. Regarding the Applicant’s argument stating: “If two sections of Sheck's metal layer 14 correspond to the first raised section and the second raised section of the first portion, both of these sections comprise the same metal. However, passivation layer 44/16 is described as "silicon nitride deposited by a plasma enhanced chemical vapor deposition process, or alternatively, a silicon oxide material which can be dealt with either phosphorous, boron, or both."6 Contrary to what is asserted in lines 12-13 on page 4 of the Office Action, Sheck's passivation layer 44/16 does not correspond to the second raised section of the first portion of the composite alignment mark.”, the Examiner respectfully disagrees. Sheck teaches a first raised portion including layer 14, and a second raised portion including 16 and/or 44. See below for a possible example. Since the first raised section includes only metal, and the second raised section includes both metal and a passivation material, the claimed feature of ‘the composite alignment mark comprises a first portion that comprises at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion and that comprises at least one raised section formed of a second material that is different from the first material’ is met. PNG media_image1.png 270 496 media_image1.png Greyscale Regarding the Applicant’s argument stating: “Sheck's alignment key 10 is intentionally designed to be part of the final product (die), to enable die alignment and to provide an ion trap against ionic contamination. If Sheck's alignment key 10 were moved to the scribe line region of the wafer, as suggested on page 17 of the Office Action, the alignment key 10 would be damaged or even completely removed during the wafer singulation (dicing) process. As a result, Sheck's semiconductor die 34 would no longer contain a functional alignment key 10, defeating the main purpose of the Sheck invention and rendering Sheck's alignment key 10 unsatisfactory for its intended purpose”, the Examiner respectfully disagrees. Sheck teaches an alignment key in a corner region of a die, in a location suitable to prevent ionic contamination from adjacent active circuit components. Therefore, Shecks’s alignment mark is not positioned in an active die region, but rather adjacent to an active die region. Chen teaches an alignment mark in a scribe line region proximal to a peripheral region of a die. As the width of the scribe line is not disclosed, Chen does not explicitly teach the entire scribe line region, including the alignment mark, is removed. Rather, Chen teaches positioning the alignment mark in a non-active region adjacent to an active die region (e.g. region 301). Therefore, Chen could be combined with Sheck to provide the alignment mark of Sheck in a non-active scribe line region (310), the alignment mark remaining in a region adjacent to an active circuit such as 301 or 302 of Chen. See below for possible examples. PNG media_image2.png 448 618 media_image2.png Greyscale PNG media_image3.png 448 618 media_image3.png Greyscale Accordingly, the Applicant’s arguments are not persuasive, and the 35 USC §103 rejection of claim 29 is maintained. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kunishima (US 2010/0072578 A1) teaches an alignment mark (36) arranged in a scribe region of a semiconductor wafer (fig. 10), where a scribe line divides the alignment mark (figs. 6A-6B among others) such that portions of the alignment mark (343a-343b) remain as part of the final singulated device. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN TURNER/Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 2 earlier events
Oct 01, 2025
Response Filed
Jan 02, 2026
Final Rejection mailed — §103
Feb 02, 2026
Response after Non-Final Action
Feb 09, 2026
Request for Continued Examination
Feb 17, 2026
Response after Non-Final Action
May 28, 2026
Non-Final Rejection mailed — §103
Aug 04, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+4.1%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 776 resolved cases by this examiner. Grant probability derived from career allowance rate.

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