DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/18/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-9, 13-18, and 21, 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US Pub. 2021/0375901) in view of Pagliato et al. (US Pub. 2023/0201744) and further in view of Lee et al. (US Pub. 2022/0028461).
Regarding claim 1, Fig. 4 of Oh discloses a non-volatile memory device comprising:
a first semiconductor layer [CP] comprising a first cell region [MCA] in which a first memory cell array [CR1] is disposed, a second cell region [MCA] in which a second memory cell array [CR2] is disposed, and a first metal pad layer [within CP], wherein the first memory cell array and the second memory cell array each comprise a plurality of word lines [WL, Fig. 2] stacked in a vertical direction [VD, Fig. 2], a plurality of memory cells [clearly shows in Fig. 2] respectively connected to the plurality of word lines [WL, Fig. 2], and a plurality of bit lines [BL, Fig. 2]; and
a second semiconductor layer [LP1] comprising a page buffer circuit region [the whole region comprises both PBC] in which a page buffer circuit connected [as shows in Fig. 5, page buffer region (LP1) is connected to memory cells array region (CP)] to the first memory cell array [memory array in CP region] and the second memory cell array is disposed, and a second metal pad layer [DCC1, Fig. 5], wherein the second semiconductor layer [LP1] is connected to the first semiconductor layer [CP] in the vertical direction [clearly shows in Fig. 4] through bonding [similar to pad DCC1, 16a in Fig. 5] by the first metal pad layer and the second metal pad layer,
Oh discloses all claimed invention, but does not specifically shows a first switch connected between a page buffer and a first bit line connected to the first memory array, and a second switch connected between the page buffer and a second bit line connected to the second cell array, and the page buffer comprising a sensing latch connected to the first switch and the second switch in common. However, Fig. 9 of Pagliato discloses a page buffer [PAGE BUFFER] circuit having a first switch [switch controls by Sele] connected between a page buffer [PAGE BUFFER] and a first bit line [BLE] connected to the first memory array [ARRAY connects to BLE], and a second switch [switch controls by signal Selo] connected between the page buffer [PAGE BUFFER] and a second bit line [BLO] connected to the second cell array [array connects to BLO], and the page buffer [102, PAGE BUFER] comprising a sensing latch [903] connected to the first switch and the second switch in common.
Oh discloses all claimed invention, but does not specifically shows the page buffer circuit includes at least one transistor that overlaps a boundary region within the first semiconductor layer. However, Fig. 2B of Lee shows a memory device having a boundary region [A1] between a first cell region [MG1] and a second cell region [MG2], and page buffer circuit [combination of R1, 150, and R2, within layer L1], wherein the page buffer circuit [combination of R1, 150, and R2] includes at least one transistor [150 or X1 in Fig. 6B] that overlaps a boundary region [as shows in Fig. 2B, region 150, where the transistor is located overlaps a boundary region A1].
. As shows in Fig. 4, the region LP1 is considered a page buffer circuit] overlaps a boundary region [SR, Fig. 4] between the first cell region [CR1] and the second cell region [CR2] when viewed from the vertical direction [VD direction as shows in Fig. 4]. In addition, it would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange the page buffer circuit so that it overlaps a boundary region between the first cell region and the second cell region, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee’s page buffer circuit having at least one transistor overlapping the boundary to Oh’s page buffer in order to create a common page buffer circuit for a purpose of sharing between two different memory regions.
Regarding claim 3, Fig. 5 of Oh discloses wherein the first semiconductor layer [CP] comprises: wires electrically connected to the plurality of bit lines [vertical line connects to BL]; and first bonding pads [the pad connects to BL] connected to the wires in a region overlapping the boundary region when viewed from the vertical direction and forming the first metal pad layer [CP], and the second semiconductor layer [LP1] comprises second bonding pads [DCC1 and 16a] connected to the first bonding pads in a region overlapping the boundary region when viewed from the vertical direction, the second bonding pads forming the second metal pad layer, and connected to the page buffer circuit [PBC].
Regarding claim 4, Fig. 5 of Oh discloses wherein the first metal pad layer [CP] comprises wires electrically connected to the plurality of bit lines [BL] in a region that does not overlap [region within CR1 region] the boundary region when viewed from the vertical direction and extending to a region [SR region, through 24 or 22] overlapping the boundary region when viewed from the vertical direction [VD].
Regarding claim 5, Fig. 5 of Oh discloses wherein the first metal pad layer [CP] comprises first pads, which are electrically connected to the plurality of bit lines [pad that connects to BL], and are connected to wires that form the first metal pad layer in a region [within region CR1] that does not overlap the boundary region in the vertical direction [CR1 does not overlap boundary region SR], wherein the wires are connected to the page buffer circuit [PBC] by extending to a region [extend to SR region] overlapping the boundary region [extend through line 24 or 22] when viewed from the vertical direction.
Regarding claim 7, Fig. 5 of Oh discloses wherein the second semiconductor layer further comprises first to fourth metal wire layers [14a, 14b, 14c, 14d], and the first switch [TR1] and the page buffer are connected to each other through a wire formed in one layer from among the first to fourth metal wire layers [clearly shows in Fig. 5] and the second metal pad layer [16a] and extending in a first horizontal direction and a second horizontal direction.
Regarding claim 8, Fig. 5 of Oh discloses wherein the second semiconductor layer further comprises first to fourth metal wire layers [14a, 14b, 14c, 14d], and the first switch [TR1] and the page buffer [PBC] are connected to each other by wires formed in at least two layers selected from the first to fourth metal wire layers and the second metal pad layer [LP1].
Regarding claim 9, Fig. 5 of Oh discloses wherein the first switch and the second switch [within region PBC] share a source/drain region [Jn11] corresponding to a node connected to the page buffer.
Regarding claim 13, Fig. 10 of Oh discloses wherein: a portion of the page buffer is disposed to overlap the first cell region [where BL1 and BL2 are] when viewed from the vertical direction [VD], and the remaining portion [whole SP1 region] of the page buffer is disposed to overlap the second cell region [CR2 region in Fig. 4] when viewed from the vertical direction.
Regarding claim 14, Fig. 10 of Oh discloses wherein: the first switch [T1] and the second switch [T2] are arranged to overlap the second cell region [CP] when viewed from the vertical direction, and the page buffer [PBC] is disposed to overlap the first cell region or the boundary region when viewed from the vertical direction.
Regarding claim 15, Fig. 10 of Oh discloses wherein: the first switch [T1] is disposed to overlap the first cell region [CR1, Fig. 4] when viewed from the vertical direction, the second switch [similar to T1, but in the right PBC region] is disposed to overlap the second cell region [CR2, Fig. 4] when viewed from the vertical direction, and the page buffer [PBC] is disposed to overlap the boundary region when viewed from the vertical direction.
Regarding claim 16, Fig. 1 of Oh discloses a first cache latch [within circuit 123] connected to the page buffer [PB] and configured to input/output data for the first memory cell array [110]; and a second cache latch [similar to 123 for the second memory array] connected to the page buffer and configured to input/output data for the second memory cell array.
Regarding claim 17, Fig. 1 of Oh discloses wherein: the first cache latch [within 123] is disposed to overlap the first cell region [110 or CR1 in Fig. 4] when viewed from the vertical direction, and the second cache latch [similar to 123 for right PBC] is disposed to overlap the second cell region when viewed from the vertical direction.
Regarding claim 18, Fig. 1 of Oh discloses during a read operation [paragraph 0153] or a program operation on the first memory cell array and the second memory cell array, a time period in which the first switch is turned on and a time period in which the second switch is turned on do not overlap, and, during an erase operation on the first memory cell array and the second memory cell array, a time period in which the first switch is turned on and a time period in which the second switch is turned on overlap each other. In addition, MPEP 2114(II) explains the “Manner of operating the device does not differentiate apparatus claim from the prior art.” The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Oh’s device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I). Where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter my, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. see In re Swinehart, 439 F.2d 210, 213 (CCPA 1971).This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I))].
Regarding claim 21, Fig. 4 of Oh discloses non-volatile memory device comprising:
a first semiconductor layer [CP] comprising a first cell region [CR1] in which a first memory cell array is disposed and a second cell region [CR2] in which a second memory cell array is disposed, wherein the first memory cell array and the second memory cell array each comprises a plurality of word lines [WL in Fig. 2] stacked in a vertical direction [VD], a plurality of memory cells [clearly shows in Fig. 2] respectively connected to the plurality of word lines [WL], and a plurality of bit lines [BL], and wherein the first cell region [CR1] is horizontally separated from the second cell region [CR2] by a boundary region [SR] disposed therebetween; and
a second semiconductor layer [LP1] disposed under the first semiconductor layer [CP] and comprising a page buffer circuit region [combination of two PBC regions] in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed [as shows in Fig. 1 or Fig. 5],
Oh discloses all claimed invention, but does not specifically shows a first switch connected between a page buffer and a first bit line connected to the first memory array, and a second switch connected between the page buffer and a second bit line connected to the second cell array, and the page buffer comprising a sensing latch connected to the first switch and the second switch in common. However, Fig. 9 of Pagliato discloses a page buffer [PAGE BUFFER] circuit having a first switch [switch controls by Sele] connected between a page buffer [PAGE BUFFER] and a first bit line [BLE] connected to the first memory array [ARRAY connects to BLE], and a second switch [switch controls by signal Selo] connected between the page buffer [PAGE BUFFER] and a second bit line [BLO] connected to the second cell array [array connects to BLO], and the page buffer [102, PAGE BUFER] comprising a sensing latch [903] connected to the first switch and the second switch in common.
Oh discloses all claimed invention, but does not specifically shows the page buffer circuit includes at least one transistor that overlaps a boundary region within the first semiconductor layer. However, Fig. 2B of Lee shows a memory device having a boundary region [A1] between a first cell region [MG1] and a second cell region [MG2], and page buffer circuit [combination of R1, 150, and R2, within layer L1], wherein the page buffer circuit [combination of R1, 150, and R2] includes at least one transistor [150 or X1 in Fig. 6B] that overlaps a boundary region [as shows in Fig. 2B, region 150, where the transistor is located overlaps a boundary region A1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee’s page buffer circuit having at least one transistor overlapping the boundary to Oh’s page buffer in order to create a common page buffer circuit for a purpose of sharing between two different memory regions.
Regarding claim 23, Fig. 1 of Oh discloses a first cache latch [within circuit 123] connected to the page buffer [PB] and configured to input/output data for the first memory cell array [110]; and a second cache latch [similar to 123 for the second memory array] connected to the page buffer and configured to input/output data for the second memory cell array.
Regarding claim 24, Fig. 1 of Oh discloses wherein the page buffer circuit comprises: a first page buffer comprising a sensing latch [PB] connected to a first bit line [BL] connected to the first memory cell array [110]; a second page buffer [similar to PB for second region] comprising a sensing latch connected to a second bit line [similar to BL] connected to the second memory cell array; and a cache latch [within 123] connected to the first page buffer and the second page buffer.
Regarding claim 25, Fig. 1 of Oh discloses during a read operation [paragraph 0153] or a program operation on the first memory cell array and the second memory cell array, a time period in which the first switch is turned on and a time period in which the second switch is turned on do not overlap, and, during an erase operation on the first memory cell array and the second memory cell array, a time period in which the first switch is turned on and a time period in which the second switch is turned on overlap each other. In addition, MPEP 2114(II) explains the “Manner of operating the device does not differentiate apparatus claim from the prior art.” The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Oh’s device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I). Where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter my, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. see In re Swinehart, 439 F.2d 210, 213 (CCPA 1971).This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicants are reminded that argument of counsel is not evidence (see MPEP 2145(I))].
Regarding claim 26, Fig. 4 of Oh discloses a non-volatile memory device comprising:
a first memory cell array [CR1] comprising a plurality of word lines [WL shows in Fig. 2] and a plurality of first bit lines [BL as shows in Fig. 2];
a second memory cell array [CR2] comprising a plurality of word lines [WL in Fig. 2] and a plurality of second bit lines [BL as shows in Fig. 2], the second memory cell array [CR2] horizontally separated from the first memory cell array [CR1] by a boundary region [SR] disposed therebetween; and
a page buffer circuit [combination of PBC] shared by the first memory cell array [CR1] and the second memory cell array [CR2],
Oh discloses all claimed invention, but does not specifically shows a first switch connected between a page buffer and a first bit line connected to the first memory array, and a second switch connected between the page buffer and a second bit line connected to the second cell array, and the page buffer comprising a sensing latch connected to the first switch and the second switch in common. However, Fig. 9 of Pagliato discloses a page buffer [PAGE BUFFER] circuit having a first switch [switch controls by Sele] connected between a page buffer [PAGE BUFFER] and a first bit line [BLE] connected to the first memory array [ARRAY connects to BLE], and a second switch [switch controls by signal Selo] connected between the page buffer [PAGE BUFFER] and a second bit line [BLO] connected to the second cell array [array connects to BLO], and the page buffer [102, PAGE BUFER] comprising a sensing latch [903] connected to the first switch and the second switch in common.
Oh discloses all claimed invention, but does not specifically shows the page buffer circuit includes at least one transistor that overlaps a boundary region within the first semiconductor layer. However, Fig. 2B of Lee shows a memory device having a boundary region [A1] between a first cell region [MG1] and a second cell region [MG2], and page buffer circuit [combination of R1, 150, and R2, within layer L1], wherein the page buffer circuit [combination of R1, 150, and R2] includes at least one transistor [150 or X1 in Fig. 6B] that overlaps a boundary region [as shows in Fig. 2B, region 150, where the transistor is located overlaps a boundary region A1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee’s page buffer circuit having at least one transistor overlapping the boundary to Oh’s page buffer in order to create a common page buffer circuit for a purpose of sharing between two different memory regions.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-5, 7-9, 13-18, and 21, 23-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825