Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/104,789 filed on October 28, 2025.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
5. Applicant’s election without traverse of claims 1-8, 13-22 w.r.t. the species I (Fig. 2) in the reply filed on 10/28/2025 is acknowledged.
6. Claims 9-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/28/2025.
Specification
7. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device Comprising Bonded a Plurality of Semiconductor Structures Along With Conductive Layers and Bonding Pads”.
Claim Objections
8. Claims 1, 6, 19, 21 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or missing period (.) in place of (,) at the end of the limitation:
1. (Currently Amended) A semiconductor device comprising:
a first semiconductor structure including a first conductive layer and four first bonding pads connected to the first conductive layer; and
a second semiconductor structure including a second conductive layer and four second bonding pads connected to the second conductive layer,
wherein the four first bonding pads are configured to be disposed to have respective centers each overlapping four intersections that are formed by two virtual first straight lines extending in parallel in a first direction and two virtual second straight lines extending in parallel in a second direction intersecting the first direction, where each of the four first bonding pads has four quadrants divided by a first straight line and a second straight line, and
wherein, when the first semiconductor structure and the second semiconductor structure are normally aligned, the four second bonding pads are configured to be disposed to have respective centers that are displaced in directions from the respective centers of the four first bonding pads toward different quadrants.
6. (Currently Amended) The semiconductor device according to claim 1, wherein each of the four first bonding pads and each of the four second bonding pads are configured to have same area and shape in a plan view.
19. (Currently Amended) The semiconductor device according to claim 1, when the first semiconductor structure (112) and the second semiconductor structure (212) are normally aligned, a center of the first conductive layer () and a center of the second conductive layer overlap with each other
21. (Currently Amended) A semiconductor device comprising:
a first semiconductor structure including a first conductive layer and a plurality of first bonding pads; and
a second semiconductor structure including a second conductive layer and a plurality of second bonding pads,
wherein the plurality of the first bonding pads are connected to the first conductive layer and the plurality of the second bonding pads are connected to the second conductive layer,
wherein centers of the plurality of first bonding pads aligned in a first direction lie on a first virtual straight line and in a second direction lie on a second virtual straight line, and
wherein, when the first semiconductor structure and the second semiconductor structure are normally aligned, one vertex of each of the plurality of second bonding pads are disposed to contact an intersecting point between the first vertical straight line and the second virtual straight line from a plan view.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1-7, 13-22 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Shen et al. (US 2022/0037268 A1).
Regarding independent claim 1, Shen et al. teaches a semiconductor device comprising (Figs. 18-19):
a first semiconductor structure (112, para [0046]) including a first conductive layer (236 denoted in Fig. 14) and four first bonding pads (142, para [0046]) connected to the first conductive layer (236); and
a second semiconductor structure (212, para [0046]) including a second conductive layer (232, see Fig. 16b) and four second bonding pads (242, para [0046]) connected to the second conductive layer (232),
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wherein the four first bonding pads (142) are configured to be disposed to have respective centers (midpoints) each overlapping four intersections that are formed by two virtual first straight lines (L1: shown in the following figure) extending in parallel in a first direction (shown in figure below) and two virtual second straight lines (L2: shown in the following figure) extending in parallel in a second direction (shown in figure below) intersecting the first direction, where each of the four first bonding pads (142) has four quadrants (1st - 4th quadrants, shown in the following figure) divided by the first straight line and the second straight line (shown in the following figure), and
wherein, when the first semiconductor structure (112) and the second semiconductor structure (212) are normally aligned, the four second bonding pads (242) are configured to be disposed to have respective centers (midpoints) that are displaced in directions from the respective centers (midpoints) of the four first bonding pads (142) toward different quadrants (1st - 4th quadrants).
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Regarding claim 2, Shen et al. teaches wherein (Fig. 18), the four second bonding pads (242) are configured to partially overlap the different quadrants (1st - 4th quadrants) of the four first bonding pads (142), respectively.
Regarding claim 3, Shen et al. teaches wherein (Fig. 18), overlapping areas between the four first bonding pads (142) and the four second bonding pads (242) are same as each other.
Regarding claim 4, Shen et al. teaches wherein (Fig. 18), the four first bonding pads (142) and the four second bonding pads (242) are configured to form a metal-to-metal bond (metal-to-metal bonding, para [0046]).
Regarding claim 5, Shen et al. teaches wherein (Fig. 18):
the first semiconductor structure (112) further includes a first insulating layer (138 denoted in Fig. 15) filled between the four first bonding pads (142),
the second semiconductor structure (212) further includes a second insulating layer (238 denoted in Fig. 15) filled between the four second bonding pads (242), and
the first insulating layer (138) and the second insulating layer (238) are configured to form an insulator-to-insulator bond (fusion or dielectric bonding, para [0046]-[0048]).
Regarding claim 6, Shen et al. teaches wherein (Fig. 18), each of the four first bonding pads (142) and each of the four second bonding pads (242) are configured to have same area and shape in a plan view (see Fig. 19).
Regarding claim 7, Shen et al. teaches wherein (Fig. 18), an area of each first bonding pad (142) overlapping a corresponding second bonding pad (242) is configured to be substantially same as an area of the second bonding pad (242) overlapping the first bonding pad (142).
Regarding claim 13, Shen et al. teaches wherein (Fig. 18), when the first semiconductor structure (112) and the second semiconductor structure (212) are misaligned, a total overlapping area between the four first bonding pads (142) and the four second bonding pads (242) is maintained.
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Regarding claim 14, Chen et al. teaches wherein (Fig. 18), the first semiconductor structure (112) further includes one or more first conductive layers (236 denoted in Fig. 14), and the four first bonding pads (142) are configured to be connected to each of the one or more first conductive layers (236 denoted in Fig. 14).
Regarding claim 15, Chen et al. teaches wherein (Fig. 18), 15. The semiconductor device according to claim 1, wherein, when the four first bonding pads (142) form a bonding pad group, the first conductive layer (236) is configured to be connected to one or more bonding pad groups (this is a functional limitation/an intended use).
Regarding claim 16, Shen et al. teaches wherein (Fig. 18), the first semiconductor structure (112 SRAM, para [0021]) and the second semiconductor structure (212 SRAM, para [0044]) include same type of memory (both are SRAM).
Regarding claim 17, Shen et al. teaches wherein (Fig. 18), the first semiconductor structure (112 SRAM, para [0021]) and the second semiconductor structure (212 DRAM, para [0044]) include different types of memory (SRAM vs. DRAM).
Regarding claim 18, Shen et al. teaches wherein (Fig. 18), one of the first semiconductor structure (112) and the second semiconductor structure (212 DRAM) includes a memory and the other of the first semiconductor structure (112 logic device, para [0021]) and the second semiconductor structure (212) includes a peripheral circuit (logic device) for driving the memory.
Regarding claim 19, Shen et al. teaches wherein (Fig. 18), when the first semiconductor structure (112) and the second semiconductor structure (212) are normally aligned, a center of the first conductive layer () and a center of the second conductive layer overlap with each other.
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Regarding claim 20, Shen et al. teaches wherein (Fig. 18), when the first semiconductor structure (112) and the second semiconductor structure (212) are misaligned, one of the centers (midpoint/middle) of the first conductive layer (236) and the second conductive layer (232) displaces (misaligns) within a predetermined limit from the other of the centers (midpoint/middle) of the first conductive layer (236) and the second conductive layer (232).
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Regarding independent claim 21, Shen et al. teaches a semiconductor device comprising (Figs. 18-19):
a first semiconductor structure (112, para [0046]) including a first conductive layer (236 denoted in Fig. 14) and a plurality of first bonding pads (142, para [0046]); and
a second semiconductor structure (212, para [0046]) including a second conductive layer (232, see Fig. 16b) and a plurality of second bonding pads (242, para [0046]),
wherein the plurality of the first bonding pads (142) are connected to the first conductive layer (236) and the plurality of the second bonding pads (242) are connected to the second conductive layer (232),
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wherein centers (midpoints/middle) of the plurality of first bonding pads (142) aligned in a first direction (shown in the following figure) lie on a first virtual straight line (L1: shown in the following figure) and in a second direction (shown in the following figure) lie on a second virtual straight line (L2: shown in the following figure), and
wherein, when the first semiconductor structure (112) and the second semiconductor structure (212) are normally aligned, one vertex of each of the plurality of second bonding pads (242) are disposed to contact an intersecting point between the first vertical straight line (L1) and the second virtual straight line (L2) from a plan view (or top view, see Fig. 19).
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Regarding independent claim 22, Shen et al. teaches a semiconductor device comprising (Figs. 18-19):
a first semiconductor structure (112, para [0046]) including a first conductive layer (236 denoted in Fig. 14) and four first bonding pads (142, para [0046]) connected to the first conductive layer (236); and
a second semiconductor structure (212, para [0046]) including a second conductive layer (232, see Fig. 16b) and four second bonding pads (242, para [0046]) connected to the second conductive layer (232),
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wherein, when the first semiconductor structure (112) and the second semiconductor structure (212) are normally aligned, the four first bonding pads (142) are configured to be disposed to have respective centers that are displaced from respective centers of the four second bonding pads (242) (this is a functional limitation/an intended use), and
wherein a total contact area (overlapped area of 142/242, see Fig. 19) of the four first bonding pads (142) to the four second bonding pads (242) is maintained even with misalignment (see Fig. 18: between 142 and 242) of the first semiconductor structure (112) and the second semiconductor structure (212).
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
15. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
16. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 2022/0037268 A1) as applied to claim 6 above, and further in view of Chen et al. (US 2015/0279888 A1).
Regarding claim 8, Shen et al. teaches all of the limitations of claim 6 from which this claim depends.
Shen et al. teaches wherein (Fig. 18), the four first bonding pads (142) and the four second bonding pads (242) are configured to have a circular shape (see Fig. 19) in a plan view,
wherein an area of each first bonding pad (142) overlapping a corresponding second bonding pad (242) correspond to 1/4 of an area of each first bonding pad (142) or each second bonding pad (242).
Shen et al. is explicitly silent of disclosing wherein, the four first bonding pads and the four second bonding pads are configured to have a square shape in a plan view.
Chen et al. discloses wherein (Figs. 9-10), the four first bonding pads (124, see Fig. 9) and the four second bonding pads (224) are configured to have a square shape (see Fig. 10) in a plan view.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Chen et al., and modify the circular shape of the bonding pads towards the square shape of Shen et al., in order to achieve larger contact area, high current transmission, better durability and resistance to wear. Also it has been modifiable/changeable in shape, per In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), see MPEP 2144.04, IV changes in shape: B.
Examiner’s Note
17. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
19. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812